/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 18 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, argument 29 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); 44 MachineInstr *DefMI = LastMI; local 57 DefMI = &*I; 61 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && 63 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
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H A D | MLxExpansionPass.cpp | 94 MachineInstr *DefMI = MRI->getVRegDef(Reg); local 96 if (DefMI->getParent() != MBB) 98 if (DefMI->isCopyLike()) { 99 Reg = DefMI->getOperand(1).getReg(); 101 DefMI = MRI->getVRegDef(Reg); 104 } else if (DefMI->isInsertSubreg()) { 105 Reg = DefMI->getOperand(2).getReg(); 107 DefMI = MRI->getVRegDef(Reg); 113 return DefMI; 146 MachineInstr *DefMI local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetSchedule.cpp | 185 const MachineInstr *DefMI, unsigned DefOperIdx, 189 return TII->defaultDefLatency(SchedModel, *DefMI); 194 OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx, 198 unsigned DefClass = DefMI->getDesc().getSchedClass(); 205 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI); 213 std::max(InstrLatency, TII->defaultDefLatency(SchedModel, *DefMI)); 217 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); 218 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); 241 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit() 242 && !DefMI 184 computeOperandLatency( const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const argument 245 << *DefMI << " (Try with MCSchedModel.CompleteModel set to false)"; local 290 computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *DepMI) const argument [all...] |
H A D | LiveRangeEdit.cpp | 72 const MachineInstr *DefMI, 74 assert(DefMI && "Missing instruction"); 76 if (!TII.isTriviallyReMaterializable(*DefMI, aa)) 91 MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def); local 92 if (!DefMI) 94 checkRematerializable(OrigVNI, DefMI, aa); 188 MachineInstr *DefMI = nullptr, *UseMI = nullptr; local 194 if (DefMI && DefMI != MI) 198 DefMI 71 checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI, AAResults *aa) argument [all...] |
H A D | MachineTraceMetrics.cpp | 628 const MachineInstr *DefMI; 632 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp) 633 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} 641 DefMI = DefI->getParent(); 771 const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg); 773 const TraceBlockInfo &DefTBI = BlockInfo[DefMI->getParent()->getNumber()]; 776 unsigned Len = LIR.Height + Cycles[DefMI].Depth; 796 BlockInfo[Dep.DefMI->getParent()->getNumber()]; 801 unsigned DepCycle = Cycles.lookup(Dep.DefMI) [all...] |
H A D | PHIElimination.cpp | 166 MachineInstr *DefMI = MRI->getVRegDef(VirtReg); local 167 if (!DefMI) 178 MachineBasicBlock *DefMBB = DefMI->getParent(); 202 for (MachineInstr *DefMI : ImpDefs) { 203 Register DefReg = DefMI->getOperand(0).getReg(); 206 LIS->RemoveMachineInstrFromMaps(*DefMI); 207 DefMI->eraseFromParent(); 440 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) 441 if (DefMI->isImplicitDef()) 442 ImpDefs.insert(DefMI); [all...] |
H A D | RegisterCoalescer.cpp | 813 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def); 814 if (!DefMI) 816 if (!DefMI->isCommutable()) 818 // If DefMI is a two-address instruction then commuting it will change the 820 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); 823 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) 836 if (!TII->findCommutedOpIndices(*DefMI, UseOpIdx, NewDstIdx)) 839 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); 864 << *DefMI); 868 MachineBasicBlock *MBB = DefMI 1097 MachineInstr *DefMI = LIS->getInstructionFromIndex(PVal->def); local 2451 computeWriteLanes(const MachineInstr *DefMI, bool &Redef) const argument 2553 const MachineInstr *DefMI = nullptr; local [all...] |
H A D | DetectDeadLanes.cpp | 359 const MachineInstr &DefMI = *Def.getParent(); local 360 if (lowersToCopies(DefMI)) { 377 for (const MachineOperand &MO : DefMI.uses()) { 387 } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) { 404 unsigned OpNum = DefMI.getOperandNo(&MO); 409 if (DefMI.isImplicitDef() || Def.isDead()) 513 // Transfer UsedLanes to operands of DefMI (backwards dataflow).
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H A D | TwoAddressInstructionPass.cpp | 208 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) { 209 if (DefMI.getParent() != BB || DefMI.isDebugValue()) 212 Ret = &DefMI; 213 else if (Ret != &DefMI) 336 MachineInstr *DefMI = &MI; local 342 if (!isPlainlyKilled(DefMI, Reg, LIS)) 351 DefMI = Begin->getParent(); 356 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 877 for (MachineInstr &DefMI [all...] |
H A D | TargetInstrInfo.cpp | 1110 const MachineInstr &DefMI) const { 1111 if (DefMI.isTransient()) 1113 if (DefMI.mayLoad()) 1115 if (isHighLatencyDef(DefMI.getOpcode())) 1136 const MachineInstr &DefMI, 1142 unsigned DefClass = DefMI.getDesc().getSchedClass(); 1228 /// Both DefMI and UseMI must be valid. By default, call directly to the 1231 const MachineInstr &DefMI, 1235 unsigned DefClass = DefMI.getDesc().getSchedClass(); 1243 const InstrItineraryData *ItinData, const MachineInstr &DefMI) cons 1135 hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const argument 1230 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64CondBrTuning.cpp | 66 bool tryToTuneBranch(MachineInstr &MI, MachineInstr &DefMI); 143 MachineInstr &DefMI) { 145 if (MI.getParent() != DefMI.getParent()) 151 switch (DefMI.getOpcode()) { 195 // There must not be any instruction between DefMI and MI that clobbers or 197 if (isNZCVTouchedInInstructionRange(DefMI, MI, TRI)) 200 LLVM_DEBUG(DefMI.print(dbgs())); 204 NewCmp = convertToFlagSetting(DefMI, IsFlagSetting); 250 // There must not be any instruction between DefMI and MI that clobbers or 252 if (isNZCVTouchedInInstructionRange(DefMI, M 142 tryToTuneBranch(MachineInstr &MI, MachineInstr &DefMI) argument 313 MachineInstr *DefMI = getOperandDef(MI.getOperand(0)); local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsOptimizePICCall.cpp | 280 MachineInstr *DefMI = MRI.getVRegDef(Reg); local 282 assert(DefMI); 284 // See if DefMI is an instruction that loads from a GOT entry that holds the 286 if (!DefMI->mayLoad() || DefMI->getNumOperands() < 3) 289 unsigned Flags = DefMI->getOperand(2).getTargetFlags(); 295 assert(DefMI->hasOneMemOperand()); 296 Val = (*DefMI->memoperands_begin())->getValue(); 298 Val = (*DefMI->memoperands_begin())->getPseudoValue();
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86OptimizeLEAs.cpp | 352 for (auto DefMI : List) { 354 int64_t AddrDispShiftTemp = getAddrDispShift(MI, MemOpNo, *DefMI, 1); 366 MRI->getRegClass(DefMI->getOperand(0).getReg())) 373 int DistTemp = calcInstrDist(*DefMI, MI); 383 BestLEA = DefMI; 529 MachineInstr *DefMI; local 532 if (!chooseBestLEA(Insns->second, MI, DefMI, AddrDispShift, Dist)) 542 DefMI->removeFromParent(); 543 MBB->insert(MachineBasicBlock::iterator(&MI), DefMI); local 544 InstrPos[DefMI] [all...] |
H A D | X86CallFrameOptimization.cpp | 621 MachineInstr &DefMI = *MRI->getVRegDef(Reg); 625 if ((DefMI.getOpcode() != X86::MOV32rm && 626 DefMI.getOpcode() != X86::MOV64rm) || 627 DefMI.getParent() != FrameSetup->getParent()) 630 // Make sure we don't have any instructions between DefMI and the 632 for (MachineBasicBlock::iterator I = DefMI; I != FrameSetup; ++I) 636 return &DefMI;
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetSchedule.h | 174 unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, 198 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | Utils.cpp | 351 auto *DefMI = MRI.getVRegDef(Reg); local 352 auto DstTy = MRI.getType(DefMI->getOperand(0).getReg()); 355 while (DefMI->getOpcode() == TargetOpcode::COPY) { 356 Register SrcReg = DefMI->getOperand(1).getReg(); 360 DefMI = MRI.getVRegDef(SrcReg); 363 return DefinitionAndSourceRegister{DefMI, DefSrcReg}; 382 MachineInstr *DefMI = getDefIgnoringCopies(Reg, MRI); local 383 return DefMI && DefMI->getOpcode() == Opcode ? DefMI 457 const MachineInstr *DefMI = MRI.getVRegDef(Val); local [all...] |
H A D | CombinerHelper.cpp | 326 MachineIRBuilder &Builder, MachineInstr &DefMI, MachineOperand &UseMO, 342 if (InsertBB == DefMI.getParent()) { 343 MachineBasicBlock::iterator InsertPt = &DefMI; 551 bool CombinerHelper::isPredecessor(const MachineInstr &DefMI, argument 553 assert(!DefMI.isDebugInstr() && !UseMI.isDebugInstr() && 555 assert(DefMI.getParent() == UseMI.getParent()); 556 if (&DefMI == &UseMI) 560 MachineBasicBlock::const_iterator I = DefMI.getParent()->begin(); 561 for (; &*I != &DefMI && &*I != &UseMI; ++I) 562 return &*I == &DefMI; 325 InsertInsnsWithoutSideEffectsBeforeUse( MachineIRBuilder &Builder, MachineInstr &DefMI, MachineOperand &UseMO, std::function<void(MachineBasicBlock *, MachineBasicBlock::iterator, MachineOperand &UseMO)> Inserter) argument 567 dominates(const MachineInstr &DefMI, const MachineInstr &UseMI) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFMIPeephole.cpp | 464 MachineInstr *DefMI; local 488 DefMI = MRI->getVRegDef(SrcReg); 489 if (DefMI) 495 DefMI = MRI->getVRegDef(SrcReg); 497 if (!DefMI) 511 if (DefMI->isPHI()) { 514 for (unsigned i = 1, e = DefMI->getNumOperands(); i < e; i += 2) { 515 MachineOperand &opnd = DefMI->getOperand(i); 531 } else if (!TruncSizeCompatible(TruncSize, DefMI->getOpcode())) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.h | 190 // Replace the instruction with single LI if possible. \p DefMI must be LI or 192 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI, 196 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI, 202 MachineInstr &DefMI) const; 206 unsigned ConstantOpNo, MachineInstr &DefMI, 221 bool isDefMIElgibleForForwarding(MachineInstr &DefMI, 226 const MachineInstr &DefMI, 231 const MachineInstr &DefMI, 298 const MachineInstr &DefMI, unsigned DefIdx, 309 const MachineInstr &DefMI, [all...] |
H A D | PPCMIPeephole.cpp | 375 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1); local 377 if (!DefMI) 380 unsigned DefOpc = DefMI->getOpcode(); 390 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI); 413 unsigned DefReg1 = DefMI->getOperand(1).getReg(); 414 unsigned DefReg2 = DefMI->getOperand(2).getReg(); 415 unsigned DefImmed = DefMI->getOperand(3).getImm(); 459 .add(DefMI->getOperand(1)); 464 (DefMI->getOperand(2).getImm() == 0 || 465 DefMI 485 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); local 548 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); local [all...] |
H A D | PPCInstrInfo.cpp | 156 const MachineInstr &DefMI, unsigned DefIdx, 159 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx, 162 if (!DefMI.getParent()) 165 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); 171 &DefMI.getParent()->getParent()->getRegInfo(); 181 Latency = getInstrLatency(ItinData, DefMI); 1561 bool PPCInstrInfo::onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, argument 1564 unsigned DefOpc = DefMI.getOpcode(); 1567 if (!DefMI.getOperand(1).isImm()) 1569 if (DefMI 155 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const argument [all...] |
H A D | PPCVSXSwapRemoval.cpp | 617 MachineInstr* DefMI = MRI->getVRegDef(Reg); local 618 assert(SwapMap.find(DefMI) != SwapMap.end() && 620 int DefIdx = SwapMap[DefMI]; 628 LLVM_DEBUG(DefMI->dump()); 699 MachineInstr *DefMI = MRI->getVRegDef(UseReg); local 700 Register DefReg = DefMI->getOperand(0).getReg(); 701 int DefIdx = SwapMap[DefMI]; 711 LLVM_DEBUG(DefMI->dump()); 717 // Ensure all uses of the register defined by DefMI feed store 730 LLVM_DEBUG(DefMI 776 MachineInstr *DefMI = MRI->getVRegDef(UseReg); local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiInstrInfo.cpp | 498 MachineInstr *DefMI = canFoldIntoSelect(MI.getOperand(1).getReg(), MRI); local 499 bool Invert = !DefMI; 500 if (!DefMI) 501 DefMI = canFoldIntoSelect(MI.getOperand(2).getReg(), MRI); 502 if (!DefMI) 512 // Create a new predicated version of DefMI. 514 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg); 516 // Copy all the DefMI operands, excluding its (null) predicate. 517 const MCInstrDesc &DefDesc = DefMI->getDesc(); 520 NewMI.add(DefMI [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIFixSGPRCopies.cpp | 647 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); 652 if (isSafeToFoldImmIntoCopy(&MI, DefMI, TII, SMovOp, Imm)) { 725 MachineInstr *DefMI = MRI->getVRegDef(MO->getReg()); 726 if (DefMI && TII->isFoldableCopy(*DefMI)) { 727 const MachineOperand &Def = DefMI->getOperand(0); 731 const MachineOperand &Copied = DefMI->getOperand(1); 815 MachineInstr *DefMI = MRI->getVRegDef(MI.getOperand(I).getReg()); 816 if (DefMI && DefMI [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | LegalizationArtifactCombiner.h | 306 if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, 329 markInstAndDefDead(MI, *DefMI, DeadInsts); 826 /// Mark a def of one of MI's original operands, DefMI, as dead if changing MI 827 /// (either by killing it or changing operands) results in DefMI being dead 831 void markDefDead(MachineInstr &MI, MachineInstr &DefMI, argument 834 // this instruction. Collect all of them until the Trunc(DefMI). 843 while (PrevMI != &DefMI) { 848 if (TmpDef != &DefMI) { 859 if (PrevMI == &DefMI && MRI.hasOneUse(DefMI 868 markInstAndDefDead(MachineInstr &MI, MachineInstr &DefMI, SmallVectorImpl<MachineInstr *> &DeadInsts) argument [all...] |