Lines Matching refs:DefMI
813 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
814 if (!DefMI)
816 if (!DefMI->isCommutable())
818 // If DefMI is a two-address instruction then commuting it will change the
820 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
823 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
836 if (!TII->findCommutedOpIndices(*DefMI, UseOpIdx, NewDstIdx))
839 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
864 << *DefMI);
868 MachineBasicBlock *MBB = DefMI->getParent();
870 TII->commuteInstruction(*DefMI, false, UseOpIdx, NewDstIdx);
877 if (NewMI != DefMI) {
878 LIS->ReplaceMachineInstrInMaps(*DefMI, *NewMI);
879 MachineBasicBlock::iterator Pos = DefMI;
881 MBB->erase(DefMI);
1097 MachineInstr *DefMI = LIS->getInstructionFromIndex(PVal->def);
1098 if (!DefMI || !DefMI->isFullCopy()) {
1102 // Check DefMI is a reverse copy and it is in BB Pred.
1103 if (DefMI->getOperand(0).getReg() != IntA.reg ||
1104 DefMI->getOperand(1).getReg() != IntB.reg ||
1105 DefMI->getParent() != Pred) {
1109 // If there is any other def of B after DefMI and before the end of Pred,
1259 MachineInstr *DefMI = LIS->getInstructionFromIndex(ValNo->def);
1260 if (!DefMI)
1262 if (DefMI->isCopyLike()) {
1266 if (!TII->isAsCheapAsAMove(*DefMI))
1268 if (!TII->isTriviallyReMaterializable(*DefMI, AA))
1270 if (!definesFullReg(*DefMI, SrcReg))
1273 if (!DefMI->isSafeToMove(AA, SawStore))
1275 const MCInstrDesc &MCID = DefMI->getDesc();
1293 if (!DefMI->isImplicitDef()) {
1298 DefMI->getOperand(0).getSubReg());
1318 TII->reMaterialize(*MBB, MII, DstReg, SrcIdx, *DefMI, *TRI);
1323 // %0:subreg = instr ; DefMI, subreg = DstIdx
2336 /// Compute the bitmask of lanes actually written by DefMI.
2339 LaneBitmask computeWriteLanes(const MachineInstr *DefMI, bool &Redef) const;
2451 LaneBitmask JoinVals::computeWriteLanes(const MachineInstr *DefMI, bool &Redef)
2454 for (const MachineOperand &MO : DefMI->operands()) {
2553 const MachineInstr *DefMI = nullptr;
2560 DefMI = Indexes->getInstructionFromIndex(VNI->def);
2561 assert(DefMI != nullptr);
2565 if (DefMI->isImplicitDef()) {
2571 V.ValidLanes = V.WriteLanes = computeWriteLanes(DefMI, Redef);
2575 // This only covers partial redef operands. DefMI may have normal use
2599 if (DefMI->isImplicitDef()) {
2669 if (DefMI &&
2670 DefMI->getParent() != Indexes->getMBBFromIndex(V.OtherVNI->def)) {
2673 << printMBBReference(*DefMI->getParent())
2688 if (DefMI->isImplicitDef()) {
2697 // Include the non-conflict where DefMI is a coalescable copy that kills
2699 if (CP.isCoalescable(DefMI)) {
2706 // This may not be a real conflict if DefMI simply kills Other and defines
2716 if (DefMI->isFullCopy() && !CP.isPartial() &&
2743 // If the other live range is killed by DefMI and the live ranges are still