| /freebsd-11.0-release/sys/cddl/dev/dtrace/arm/ |
| H A D | regset.h | 47 #define REG_SP R12
|
| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 41 case R8: case R9: case R10: case R11: case R12:
52 case R8: case R9: case R10: case R11: case R12:
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| H A D | ThumbRegisterInfo.cpp | 457 // the function, the offset will be negative. Use R12 instead since that's
462 .addReg(ARM::R12, RegState::Define)
466 // interference with R12 before then, however, we'll need to restore it
472 // If this instruction affects R12, adjust our restore point.
475 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) {
483 if (MO.getReg() == ARM::R12) {
490 // Restore the register from R12
492 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill));
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| H A D | ARMFrameLowering.cpp | 357 case ARM::R12:
474 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
480 .addReg(ARM::R12, RegState::Kill)
561 case ARM::R12:
594 case ARM::R12:
1713 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
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| H A D | Thumb1FrameLowering.cpp | 215 case ARM::R12:
|
| /freebsd-11.0-release/contrib/llvm/lib/Target/MSP430/ |
| H A D | MSP430RegisterInfo.cpp | 55 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15,
61 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15,
|
| /freebsd-11.0-release/contrib/gcc/config/rs6000/ |
| H A D | darwin-world.asm | 77 USES: R0 R11 R12 */
114 /* set R12 pointing at Vector Reg save area */
165 USES: R0 R10 R11 R12 and R7 R8
200 USES: R0 R11 R12 [R7/R8]
213 /* R12 := HAS_VEC */
|
| /freebsd-11.0-release/contrib/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 324 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
361 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
397 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
433 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
434 return X86::R12;
|
| H A D | X86BaseInfo.h | 748 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
|
| H A D | X86AsmBackend.cpp | 464 case X86::R12:
644 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
|
| /freebsd-11.0-release/contrib/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 639 Value *R11,*R12; local
641 if (decomposeBitTestICmp(RHS, RHSCC, R11, R12, R2)) {
643 A = R11; D = R12;
644 } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) {
645 A = R12; D = R11;
651 if (!match(R1, m_And(m_Value(R11), m_Value(R12)))) {
655 R12
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 61 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
|
| /freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 560 - If MBB is an entry or exit block, set SR1 and SR2 to R0 and R12
564 - If the defaults (R0/R12) are available, return true
583 unsigned R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12; local
591 *SR2 = R12;
594 // If MBB is an entry or exit block, use R0 and R12 as the scratch registers.
615 // Note that we only return here if both R0 and R12 are available because
618 if (!RS.isRegUsed(R0) && !RS.isRegUsed(R12))
754 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
755 // ...(R12/X1
[all...] |
| H A D | PPCAsmPrinter.cpp | 1428 .addReg(PPC::R12)
1432 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::MTCTR).addReg(PPC::R12));
1481 .addReg(PPC::R12)
1486 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::MTCTR).addReg(PPC::R12));
|
| /freebsd-11.0-release/contrib/llvm/lib/Target/X86/Disassembler/ |
| H A D | X86DisassemblerDecoder.h | 183 ENTRY(R12) \
201 ENTRY(R12) \
|
| /freebsd-11.0-release/contrib/llvm/include/llvm/DebugInfo/PDB/ |
| H A D | PDBTypes.h | 416 R12 = 340, member in class:llvm::PDB_Checksum::PDB_Machine::PDB_Lang::PDB_BuiltinType::PDB_RegisterId
|
| /freebsd-11.0-release/sys/amd64/amd64/ |
| H A D | bpf_jit_machdep.h | 52 #define R12 4 macro
|
| /freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/Disassembler/ |
| H A D | PPCDisassembler.cpp | 167 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
178 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
|
| /freebsd-11.0-release/contrib/subversion/subversion/libsvn_subr/ |
| H A D | win32_crashrpt.c | 251 "R12=%016I64x R13=%016I64x R14=%016I64x R15=%016I64x\n",
252 context->R12, context->R13, context->R14, context->R15);
|
| /freebsd-11.0-release/contrib/llvm/lib/DebugInfo/PDB/ |
| H A D | PDBExtras.cpp | 139 CASE_OUTPUT_ENUM_CLASS_NAME(PDB_RegisterId, R12, OS)
|
| /freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCChecker.cpp | 535 case Hexagon::R12:
|
| H A D | HexagonMCCodeEmitter.cpp | 102 Hexagon::R11, Hexagon::R12, Hexagon::R13,
|
| /freebsd-11.0-release/contrib/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 404 case X86::R12: return X86::R12D;
|
| /freebsd-11.0-release/contrib/gdb/gdb/ |
| H A D | wince.c | 230 context_offset (R12),
361 context_offset (R12),
|
| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAsmBackend.cpp | 960 {ARM::R12, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R12},
|