1//===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
15#define LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
16
17#include "MCTargetDesc/ARMBaseInfo.h"
18#include "llvm/Target/TargetRegisterInfo.h"
19
20#define GET_REGINFO_HEADER
21#include "ARMGenRegisterInfo.inc"
22
23namespace llvm {
24/// Register allocation hints.
25namespace ARMRI {
26  enum {
27    RegPairOdd  = 1,
28    RegPairEven = 2
29  };
30}
31
32/// isARMArea1Register - Returns true if the register is a low register (r0-r7)
33/// or a stack/pc register that we should push/pop.
34static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
35  using namespace ARM;
36  switch (Reg) {
37    case R0:  case R1:  case R2:  case R3:
38    case R4:  case R5:  case R6:  case R7:
39    case LR:  case SP:  case PC:
40      return true;
41    case R8:  case R9:  case R10: case R11: case R12:
42      // For iOS we want r7 and lr to be next to each other.
43      return !isIOS;
44    default:
45      return false;
46  }
47}
48
49static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
50  using namespace ARM;
51  switch (Reg) {
52    case R8: case R9: case R10: case R11: case R12:
53      // iOS has this second area.
54      return isIOS;
55    default:
56      return false;
57  }
58}
59
60static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
61  using namespace ARM;
62  switch (Reg) {
63    case D15: case D14: case D13: case D12:
64    case D11: case D10: case D9:  case D8:
65    case D7:  case D6:  case D5:  case D4:
66    case D3:  case D2:  case D1:  case D0:
67    case D31: case D30: case D29: case D28:
68    case D27: case D26: case D25: case D24:
69    case D23: case D22: case D21: case D20:
70    case D19: case D18: case D17: case D16:
71      return true;
72    default:
73      return false;
74  }
75}
76
77static inline bool isCalleeSavedRegister(unsigned Reg,
78                                         const MCPhysReg *CSRegs) {
79  for (unsigned i = 0; CSRegs[i]; ++i)
80    if (Reg == CSRegs[i])
81      return true;
82  return false;
83}
84
85class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
86protected:
87  /// BasePtr - ARM physical register used as a base ptr in complex stack
88  /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
89  /// variable size stack objects.
90  unsigned BasePtr;
91
92  // Can be only subclassed.
93  explicit ARMBaseRegisterInfo();
94
95  // Return the opcode that implements 'Op', or 0 if no opcode
96  unsigned getOpcode(int Op) const;
97
98public:
99  /// Code Generation virtual methods...
100  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
101  const MCPhysReg *
102  getCalleeSavedRegsViaCopy(const MachineFunction *MF) const override;
103  const uint32_t *getCallPreservedMask(const MachineFunction &MF,
104                                       CallingConv::ID) const override;
105  const uint32_t *getNoPreservedMask() const override;
106  const uint32_t *getTLSCallPreservedMask(const MachineFunction &MF) const;
107
108  /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
109  /// case that 'returned' is on an i32 first argument if the calling convention
110  /// is one that can (partially) model this attribute with a preserved mask
111  /// (i.e. it is a calling convention that uses the same register for the first
112  /// i32 argument and an i32 return value)
113  ///
114  /// Should return NULL in the case that the calling convention does not have
115  /// this property
116  const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
117                                             CallingConv::ID) const;
118
119  BitVector getReservedRegs(const MachineFunction &MF) const override;
120
121  const TargetRegisterClass *
122  getPointerRegClass(const MachineFunction &MF,
123                     unsigned Kind = 0) const override;
124  const TargetRegisterClass *
125  getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
126
127  const TargetRegisterClass *
128  getLargestLegalSuperClass(const TargetRegisterClass *RC,
129                            const MachineFunction &MF) const override;
130
131  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
132                               MachineFunction &MF) const override;
133
134  void getRegAllocationHints(unsigned VirtReg,
135                             ArrayRef<MCPhysReg> Order,
136                             SmallVectorImpl<MCPhysReg> &Hints,
137                             const MachineFunction &MF,
138                             const VirtRegMap *VRM,
139                             const LiveRegMatrix *Matrix) const override;
140
141  void updateRegAllocHint(unsigned Reg, unsigned NewReg,
142                          MachineFunction &MF) const override;
143
144  bool hasBasePointer(const MachineFunction &MF) const;
145
146  bool canRealignStack(const MachineFunction &MF) const override;
147  int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
148                                   int Idx) const override;
149  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
150  void materializeFrameBaseRegister(MachineBasicBlock *MBB,
151                                    unsigned BaseReg, int FrameIdx,
152                                    int64_t Offset) const override;
153  void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
154                         int64_t Offset) const override;
155  bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
156                          int64_t Offset) const override;
157
158  bool cannotEliminateFrame(const MachineFunction &MF) const;
159
160  // Debug information queries.
161  unsigned getFrameRegister(const MachineFunction &MF) const override;
162  unsigned getBaseRegister() const { return BasePtr; }
163
164  bool isLowRegister(unsigned Reg) const;
165
166
167  /// emitLoadConstPool - Emits a load from constpool to materialize the
168  /// specified immediate.
169  virtual void emitLoadConstPool(MachineBasicBlock &MBB,
170                                 MachineBasicBlock::iterator &MBBI,
171                                 DebugLoc dl, unsigned DestReg, unsigned SubIdx,
172                                 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
173                                 unsigned PredReg = 0,
174                                 unsigned MIFlags = MachineInstr::NoFlags)const;
175
176  /// Code Generation virtual methods...
177  bool requiresRegisterScavenging(const MachineFunction &MF) const override;
178
179  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
180
181  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
182
183  bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
184
185  void eliminateFrameIndex(MachineBasicBlock::iterator II,
186                           int SPAdj, unsigned FIOperandNum,
187                           RegScavenger *RS = nullptr) const override;
188
189  /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true
190  bool shouldCoalesce(MachineInstr *MI,
191                      const TargetRegisterClass *SrcRC,
192                      unsigned SubReg,
193                      const TargetRegisterClass *DstRC,
194                      unsigned DstSubReg,
195                      const TargetRegisterClass *NewRC) const override;
196};
197
198} // end namespace llvm
199
200#endif
201