1//===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file provides X86 specific target descriptions. 11// 12//===----------------------------------------------------------------------===// 13 14#include "X86MCTargetDesc.h" 15#include "InstPrinter/X86ATTInstPrinter.h" 16#include "InstPrinter/X86IntelInstPrinter.h" 17#include "X86MCAsmInfo.h" 18#include "llvm/ADT/Triple.h" 19#include "llvm/MC/MCCodeGenInfo.h" 20#include "llvm/MC/MCInstrAnalysis.h" 21#include "llvm/MC/MCInstrInfo.h" 22#include "llvm/MC/MCRegisterInfo.h" 23#include "llvm/MC/MCStreamer.h" 24#include "llvm/MC/MCSubtargetInfo.h" 25#include "llvm/MC/MachineLocation.h" 26#include "llvm/Support/ErrorHandling.h" 27#include "llvm/Support/Host.h" 28#include "llvm/Support/TargetRegistry.h" 29 30#if _MSC_VER 31#include <intrin.h> 32#endif 33 34using namespace llvm; 35 36#define GET_REGINFO_MC_DESC 37#include "X86GenRegisterInfo.inc" 38 39#define GET_INSTRINFO_MC_DESC 40#include "X86GenInstrInfo.inc" 41 42#define GET_SUBTARGETINFO_MC_DESC 43#include "X86GenSubtargetInfo.inc" 44 45std::string X86_MC::ParseX86Triple(const Triple &TT) { 46 std::string FS; 47 if (TT.getArch() == Triple::x86_64) 48 FS = "+64bit-mode,-32bit-mode,-16bit-mode"; 49 else if (TT.getEnvironment() != Triple::CODE16) 50 FS = "-64bit-mode,+32bit-mode,-16bit-mode"; 51 else 52 FS = "-64bit-mode,-32bit-mode,+16bit-mode"; 53 54 return FS; 55} 56 57unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) { 58 if (TT.getArch() == Triple::x86_64) 59 return DWARFFlavour::X86_64; 60 61 if (TT.isOSDarwin()) 62 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic; 63 if (TT.isOSCygMing()) 64 // Unsupported by now, just quick fallback 65 return DWARFFlavour::X86_32_Generic; 66 return DWARFFlavour::X86_32_Generic; 67} 68 69void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) { 70 // FIXME: TableGen these. 71 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) { 72 unsigned SEH = MRI->getEncodingValue(Reg); 73 MRI->mapLLVMRegToSEHReg(Reg, SEH); 74 } 75} 76 77MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT, 78 StringRef CPU, StringRef FS) { 79 std::string ArchFS = X86_MC::ParseX86Triple(TT); 80 if (!FS.empty()) { 81 if (!ArchFS.empty()) 82 ArchFS = (Twine(ArchFS) + "," + FS).str(); 83 else 84 ArchFS = FS; 85 } 86 87 std::string CPUName = CPU; 88 if (CPUName.empty()) 89 CPUName = "generic"; 90 91 return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS); 92} 93 94static MCInstrInfo *createX86MCInstrInfo() { 95 MCInstrInfo *X = new MCInstrInfo(); 96 InitX86MCInstrInfo(X); 97 return X; 98} 99 100static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) { 101 unsigned RA = (TT.getArch() == Triple::x86_64) 102 ? X86::RIP // Should have dwarf #16. 103 : X86::EIP; // Should have dwarf #8. 104 105 MCRegisterInfo *X = new MCRegisterInfo(); 106 InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false), 107 X86_MC::getDwarfRegFlavour(TT, true), RA); 108 X86_MC::InitLLVM2SEHRegisterMapping(X); 109 return X; 110} 111 112static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, 113 const Triple &TheTriple) { 114 bool is64Bit = TheTriple.getArch() == Triple::x86_64; 115 116 MCAsmInfo *MAI; 117 if (TheTriple.isOSBinFormatMachO()) { 118 if (is64Bit) 119 MAI = new X86_64MCAsmInfoDarwin(TheTriple); 120 else 121 MAI = new X86MCAsmInfoDarwin(TheTriple); 122 } else if (TheTriple.isOSBinFormatELF()) { 123 // Force the use of an ELF container. 124 MAI = new X86ELFMCAsmInfo(TheTriple); 125 } else if (TheTriple.isWindowsMSVCEnvironment() || 126 TheTriple.isWindowsCoreCLREnvironment()) { 127 MAI = new X86MCAsmInfoMicrosoft(TheTriple); 128 } else if (TheTriple.isOSCygMing() || 129 TheTriple.isWindowsItaniumEnvironment()) { 130 MAI = new X86MCAsmInfoGNUCOFF(TheTriple); 131 } else { 132 // The default is ELF. 133 MAI = new X86ELFMCAsmInfo(TheTriple); 134 } 135 136 // Initialize initial frame state. 137 // Calculate amount of bytes used for return address storing 138 int stackGrowth = is64Bit ? -8 : -4; 139 140 // Initial state of the frame pointer is esp+stackGrowth. 141 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; 142 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa( 143 nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth); 144 MAI->addInitialFrameState(Inst); 145 146 // Add return address to move list 147 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP; 148 MCCFIInstruction Inst2 = MCCFIInstruction::createOffset( 149 nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth); 150 MAI->addInitialFrameState(Inst2); 151 152 return MAI; 153} 154 155static MCCodeGenInfo *createX86MCCodeGenInfo(const Triple &TT, Reloc::Model RM, 156 CodeModel::Model CM, 157 CodeGenOpt::Level OL) { 158 MCCodeGenInfo *X = new MCCodeGenInfo(); 159 160 bool is64Bit = TT.getArch() == Triple::x86_64; 161 162 if (RM == Reloc::Default) { 163 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode. 164 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we 165 // use static relocation model by default. 166 if (TT.isOSDarwin()) { 167 if (is64Bit) 168 RM = Reloc::PIC_; 169 else 170 RM = Reloc::DynamicNoPIC; 171 } else if (TT.isOSWindows() && is64Bit) 172 RM = Reloc::PIC_; 173 else 174 RM = Reloc::Static; 175 } 176 177 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC 178 // is defined as a model for code which may be used in static or dynamic 179 // executables but not necessarily a shared library. On X86-32 we just 180 // compile in -static mode, in x86-64 we use PIC. 181 if (RM == Reloc::DynamicNoPIC) { 182 if (is64Bit) 183 RM = Reloc::PIC_; 184 else if (!TT.isOSDarwin()) 185 RM = Reloc::Static; 186 } 187 188 // If we are on Darwin, disallow static relocation model in X86-64 mode, since 189 // the Mach-O file format doesn't support it. 190 if (RM == Reloc::Static && TT.isOSDarwin() && is64Bit) 191 RM = Reloc::PIC_; 192 193 // For static codegen, if we're not already set, use Small codegen. 194 if (CM == CodeModel::Default) 195 CM = CodeModel::Small; 196 else if (CM == CodeModel::JITDefault) 197 // 64-bit JIT places everything in the same buffer except external funcs. 198 CM = is64Bit ? CodeModel::Large : CodeModel::Small; 199 200 X->initMCCodeGenInfo(RM, CM, OL); 201 return X; 202} 203 204static MCInstPrinter *createX86MCInstPrinter(const Triple &T, 205 unsigned SyntaxVariant, 206 const MCAsmInfo &MAI, 207 const MCInstrInfo &MII, 208 const MCRegisterInfo &MRI) { 209 if (SyntaxVariant == 0) 210 return new X86ATTInstPrinter(MAI, MII, MRI); 211 if (SyntaxVariant == 1) 212 return new X86IntelInstPrinter(MAI, MII, MRI); 213 return nullptr; 214} 215 216static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple, 217 MCContext &Ctx) { 218 if (TheTriple.isOSBinFormatMachO() && TheTriple.getArch() == Triple::x86_64) 219 return createX86_64MachORelocationInfo(Ctx); 220 else if (TheTriple.isOSBinFormatELF()) 221 return createX86_64ELFRelocationInfo(Ctx); 222 // Default to the stock relocation info. 223 return llvm::createMCRelocationInfo(TheTriple, Ctx); 224} 225 226static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) { 227 return new MCInstrAnalysis(Info); 228} 229 230// Force static initialization. 231extern "C" void LLVMInitializeX86TargetMC() { 232 for (Target *T : {&TheX86_32Target, &TheX86_64Target}) { 233 // Register the MC asm info. 234 RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo); 235 236 // Register the MC codegen info. 237 RegisterMCCodeGenInfoFn Y(*T, createX86MCCodeGenInfo); 238 239 // Register the MC instruction info. 240 TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo); 241 242 // Register the MC register info. 243 TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo); 244 245 // Register the MC subtarget info. 246 TargetRegistry::RegisterMCSubtargetInfo(*T, 247 X86_MC::createX86MCSubtargetInfo); 248 249 // Register the MC instruction analyzer. 250 TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis); 251 252 // Register the code emitter. 253 TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter); 254 255 // Register the object streamer. 256 TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer); 257 258 // Register the MCInstPrinter. 259 TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter); 260 261 // Register the MC relocation info. 262 TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo); 263 } 264 265 // Register the asm backend. 266 TargetRegistry::RegisterMCAsmBackend(TheX86_32Target, 267 createX86_32AsmBackend); 268 TargetRegistry::RegisterMCAsmBackend(TheX86_64Target, 269 createX86_64AsmBackend); 270} 271 272unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size, 273 bool High) { 274 switch (Size) { 275 default: return 0; 276 case 8: 277 if (High) { 278 switch (Reg) { 279 default: return getX86SubSuperRegisterOrZero(Reg, 64); 280 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 281 return X86::SI; 282 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 283 return X86::DI; 284 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 285 return X86::BP; 286 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 287 return X86::SP; 288 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 289 return X86::AH; 290 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 291 return X86::DH; 292 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 293 return X86::CH; 294 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 295 return X86::BH; 296 } 297 } else { 298 switch (Reg) { 299 default: return 0; 300 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 301 return X86::AL; 302 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 303 return X86::DL; 304 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 305 return X86::CL; 306 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 307 return X86::BL; 308 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 309 return X86::SIL; 310 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 311 return X86::DIL; 312 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 313 return X86::BPL; 314 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 315 return X86::SPL; 316 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 317 return X86::R8B; 318 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 319 return X86::R9B; 320 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 321 return X86::R10B; 322 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 323 return X86::R11B; 324 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 325 return X86::R12B; 326 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 327 return X86::R13B; 328 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 329 return X86::R14B; 330 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 331 return X86::R15B; 332 } 333 } 334 case 16: 335 switch (Reg) { 336 default: return 0; 337 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 338 return X86::AX; 339 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 340 return X86::DX; 341 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 342 return X86::CX; 343 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 344 return X86::BX; 345 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 346 return X86::SI; 347 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 348 return X86::DI; 349 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 350 return X86::BP; 351 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 352 return X86::SP; 353 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 354 return X86::R8W; 355 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 356 return X86::R9W; 357 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 358 return X86::R10W; 359 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 360 return X86::R11W; 361 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 362 return X86::R12W; 363 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 364 return X86::R13W; 365 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 366 return X86::R14W; 367 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 368 return X86::R15W; 369 } 370 case 32: 371 switch (Reg) { 372 default: return 0; 373 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 374 return X86::EAX; 375 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 376 return X86::EDX; 377 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 378 return X86::ECX; 379 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 380 return X86::EBX; 381 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 382 return X86::ESI; 383 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 384 return X86::EDI; 385 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 386 return X86::EBP; 387 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 388 return X86::ESP; 389 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 390 return X86::R8D; 391 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 392 return X86::R9D; 393 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 394 return X86::R10D; 395 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 396 return X86::R11D; 397 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 398 return X86::R12D; 399 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 400 return X86::R13D; 401 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 402 return X86::R14D; 403 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 404 return X86::R15D; 405 } 406 case 64: 407 switch (Reg) { 408 default: return 0; 409 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 410 return X86::RAX; 411 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 412 return X86::RDX; 413 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 414 return X86::RCX; 415 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 416 return X86::RBX; 417 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 418 return X86::RSI; 419 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 420 return X86::RDI; 421 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 422 return X86::RBP; 423 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 424 return X86::RSP; 425 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 426 return X86::R8; 427 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 428 return X86::R9; 429 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 430 return X86::R10; 431 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 432 return X86::R11; 433 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 434 return X86::R12; 435 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 436 return X86::R13; 437 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 438 return X86::R14; 439 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 440 return X86::R15; 441 } 442 } 443} 444 445unsigned llvm::getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) { 446 unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High); 447 assert(Res != 0 && "Unexpected register or VT"); 448 return Res; 449} 450 451 452