1//===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/X86BaseInfo.h"
11#include "MCTargetDesc/X86FixupKinds.h"
12#include "llvm/ADT/StringSwitch.h"
13#include "llvm/MC/MCAsmBackend.h"
14#include "llvm/MC/MCELFObjectWriter.h"
15#include "llvm/MC/MCExpr.h"
16#include "llvm/MC/MCFixupKindInfo.h"
17#include "llvm/MC/MCInst.h"
18#include "llvm/MC/MCMachObjectWriter.h"
19#include "llvm/MC/MCObjectWriter.h"
20#include "llvm/MC/MCRegisterInfo.h"
21#include "llvm/MC/MCSectionCOFF.h"
22#include "llvm/MC/MCSectionELF.h"
23#include "llvm/MC/MCSectionMachO.h"
24#include "llvm/Support/CommandLine.h"
25#include "llvm/Support/ELF.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/MachO.h"
28#include "llvm/Support/TargetRegistry.h"
29#include "llvm/Support/raw_ostream.h"
30using namespace llvm;
31
32static unsigned getFixupKindLog2Size(unsigned Kind) {
33  switch (Kind) {
34  default:
35    llvm_unreachable("invalid fixup kind!");
36  case FK_PCRel_1:
37  case FK_SecRel_1:
38  case FK_Data_1:
39    return 0;
40  case FK_PCRel_2:
41  case FK_SecRel_2:
42  case FK_Data_2:
43    return 1;
44  case FK_PCRel_4:
45  case X86::reloc_riprel_4byte:
46  case X86::reloc_riprel_4byte_movq_load:
47  case X86::reloc_signed_4byte:
48  case X86::reloc_global_offset_table:
49  case FK_SecRel_4:
50  case FK_Data_4:
51    return 2;
52  case FK_PCRel_8:
53  case FK_SecRel_8:
54  case FK_Data_8:
55  case X86::reloc_global_offset_table8:
56    return 3;
57  }
58}
59
60namespace {
61
62class X86ELFObjectWriter : public MCELFObjectTargetWriter {
63public:
64  X86ELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine,
65                     bool HasRelocationAddend, bool foobar)
66    : MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {}
67};
68
69class X86AsmBackend : public MCAsmBackend {
70  const StringRef CPU;
71  bool HasNopl;
72  const uint64_t MaxNopLength;
73public:
74  X86AsmBackend(const Target &T, StringRef CPU)
75      : MCAsmBackend(), CPU(CPU), MaxNopLength(CPU == "slm" ? 7 : 15) {
76    HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" &&
77              CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" &&
78              CPU != "i686" && CPU != "k6" && CPU != "k6-2" && CPU != "k6-3" &&
79              CPU != "geode" && CPU != "winchip-c6" && CPU != "winchip2" &&
80              CPU != "c3" && CPU != "c3-2";
81  }
82
83  unsigned getNumFixupKinds() const override {
84    return X86::NumTargetFixupKinds;
85  }
86
87  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
88    const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
89      { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
90      { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
91      { "reloc_signed_4byte", 0, 4 * 8, 0},
92      { "reloc_global_offset_table", 0, 4 * 8, 0}
93    };
94
95    if (Kind < FirstTargetFixupKind)
96      return MCAsmBackend::getFixupKindInfo(Kind);
97
98    assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
99           "Invalid kind!");
100    return Infos[Kind - FirstTargetFixupKind];
101  }
102
103  void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
104                  uint64_t Value, bool IsPCRel) const override {
105    unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
106
107    assert(Fixup.getOffset() + Size <= DataSize &&
108           "Invalid fixup offset!");
109
110    // Check that uppper bits are either all zeros or all ones.
111    // Specifically ignore overflow/underflow as long as the leakage is
112    // limited to the lower bits. This is to remain compatible with
113    // other assemblers.
114    assert(isIntN(Size * 8 + 1, Value) &&
115           "Value does not fit in the Fixup field");
116
117    for (unsigned i = 0; i != Size; ++i)
118      Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
119  }
120
121  bool mayNeedRelaxation(const MCInst &Inst) const override;
122
123  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
124                            const MCRelaxableFragment *DF,
125                            const MCAsmLayout &Layout) const override;
126
127  void relaxInstruction(const MCInst &Inst, MCInst &Res) const override;
128
129  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
130};
131} // end anonymous namespace
132
133static unsigned getRelaxedOpcodeBranch(unsigned Op) {
134  switch (Op) {
135  default:
136    return Op;
137
138  case X86::JAE_1: return X86::JAE_4;
139  case X86::JA_1:  return X86::JA_4;
140  case X86::JBE_1: return X86::JBE_4;
141  case X86::JB_1:  return X86::JB_4;
142  case X86::JE_1:  return X86::JE_4;
143  case X86::JGE_1: return X86::JGE_4;
144  case X86::JG_1:  return X86::JG_4;
145  case X86::JLE_1: return X86::JLE_4;
146  case X86::JL_1:  return X86::JL_4;
147  case X86::JMP_1: return X86::JMP_4;
148  case X86::JNE_1: return X86::JNE_4;
149  case X86::JNO_1: return X86::JNO_4;
150  case X86::JNP_1: return X86::JNP_4;
151  case X86::JNS_1: return X86::JNS_4;
152  case X86::JO_1:  return X86::JO_4;
153  case X86::JP_1:  return X86::JP_4;
154  case X86::JS_1:  return X86::JS_4;
155  }
156}
157
158static unsigned getRelaxedOpcodeArith(unsigned Op) {
159  switch (Op) {
160  default:
161    return Op;
162
163    // IMUL
164  case X86::IMUL16rri8: return X86::IMUL16rri;
165  case X86::IMUL16rmi8: return X86::IMUL16rmi;
166  case X86::IMUL32rri8: return X86::IMUL32rri;
167  case X86::IMUL32rmi8: return X86::IMUL32rmi;
168  case X86::IMUL64rri8: return X86::IMUL64rri32;
169  case X86::IMUL64rmi8: return X86::IMUL64rmi32;
170
171    // AND
172  case X86::AND16ri8: return X86::AND16ri;
173  case X86::AND16mi8: return X86::AND16mi;
174  case X86::AND32ri8: return X86::AND32ri;
175  case X86::AND32mi8: return X86::AND32mi;
176  case X86::AND64ri8: return X86::AND64ri32;
177  case X86::AND64mi8: return X86::AND64mi32;
178
179    // OR
180  case X86::OR16ri8: return X86::OR16ri;
181  case X86::OR16mi8: return X86::OR16mi;
182  case X86::OR32ri8: return X86::OR32ri;
183  case X86::OR32mi8: return X86::OR32mi;
184  case X86::OR64ri8: return X86::OR64ri32;
185  case X86::OR64mi8: return X86::OR64mi32;
186
187    // XOR
188  case X86::XOR16ri8: return X86::XOR16ri;
189  case X86::XOR16mi8: return X86::XOR16mi;
190  case X86::XOR32ri8: return X86::XOR32ri;
191  case X86::XOR32mi8: return X86::XOR32mi;
192  case X86::XOR64ri8: return X86::XOR64ri32;
193  case X86::XOR64mi8: return X86::XOR64mi32;
194
195    // ADD
196  case X86::ADD16ri8: return X86::ADD16ri;
197  case X86::ADD16mi8: return X86::ADD16mi;
198  case X86::ADD32ri8: return X86::ADD32ri;
199  case X86::ADD32mi8: return X86::ADD32mi;
200  case X86::ADD64ri8: return X86::ADD64ri32;
201  case X86::ADD64mi8: return X86::ADD64mi32;
202
203   // ADC
204  case X86::ADC16ri8: return X86::ADC16ri;
205  case X86::ADC16mi8: return X86::ADC16mi;
206  case X86::ADC32ri8: return X86::ADC32ri;
207  case X86::ADC32mi8: return X86::ADC32mi;
208  case X86::ADC64ri8: return X86::ADC64ri32;
209  case X86::ADC64mi8: return X86::ADC64mi32;
210
211    // SUB
212  case X86::SUB16ri8: return X86::SUB16ri;
213  case X86::SUB16mi8: return X86::SUB16mi;
214  case X86::SUB32ri8: return X86::SUB32ri;
215  case X86::SUB32mi8: return X86::SUB32mi;
216  case X86::SUB64ri8: return X86::SUB64ri32;
217  case X86::SUB64mi8: return X86::SUB64mi32;
218
219   // SBB
220  case X86::SBB16ri8: return X86::SBB16ri;
221  case X86::SBB16mi8: return X86::SBB16mi;
222  case X86::SBB32ri8: return X86::SBB32ri;
223  case X86::SBB32mi8: return X86::SBB32mi;
224  case X86::SBB64ri8: return X86::SBB64ri32;
225  case X86::SBB64mi8: return X86::SBB64mi32;
226
227    // CMP
228  case X86::CMP16ri8: return X86::CMP16ri;
229  case X86::CMP16mi8: return X86::CMP16mi;
230  case X86::CMP32ri8: return X86::CMP32ri;
231  case X86::CMP32mi8: return X86::CMP32mi;
232  case X86::CMP64ri8: return X86::CMP64ri32;
233  case X86::CMP64mi8: return X86::CMP64mi32;
234
235    // PUSH
236  case X86::PUSH32i8:  return X86::PUSHi32;
237  case X86::PUSH16i8:  return X86::PUSHi16;
238  case X86::PUSH64i8:  return X86::PUSH64i32;
239  }
240}
241
242static unsigned getRelaxedOpcode(unsigned Op) {
243  unsigned R = getRelaxedOpcodeArith(Op);
244  if (R != Op)
245    return R;
246  return getRelaxedOpcodeBranch(Op);
247}
248
249bool X86AsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
250  // Branches can always be relaxed.
251  if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
252    return true;
253
254  // Check if this instruction is ever relaxable.
255  if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
256    return false;
257
258
259  // Check if the relaxable operand has an expression. For the current set of
260  // relaxable instructions, the relaxable operand is always the last operand.
261  unsigned RelaxableOp = Inst.getNumOperands() - 1;
262  if (Inst.getOperand(RelaxableOp).isExpr())
263    return true;
264
265  return false;
266}
267
268bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
269                                         uint64_t Value,
270                                         const MCRelaxableFragment *DF,
271                                         const MCAsmLayout &Layout) const {
272  // Relax if the value is too big for a (signed) i8.
273  return int64_t(Value) != int64_t(int8_t(Value));
274}
275
276// FIXME: Can tblgen help at all here to verify there aren't other instructions
277// we can relax?
278void X86AsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
279  // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
280  unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
281
282  if (RelaxedOp == Inst.getOpcode()) {
283    SmallString<256> Tmp;
284    raw_svector_ostream OS(Tmp);
285    Inst.dump_pretty(OS);
286    OS << "\n";
287    report_fatal_error("unexpected instruction to relax: " + OS.str());
288  }
289
290  Res = Inst;
291  Res.setOpcode(RelaxedOp);
292}
293
294/// \brief Write a sequence of optimal nops to the output, covering \p Count
295/// bytes.
296/// \return - true on success, false on failure
297bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
298  static const uint8_t Nops[10][10] = {
299    // nop
300    {0x90},
301    // xchg %ax,%ax
302    {0x66, 0x90},
303    // nopl (%[re]ax)
304    {0x0f, 0x1f, 0x00},
305    // nopl 0(%[re]ax)
306    {0x0f, 0x1f, 0x40, 0x00},
307    // nopl 0(%[re]ax,%[re]ax,1)
308    {0x0f, 0x1f, 0x44, 0x00, 0x00},
309    // nopw 0(%[re]ax,%[re]ax,1)
310    {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
311    // nopl 0L(%[re]ax)
312    {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
313    // nopl 0L(%[re]ax,%[re]ax,1)
314    {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
315    // nopw 0L(%[re]ax,%[re]ax,1)
316    {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
317    // nopw %cs:0L(%[re]ax,%[re]ax,1)
318    {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
319  };
320
321  // This CPU doesn't support long nops. If needed add more.
322  // FIXME: Can we get this from the subtarget somehow?
323  // FIXME: We could generated something better than plain 0x90.
324  if (!HasNopl) {
325    for (uint64_t i = 0; i < Count; ++i)
326      OW->write8(0x90);
327    return true;
328  }
329
330  // 15 is the longest single nop instruction.  Emit as many 15-byte nops as
331  // needed, then emit a nop of the remaining length.
332  do {
333    const uint8_t ThisNopLength = (uint8_t) std::min(Count, MaxNopLength);
334    const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
335    for (uint8_t i = 0; i < Prefixes; i++)
336      OW->write8(0x66);
337    const uint8_t Rest = ThisNopLength - Prefixes;
338    for (uint8_t i = 0; i < Rest; i++)
339      OW->write8(Nops[Rest - 1][i]);
340    Count -= ThisNopLength;
341  } while (Count != 0);
342
343  return true;
344}
345
346/* *** */
347
348namespace {
349
350class ELFX86AsmBackend : public X86AsmBackend {
351public:
352  uint8_t OSABI;
353  ELFX86AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
354      : X86AsmBackend(T, CPU), OSABI(OSABI) {}
355};
356
357class ELFX86_32AsmBackend : public ELFX86AsmBackend {
358public:
359  ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
360    : ELFX86AsmBackend(T, OSABI, CPU) {}
361
362  MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
363    return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, ELF::EM_386);
364  }
365};
366
367class ELFX86_X32AsmBackend : public ELFX86AsmBackend {
368public:
369  ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
370      : ELFX86AsmBackend(T, OSABI, CPU) {}
371
372  MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
373    return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI,
374                                    ELF::EM_X86_64);
375  }
376};
377
378class ELFX86_IAMCUAsmBackend : public ELFX86AsmBackend {
379public:
380  ELFX86_IAMCUAsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
381      : ELFX86AsmBackend(T, OSABI, CPU) {}
382
383  MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
384    return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI,
385                                    ELF::EM_IAMCU);
386  }
387};
388
389class ELFX86_64AsmBackend : public ELFX86AsmBackend {
390public:
391  ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
392    : ELFX86AsmBackend(T, OSABI, CPU) {}
393
394  MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
395    return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64);
396  }
397};
398
399class WindowsX86AsmBackend : public X86AsmBackend {
400  bool Is64Bit;
401
402public:
403  WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU)
404    : X86AsmBackend(T, CPU)
405    , Is64Bit(is64Bit) {
406  }
407
408  MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
409    return createX86WinCOFFObjectWriter(OS, Is64Bit);
410  }
411};
412
413namespace CU {
414
415  /// Compact unwind encoding values.
416  enum CompactUnwindEncodings {
417    /// [RE]BP based frame where [RE]BP is pused on the stack immediately after
418    /// the return address, then [RE]SP is moved to [RE]BP.
419    UNWIND_MODE_BP_FRAME                   = 0x01000000,
420
421    /// A frameless function with a small constant stack size.
422    UNWIND_MODE_STACK_IMMD                 = 0x02000000,
423
424    /// A frameless function with a large constant stack size.
425    UNWIND_MODE_STACK_IND                  = 0x03000000,
426
427    /// No compact unwind encoding is available.
428    UNWIND_MODE_DWARF                      = 0x04000000,
429
430    /// Mask for encoding the frame registers.
431    UNWIND_BP_FRAME_REGISTERS              = 0x00007FFF,
432
433    /// Mask for encoding the frameless registers.
434    UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF
435  };
436
437} // end CU namespace
438
439class DarwinX86AsmBackend : public X86AsmBackend {
440  const MCRegisterInfo &MRI;
441
442  /// \brief Number of registers that can be saved in a compact unwind encoding.
443  enum { CU_NUM_SAVED_REGS = 6 };
444
445  mutable unsigned SavedRegs[CU_NUM_SAVED_REGS];
446  bool Is64Bit;
447
448  unsigned OffsetSize;                   ///< Offset of a "push" instruction.
449  unsigned MoveInstrSize;                ///< Size of a "move" instruction.
450  unsigned StackDivide;                  ///< Amount to adjust stack size by.
451protected:
452  /// \brief Size of a "push" instruction for the given register.
453  unsigned PushInstrSize(unsigned Reg) const {
454    switch (Reg) {
455      case X86::EBX:
456      case X86::ECX:
457      case X86::EDX:
458      case X86::EDI:
459      case X86::ESI:
460      case X86::EBP:
461      case X86::RBX:
462      case X86::RBP:
463        return 1;
464      case X86::R12:
465      case X86::R13:
466      case X86::R14:
467      case X86::R15:
468        return 2;
469    }
470    return 1;
471  }
472
473  /// \brief Implementation of algorithm to generate the compact unwind encoding
474  /// for the CFI instructions.
475  uint32_t
476  generateCompactUnwindEncodingImpl(ArrayRef<MCCFIInstruction> Instrs) const {
477    if (Instrs.empty()) return 0;
478
479    // Reset the saved registers.
480    unsigned SavedRegIdx = 0;
481    memset(SavedRegs, 0, sizeof(SavedRegs));
482
483    bool HasFP = false;
484
485    // Encode that we are using EBP/RBP as the frame pointer.
486    uint32_t CompactUnwindEncoding = 0;
487
488    unsigned SubtractInstrIdx = Is64Bit ? 3 : 2;
489    unsigned InstrOffset = 0;
490    unsigned StackAdjust = 0;
491    unsigned StackSize = 0;
492    unsigned PrevStackSize = 0;
493    unsigned NumDefCFAOffsets = 0;
494
495    for (unsigned i = 0, e = Instrs.size(); i != e; ++i) {
496      const MCCFIInstruction &Inst = Instrs[i];
497
498      switch (Inst.getOperation()) {
499      default:
500        // Any other CFI directives indicate a frame that we aren't prepared
501        // to represent via compact unwind, so just bail out.
502        return 0;
503      case MCCFIInstruction::OpDefCfaRegister: {
504        // Defines a frame pointer. E.g.
505        //
506        //     movq %rsp, %rbp
507        //  L0:
508        //     .cfi_def_cfa_register %rbp
509        //
510        HasFP = true;
511        assert(MRI.getLLVMRegNum(Inst.getRegister(), true) ==
512               (Is64Bit ? X86::RBP : X86::EBP) && "Invalid frame pointer!");
513
514        // Reset the counts.
515        memset(SavedRegs, 0, sizeof(SavedRegs));
516        StackAdjust = 0;
517        SavedRegIdx = 0;
518        InstrOffset += MoveInstrSize;
519        break;
520      }
521      case MCCFIInstruction::OpDefCfaOffset: {
522        // Defines a new offset for the CFA. E.g.
523        //
524        //  With frame:
525        //
526        //     pushq %rbp
527        //  L0:
528        //     .cfi_def_cfa_offset 16
529        //
530        //  Without frame:
531        //
532        //     subq $72, %rsp
533        //  L0:
534        //     .cfi_def_cfa_offset 80
535        //
536        PrevStackSize = StackSize;
537        StackSize = std::abs(Inst.getOffset()) / StackDivide;
538        ++NumDefCFAOffsets;
539        break;
540      }
541      case MCCFIInstruction::OpOffset: {
542        // Defines a "push" of a callee-saved register. E.g.
543        //
544        //     pushq %r15
545        //     pushq %r14
546        //     pushq %rbx
547        //  L0:
548        //     subq $120, %rsp
549        //  L1:
550        //     .cfi_offset %rbx, -40
551        //     .cfi_offset %r14, -32
552        //     .cfi_offset %r15, -24
553        //
554        if (SavedRegIdx == CU_NUM_SAVED_REGS)
555          // If there are too many saved registers, we cannot use a compact
556          // unwind encoding.
557          return CU::UNWIND_MODE_DWARF;
558
559        unsigned Reg = MRI.getLLVMRegNum(Inst.getRegister(), true);
560        SavedRegs[SavedRegIdx++] = Reg;
561        StackAdjust += OffsetSize;
562        InstrOffset += PushInstrSize(Reg);
563        break;
564      }
565      }
566    }
567
568    StackAdjust /= StackDivide;
569
570    if (HasFP) {
571      if ((StackAdjust & 0xFF) != StackAdjust)
572        // Offset was too big for a compact unwind encoding.
573        return CU::UNWIND_MODE_DWARF;
574
575      // Get the encoding of the saved registers when we have a frame pointer.
576      uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame();
577      if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
578
579      CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
580      CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
581      CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
582    } else {
583      // If the amount of the stack allocation is the size of a register, then
584      // we "push" the RAX/EAX register onto the stack instead of adjusting the
585      // stack pointer with a SUB instruction. We don't support the push of the
586      // RAX/EAX register with compact unwind. So we check for that situation
587      // here.
588      if ((NumDefCFAOffsets == SavedRegIdx + 1 &&
589           StackSize - PrevStackSize == 1) ||
590          (Instrs.size() == 1 && NumDefCFAOffsets == 1 && StackSize == 2))
591        return CU::UNWIND_MODE_DWARF;
592
593      SubtractInstrIdx += InstrOffset;
594      ++StackAdjust;
595
596      if ((StackSize & 0xFF) == StackSize) {
597        // Frameless stack with a small stack size.
598        CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
599
600        // Encode the stack size.
601        CompactUnwindEncoding |= (StackSize & 0xFF) << 16;
602      } else {
603        if ((StackAdjust & 0x7) != StackAdjust)
604          // The extra stack adjustments are too big for us to handle.
605          return CU::UNWIND_MODE_DWARF;
606
607        // Frameless stack with an offset too large for us to encode compactly.
608        CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
609
610        // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP'
611        // instruction.
612        CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
613
614        // Encode any extra stack stack adjustments (done via push
615        // instructions).
616        CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
617      }
618
619      // Encode the number of registers saved. (Reverse the list first.)
620      std::reverse(&SavedRegs[0], &SavedRegs[SavedRegIdx]);
621      CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
622
623      // Get the encoding of the saved registers when we don't have a frame
624      // pointer.
625      uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx);
626      if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
627
628      // Encode the register encoding.
629      CompactUnwindEncoding |=
630        RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
631    }
632
633    return CompactUnwindEncoding;
634  }
635
636private:
637  /// \brief Get the compact unwind number for a given register. The number
638  /// corresponds to the enum lists in compact_unwind_encoding.h.
639  int getCompactUnwindRegNum(unsigned Reg) const {
640    static const MCPhysReg CU32BitRegs[7] = {
641      X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
642    };
643    static const MCPhysReg CU64BitRegs[] = {
644      X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
645    };
646    const MCPhysReg *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
647    for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
648      if (*CURegs == Reg)
649        return Idx;
650
651    return -1;
652  }
653
654  /// \brief Return the registers encoded for a compact encoding with a frame
655  /// pointer.
656  uint32_t encodeCompactUnwindRegistersWithFrame() const {
657    // Encode the registers in the order they were saved --- 3-bits per
658    // register. The list of saved registers is assumed to be in reverse
659    // order. The registers are numbered from 1 to CU_NUM_SAVED_REGS.
660    uint32_t RegEnc = 0;
661    for (int i = 0, Idx = 0; i != CU_NUM_SAVED_REGS; ++i) {
662      unsigned Reg = SavedRegs[i];
663      if (Reg == 0) break;
664
665      int CURegNum = getCompactUnwindRegNum(Reg);
666      if (CURegNum == -1) return ~0U;
667
668      // Encode the 3-bit register number in order, skipping over 3-bits for
669      // each register.
670      RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);
671    }
672
673    assert((RegEnc & 0x3FFFF) == RegEnc &&
674           "Invalid compact register encoding!");
675    return RegEnc;
676  }
677
678  /// \brief Create the permutation encoding used with frameless stacks. It is
679  /// passed the number of registers to be saved and an array of the registers
680  /// saved.
681  uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned RegCount) const {
682    // The saved registers are numbered from 1 to 6. In order to encode the
683    // order in which they were saved, we re-number them according to their
684    // place in the register order. The re-numbering is relative to the last
685    // re-numbered register. E.g., if we have registers {6, 2, 4, 5} saved in
686    // that order:
687    //
688    //    Orig  Re-Num
689    //    ----  ------
690    //     6       6
691    //     2       2
692    //     4       3
693    //     5       3
694    //
695    for (unsigned i = 0; i < RegCount; ++i) {
696      int CUReg = getCompactUnwindRegNum(SavedRegs[i]);
697      if (CUReg == -1) return ~0U;
698      SavedRegs[i] = CUReg;
699    }
700
701    // Reverse the list.
702    std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]);
703
704    uint32_t RenumRegs[CU_NUM_SAVED_REGS];
705    for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){
706      unsigned Countless = 0;
707      for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j)
708        if (SavedRegs[j] < SavedRegs[i])
709          ++Countless;
710
711      RenumRegs[i] = SavedRegs[i] - Countless - 1;
712    }
713
714    // Take the renumbered values and encode them into a 10-bit number.
715    uint32_t permutationEncoding = 0;
716    switch (RegCount) {
717    case 6:
718      permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
719                             + 6 * RenumRegs[2] +  2 * RenumRegs[3]
720                             +     RenumRegs[4];
721      break;
722    case 5:
723      permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
724                             + 6 * RenumRegs[3] +  2 * RenumRegs[4]
725                             +     RenumRegs[5];
726      break;
727    case 4:
728      permutationEncoding |=  60 * RenumRegs[2] + 12 * RenumRegs[3]
729                             + 3 * RenumRegs[4] +      RenumRegs[5];
730      break;
731    case 3:
732      permutationEncoding |=  20 * RenumRegs[3] +  4 * RenumRegs[4]
733                             +     RenumRegs[5];
734      break;
735    case 2:
736      permutationEncoding |=   5 * RenumRegs[4] +      RenumRegs[5];
737      break;
738    case 1:
739      permutationEncoding |=       RenumRegs[5];
740      break;
741    }
742
743    assert((permutationEncoding & 0x3FF) == permutationEncoding &&
744           "Invalid compact register encoding!");
745    return permutationEncoding;
746  }
747
748public:
749  DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU,
750                      bool Is64Bit)
751    : X86AsmBackend(T, CPU), MRI(MRI), Is64Bit(Is64Bit) {
752    memset(SavedRegs, 0, sizeof(SavedRegs));
753    OffsetSize = Is64Bit ? 8 : 4;
754    MoveInstrSize = Is64Bit ? 3 : 2;
755    StackDivide = Is64Bit ? 8 : 4;
756  }
757};
758
759class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
760public:
761  DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
762                         StringRef CPU)
763      : DarwinX86AsmBackend(T, MRI, CPU, false) {}
764
765  MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
766    return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
767                                     MachO::CPU_TYPE_I386,
768                                     MachO::CPU_SUBTYPE_I386_ALL);
769  }
770
771  /// \brief Generate the compact unwind encoding for the CFI instructions.
772  uint32_t generateCompactUnwindEncoding(
773                             ArrayRef<MCCFIInstruction> Instrs) const override {
774    return generateCompactUnwindEncodingImpl(Instrs);
775  }
776};
777
778class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
779  const MachO::CPUSubTypeX86 Subtype;
780public:
781  DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
782                         StringRef CPU, MachO::CPUSubTypeX86 st)
783      : DarwinX86AsmBackend(T, MRI, CPU, true), Subtype(st) {}
784
785  MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
786    return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
787                                     MachO::CPU_TYPE_X86_64, Subtype);
788  }
789
790  /// \brief Generate the compact unwind encoding for the CFI instructions.
791  uint32_t generateCompactUnwindEncoding(
792                             ArrayRef<MCCFIInstruction> Instrs) const override {
793    return generateCompactUnwindEncodingImpl(Instrs);
794  }
795};
796
797} // end anonymous namespace
798
799MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
800                                           const MCRegisterInfo &MRI,
801                                           const Triple &TheTriple,
802                                           StringRef CPU) {
803  if (TheTriple.isOSBinFormatMachO())
804    return new DarwinX86_32AsmBackend(T, MRI, CPU);
805
806  if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF())
807    return new WindowsX86AsmBackend(T, false, CPU);
808
809  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
810
811  if (TheTriple.isOSIAMCU())
812    return new ELFX86_IAMCUAsmBackend(T, OSABI, CPU);
813
814  return new ELFX86_32AsmBackend(T, OSABI, CPU);
815}
816
817MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
818                                           const MCRegisterInfo &MRI,
819                                           const Triple &TheTriple,
820                                           StringRef CPU) {
821  if (TheTriple.isOSBinFormatMachO()) {
822    MachO::CPUSubTypeX86 CS =
823        StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName())
824            .Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H)
825            .Default(MachO::CPU_SUBTYPE_X86_64_ALL);
826    return new DarwinX86_64AsmBackend(T, MRI, CPU, CS);
827  }
828
829  if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF())
830    return new WindowsX86AsmBackend(T, true, CPU);
831
832  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
833
834  if (TheTriple.getEnvironment() == Triple::GNUX32)
835    return new ELFX86_X32AsmBackend(T, OSABI, CPU);
836  return new ELFX86_64AsmBackend(T, OSABI, CPU);
837}
838