1234353Sdim//===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===// 2218885Sdim// 3218885Sdim// The LLVM Compiler Infrastructure 4218885Sdim// 5218885Sdim// This file is distributed under the University of Illinois Open Source 6218885Sdim// License. See LICENSE.TXT for details. 7218885Sdim// 8218885Sdim//===----------------------------------------------------------------------===// 9218885Sdim// 10218885Sdim// This file contains the PPC implementation of TargetFrameLowering class. 11218885Sdim// 12218885Sdim//===----------------------------------------------------------------------===// 13218885Sdim 14218885Sdim#include "PPCFrameLowering.h" 15249423Sdim#include "PPCInstrBuilder.h" 16218885Sdim#include "PPCInstrInfo.h" 17218885Sdim#include "PPCMachineFunctionInfo.h" 18276479Sdim#include "PPCSubtarget.h" 19288943Sdim#include "PPCTargetMachine.h" 20218885Sdim#include "llvm/CodeGen/MachineFrameInfo.h" 21218885Sdim#include "llvm/CodeGen/MachineFunction.h" 22218885Sdim#include "llvm/CodeGen/MachineInstrBuilder.h" 23218885Sdim#include "llvm/CodeGen/MachineModuleInfo.h" 24218885Sdim#include "llvm/CodeGen/MachineRegisterInfo.h" 25218885Sdim#include "llvm/CodeGen/RegisterScavenging.h" 26249423Sdim#include "llvm/IR/Function.h" 27218885Sdim#include "llvm/Target/TargetOptions.h" 28218885Sdim 29218885Sdimusing namespace llvm; 30218885Sdim 31218885Sdim/// VRRegNo - Map from a numbered VR register to its enum value. 32218885Sdim/// 33296417Sdimstatic const MCPhysReg VRRegNo[] = { 34218885Sdim PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 35218885Sdim PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 36218885Sdim PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 37218885Sdim PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 38218885Sdim}; 39218885Sdim 40288943Sdimstatic unsigned computeReturnSaveOffset(const PPCSubtarget &STI) { 41288943Sdim if (STI.isDarwinABI()) 42288943Sdim return STI.isPPC64() ? 16 : 8; 43288943Sdim // SVR4 ABI: 44288943Sdim return STI.isPPC64() ? 16 : 4; 45288943Sdim} 46288943Sdim 47288943Sdimstatic unsigned computeTOCSaveOffset(const PPCSubtarget &STI) { 48288943Sdim return STI.isELFv2ABI() ? 24 : 40; 49288943Sdim} 50288943Sdim 51288943Sdimstatic unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) { 52288943Sdim // For the Darwin ABI: 53288943Sdim // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area 54288943Sdim // for saving the frame pointer (if needed.) While the published ABI has 55288943Sdim // not used this slot since at least MacOSX 10.2, there is older code 56288943Sdim // around that does use it, and that needs to continue to work. 57288943Sdim if (STI.isDarwinABI()) 58288943Sdim return STI.isPPC64() ? -8U : -4U; 59288943Sdim 60288943Sdim // SVR4 ABI: First slot in the general register save area. 61288943Sdim return STI.isPPC64() ? -8U : -4U; 62288943Sdim} 63288943Sdim 64288943Sdimstatic unsigned computeLinkageSize(const PPCSubtarget &STI) { 65288943Sdim if (STI.isDarwinABI() || STI.isPPC64()) 66288943Sdim return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4); 67288943Sdim 68288943Sdim // SVR4 ABI: 69288943Sdim return 8; 70288943Sdim} 71288943Sdim 72288943Sdimstatic unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) { 73288943Sdim if (STI.isDarwinABI()) 74288943Sdim return STI.isPPC64() ? -16U : -8U; 75288943Sdim 76288943Sdim // SVR4 ABI: First slot in the general register save area. 77288943Sdim return STI.isPPC64() 78288943Sdim ? -16U 79288943Sdim : (STI.getTargetMachine().getRelocationModel() == Reloc::PIC_) 80288943Sdim ? -12U 81288943Sdim : -8U; 82288943Sdim} 83288943Sdim 84276479SdimPPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI) 85276479Sdim : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 86288943Sdim STI.getPlatformStackAlignment(), 0), 87288943Sdim Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)), 88288943Sdim TOCSaveOffset(computeTOCSaveOffset(Subtarget)), 89288943Sdim FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)), 90288943Sdim LinkageSize(computeLinkageSize(Subtarget)), 91288943Sdim BasePointerSaveOffset(computeBasePointerSaveOffset(STI)) {} 92276479Sdim 93276479Sdim// With the SVR4 ABI, callee-saved registers have fixed offsets on the stack. 94276479Sdimconst PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots( 95276479Sdim unsigned &NumEntries) const { 96276479Sdim if (Subtarget.isDarwinABI()) { 97276479Sdim NumEntries = 1; 98276479Sdim if (Subtarget.isPPC64()) { 99276479Sdim static const SpillSlot darwin64Offsets = {PPC::X31, -8}; 100276479Sdim return &darwin64Offsets; 101276479Sdim } else { 102276479Sdim static const SpillSlot darwinOffsets = {PPC::R31, -4}; 103276479Sdim return &darwinOffsets; 104276479Sdim } 105276479Sdim } 106276479Sdim 107276479Sdim // Early exit if not using the SVR4 ABI. 108276479Sdim if (!Subtarget.isSVR4ABI()) { 109276479Sdim NumEntries = 0; 110276479Sdim return nullptr; 111276479Sdim } 112276479Sdim 113276479Sdim // Note that the offsets here overlap, but this is fixed up in 114276479Sdim // processFunctionBeforeFrameFinalized. 115276479Sdim 116276479Sdim static const SpillSlot Offsets[] = { 117276479Sdim // Floating-point register save area offsets. 118276479Sdim {PPC::F31, -8}, 119276479Sdim {PPC::F30, -16}, 120276479Sdim {PPC::F29, -24}, 121276479Sdim {PPC::F28, -32}, 122276479Sdim {PPC::F27, -40}, 123276479Sdim {PPC::F26, -48}, 124276479Sdim {PPC::F25, -56}, 125276479Sdim {PPC::F24, -64}, 126276479Sdim {PPC::F23, -72}, 127276479Sdim {PPC::F22, -80}, 128276479Sdim {PPC::F21, -88}, 129276479Sdim {PPC::F20, -96}, 130276479Sdim {PPC::F19, -104}, 131276479Sdim {PPC::F18, -112}, 132276479Sdim {PPC::F17, -120}, 133276479Sdim {PPC::F16, -128}, 134276479Sdim {PPC::F15, -136}, 135276479Sdim {PPC::F14, -144}, 136276479Sdim 137276479Sdim // General register save area offsets. 138276479Sdim {PPC::R31, -4}, 139276479Sdim {PPC::R30, -8}, 140276479Sdim {PPC::R29, -12}, 141276479Sdim {PPC::R28, -16}, 142276479Sdim {PPC::R27, -20}, 143276479Sdim {PPC::R26, -24}, 144276479Sdim {PPC::R25, -28}, 145276479Sdim {PPC::R24, -32}, 146276479Sdim {PPC::R23, -36}, 147276479Sdim {PPC::R22, -40}, 148276479Sdim {PPC::R21, -44}, 149276479Sdim {PPC::R20, -48}, 150276479Sdim {PPC::R19, -52}, 151276479Sdim {PPC::R18, -56}, 152276479Sdim {PPC::R17, -60}, 153276479Sdim {PPC::R16, -64}, 154276479Sdim {PPC::R15, -68}, 155276479Sdim {PPC::R14, -72}, 156276479Sdim 157276479Sdim // CR save area offset. We map each of the nonvolatile CR fields 158276479Sdim // to the slot for CR2, which is the first of the nonvolatile CR 159276479Sdim // fields to be assigned, so that we only allocate one save slot. 160276479Sdim // See PPCRegisterInfo::hasReservedSpillSlot() for more information. 161276479Sdim {PPC::CR2, -4}, 162276479Sdim 163276479Sdim // VRSAVE save area offset. 164276479Sdim {PPC::VRSAVE, -4}, 165276479Sdim 166276479Sdim // Vector register save area 167276479Sdim {PPC::V31, -16}, 168276479Sdim {PPC::V30, -32}, 169276479Sdim {PPC::V29, -48}, 170276479Sdim {PPC::V28, -64}, 171276479Sdim {PPC::V27, -80}, 172276479Sdim {PPC::V26, -96}, 173276479Sdim {PPC::V25, -112}, 174276479Sdim {PPC::V24, -128}, 175276479Sdim {PPC::V23, -144}, 176276479Sdim {PPC::V22, -160}, 177276479Sdim {PPC::V21, -176}, 178276479Sdim {PPC::V20, -192}}; 179276479Sdim 180276479Sdim static const SpillSlot Offsets64[] = { 181276479Sdim // Floating-point register save area offsets. 182276479Sdim {PPC::F31, -8}, 183276479Sdim {PPC::F30, -16}, 184276479Sdim {PPC::F29, -24}, 185276479Sdim {PPC::F28, -32}, 186276479Sdim {PPC::F27, -40}, 187276479Sdim {PPC::F26, -48}, 188276479Sdim {PPC::F25, -56}, 189276479Sdim {PPC::F24, -64}, 190276479Sdim {PPC::F23, -72}, 191276479Sdim {PPC::F22, -80}, 192276479Sdim {PPC::F21, -88}, 193276479Sdim {PPC::F20, -96}, 194276479Sdim {PPC::F19, -104}, 195276479Sdim {PPC::F18, -112}, 196276479Sdim {PPC::F17, -120}, 197276479Sdim {PPC::F16, -128}, 198276479Sdim {PPC::F15, -136}, 199276479Sdim {PPC::F14, -144}, 200276479Sdim 201276479Sdim // General register save area offsets. 202276479Sdim {PPC::X31, -8}, 203276479Sdim {PPC::X30, -16}, 204276479Sdim {PPC::X29, -24}, 205276479Sdim {PPC::X28, -32}, 206276479Sdim {PPC::X27, -40}, 207276479Sdim {PPC::X26, -48}, 208276479Sdim {PPC::X25, -56}, 209276479Sdim {PPC::X24, -64}, 210276479Sdim {PPC::X23, -72}, 211276479Sdim {PPC::X22, -80}, 212276479Sdim {PPC::X21, -88}, 213276479Sdim {PPC::X20, -96}, 214276479Sdim {PPC::X19, -104}, 215276479Sdim {PPC::X18, -112}, 216276479Sdim {PPC::X17, -120}, 217276479Sdim {PPC::X16, -128}, 218276479Sdim {PPC::X15, -136}, 219276479Sdim {PPC::X14, -144}, 220276479Sdim 221276479Sdim // VRSAVE save area offset. 222276479Sdim {PPC::VRSAVE, -4}, 223276479Sdim 224276479Sdim // Vector register save area 225276479Sdim {PPC::V31, -16}, 226276479Sdim {PPC::V30, -32}, 227276479Sdim {PPC::V29, -48}, 228276479Sdim {PPC::V28, -64}, 229276479Sdim {PPC::V27, -80}, 230276479Sdim {PPC::V26, -96}, 231276479Sdim {PPC::V25, -112}, 232276479Sdim {PPC::V24, -128}, 233276479Sdim {PPC::V23, -144}, 234276479Sdim {PPC::V22, -160}, 235276479Sdim {PPC::V21, -176}, 236276479Sdim {PPC::V20, -192}}; 237276479Sdim 238276479Sdim if (Subtarget.isPPC64()) { 239276479Sdim NumEntries = array_lengthof(Offsets64); 240276479Sdim 241276479Sdim return Offsets64; 242276479Sdim } else { 243276479Sdim NumEntries = array_lengthof(Offsets); 244276479Sdim 245276479Sdim return Offsets; 246276479Sdim } 247276479Sdim} 248276479Sdim 249218885Sdim/// RemoveVRSaveCode - We have found that this function does not need any code 250218885Sdim/// to manipulate the VRSAVE register, even though it uses vector registers. 251218885Sdim/// This can happen when the only registers used are known to be live in or out 252218885Sdim/// of the function. Remove all of the VRSAVE related code from the function. 253243830Sdim/// FIXME: The removal of the code results in a compile failure at -O0 when the 254243830Sdim/// function contains a function call, as the GPR containing original VRSAVE 255243830Sdim/// contents is spilled and reloaded around the call. Without the prolog code, 256243830Sdim/// the spill instruction refers to an undefined register. This code needs 257243830Sdim/// to account for all uses of that GPR. 258218885Sdimstatic void RemoveVRSaveCode(MachineInstr *MI) { 259218885Sdim MachineBasicBlock *Entry = MI->getParent(); 260218885Sdim MachineFunction *MF = Entry->getParent(); 261218885Sdim 262218885Sdim // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 263218885Sdim MachineBasicBlock::iterator MBBI = MI; 264218885Sdim ++MBBI; 265218885Sdim assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 266218885Sdim MBBI->eraseFromParent(); 267218885Sdim 268218885Sdim bool RemovedAllMTVRSAVEs = true; 269218885Sdim // See if we can find and remove the MTVRSAVE instruction from all of the 270218885Sdim // epilog blocks. 271218885Sdim for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 272218885Sdim // If last instruction is a return instruction, add an epilogue 273296417Sdim if (I->isReturnBlock()) { 274218885Sdim bool FoundIt = false; 275218885Sdim for (MBBI = I->end(); MBBI != I->begin(); ) { 276218885Sdim --MBBI; 277218885Sdim if (MBBI->getOpcode() == PPC::MTVRSAVE) { 278218885Sdim MBBI->eraseFromParent(); // remove it. 279218885Sdim FoundIt = true; 280218885Sdim break; 281218885Sdim } 282218885Sdim } 283218885Sdim RemovedAllMTVRSAVEs &= FoundIt; 284218885Sdim } 285218885Sdim } 286218885Sdim 287218885Sdim // If we found and removed all MTVRSAVE instructions, remove the read of 288218885Sdim // VRSAVE as well. 289218885Sdim if (RemovedAllMTVRSAVEs) { 290218885Sdim MBBI = MI; 291218885Sdim assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 292218885Sdim --MBBI; 293218885Sdim assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 294218885Sdim MBBI->eraseFromParent(); 295218885Sdim } 296218885Sdim 297218885Sdim // Finally, nuke the UPDATE_VRSAVE. 298218885Sdim MI->eraseFromParent(); 299218885Sdim} 300218885Sdim 301218885Sdim// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 302218885Sdim// instruction selector. Based on the vector registers that have been used, 303218885Sdim// transform this into the appropriate ORI instruction. 304218885Sdimstatic void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 305218885Sdim MachineFunction *MF = MI->getParent()->getParent(); 306280031Sdim const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); 307218885Sdim DebugLoc dl = MI->getDebugLoc(); 308218885Sdim 309296417Sdim const MachineRegisterInfo &MRI = MF->getRegInfo(); 310218885Sdim unsigned UsedRegMask = 0; 311218885Sdim for (unsigned i = 0; i != 32; ++i) 312296417Sdim if (MRI.isPhysRegModified(VRRegNo[i])) 313218885Sdim UsedRegMask |= 1 << (31-i); 314218885Sdim 315218885Sdim // Live in and live out values already must be in the mask, so don't bother 316218885Sdim // marking them. 317218885Sdim for (MachineRegisterInfo::livein_iterator 318218885Sdim I = MF->getRegInfo().livein_begin(), 319218885Sdim E = MF->getRegInfo().livein_end(); I != E; ++I) { 320249423Sdim unsigned RegNo = TRI->getEncodingValue(I->first); 321218885Sdim if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 322218885Sdim UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 323218885Sdim } 324249423Sdim 325249423Sdim // Live out registers appear as use operands on return instructions. 326249423Sdim for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end(); 327249423Sdim UsedRegMask != 0 && BI != BE; ++BI) { 328249423Sdim const MachineBasicBlock &MBB = *BI; 329296417Sdim if (!MBB.isReturnBlock()) 330249423Sdim continue; 331249423Sdim const MachineInstr &Ret = MBB.back(); 332249423Sdim for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) { 333249423Sdim const MachineOperand &MO = Ret.getOperand(I); 334249423Sdim if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg())) 335249423Sdim continue; 336249423Sdim unsigned RegNo = TRI->getEncodingValue(MO.getReg()); 337249423Sdim UsedRegMask &= ~(1 << (31-RegNo)); 338249423Sdim } 339218885Sdim } 340218885Sdim 341218885Sdim // If no registers are used, turn this into a copy. 342218885Sdim if (UsedRegMask == 0) { 343218885Sdim // Remove all VRSAVE code. 344218885Sdim RemoveVRSaveCode(MI); 345218885Sdim return; 346218885Sdim } 347218885Sdim 348218885Sdim unsigned SrcReg = MI->getOperand(1).getReg(); 349218885Sdim unsigned DstReg = MI->getOperand(0).getReg(); 350218885Sdim 351218885Sdim if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 352218885Sdim if (DstReg != SrcReg) 353218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 354218885Sdim .addReg(SrcReg) 355218885Sdim .addImm(UsedRegMask); 356218885Sdim else 357218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 358218885Sdim .addReg(SrcReg, RegState::Kill) 359218885Sdim .addImm(UsedRegMask); 360218885Sdim } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 361218885Sdim if (DstReg != SrcReg) 362218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 363218885Sdim .addReg(SrcReg) 364218885Sdim .addImm(UsedRegMask >> 16); 365218885Sdim else 366218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 367218885Sdim .addReg(SrcReg, RegState::Kill) 368218885Sdim .addImm(UsedRegMask >> 16); 369218885Sdim } else { 370218885Sdim if (DstReg != SrcReg) 371218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 372218885Sdim .addReg(SrcReg) 373218885Sdim .addImm(UsedRegMask >> 16); 374218885Sdim else 375218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 376218885Sdim .addReg(SrcReg, RegState::Kill) 377218885Sdim .addImm(UsedRegMask >> 16); 378218885Sdim 379218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 380218885Sdim .addReg(DstReg, RegState::Kill) 381218885Sdim .addImm(UsedRegMask & 0xFFFF); 382218885Sdim } 383218885Sdim 384218885Sdim // Remove the old UPDATE_VRSAVE instruction. 385218885Sdim MI->eraseFromParent(); 386218885Sdim} 387218885Sdim 388243830Sdimstatic bool spillsCR(const MachineFunction &MF) { 389243830Sdim const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 390243830Sdim return FuncInfo->isCRSpilled(); 391243830Sdim} 392243830Sdim 393249423Sdimstatic bool spillsVRSAVE(const MachineFunction &MF) { 394249423Sdim const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 395249423Sdim return FuncInfo->isVRSAVESpilled(); 396249423Sdim} 397249423Sdim 398249423Sdimstatic bool hasSpills(const MachineFunction &MF) { 399249423Sdim const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 400249423Sdim return FuncInfo->hasSpills(); 401249423Sdim} 402249423Sdim 403249423Sdimstatic bool hasNonRISpills(const MachineFunction &MF) { 404249423Sdim const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 405249423Sdim return FuncInfo->hasNonRISpills(); 406249423Sdim} 407249423Sdim 408288943Sdim/// MustSaveLR - Return true if this function requires that we save the LR 409288943Sdim/// register onto the stack in the prolog and restore it in the epilog of the 410288943Sdim/// function. 411288943Sdimstatic bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 412288943Sdim const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 413288943Sdim 414288943Sdim // We need a save/restore of LR if there is any def of LR (which is 415288943Sdim // defined by calls, including the PIC setup sequence), or if there is 416288943Sdim // some use of the LR stack slot (e.g. for builtin_return_address). 417288943Sdim // (LR comes in 32 and 64 bit versions.) 418288943Sdim MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 419288943Sdim return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 420288943Sdim} 421288943Sdim 422218885Sdim/// determineFrameLayout - Determine the size of the frame and maximum call 423218885Sdim/// frame size. 424249423Sdimunsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF, 425249423Sdim bool UpdateMF, 426249423Sdim bool UseEstimate) const { 427218885Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 428218885Sdim 429218885Sdim // Get the number of bytes to allocate from the FrameInfo 430249423Sdim unsigned FrameSize = 431249423Sdim UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize(); 432218885Sdim 433261991Sdim // Get stack alignments. The frame must be aligned to the greatest of these: 434261991Sdim unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI 435261991Sdim unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame 436261991Sdim unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1; 437218885Sdim 438261991Sdim const PPCRegisterInfo *RegInfo = 439288943Sdim static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 440261991Sdim 441218885Sdim // If we are a leaf function, and use up to 224 bytes of stack space, 442218885Sdim // don't have a frame pointer, calls, or dynamic alloca then we do not need 443251662Sdim // to adjust the stack pointer (we fit in the Red Zone). 444249423Sdim // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate 445249423Sdim // stackless code if all local vars are reg-allocated. 446288943Sdim bool DisableRedZone = MF.getFunction()->hasFnAttribute(Attribute::NoRedZone); 447288943Sdim unsigned LR = RegInfo->getRARegister(); 448218885Sdim if (!DisableRedZone && 449249423Sdim (Subtarget.isPPC64() || // 32-bit SVR4, no stack- 450249423Sdim !Subtarget.isSVR4ABI() || // allocated locals. 451276479Sdim FrameSize == 0) && 452218885Sdim FrameSize <= 224 && // Fits in red zone. 453218885Sdim !MFI->hasVarSizedObjects() && // No dynamic alloca. 454218885Sdim !MFI->adjustsStack() && // No calls. 455288943Sdim !MustSaveLR(MF, LR) && 456261991Sdim !RegInfo->hasBasePointer(MF)) { // No special alignment. 457218885Sdim // No need for frame 458249423Sdim if (UpdateMF) 459249423Sdim MFI->setStackSize(0); 460249423Sdim return 0; 461218885Sdim } 462218885Sdim 463218885Sdim // Get the maximum call frame size of all the calls. 464218885Sdim unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 465218885Sdim 466276479Sdim // Maximum call frame needs to be at least big enough for linkage area. 467288943Sdim unsigned minCallFrameSize = getLinkageSize(); 468218885Sdim maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 469218885Sdim 470218885Sdim // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 471218885Sdim // that allocations will be aligned. 472218885Sdim if (MFI->hasVarSizedObjects()) 473218885Sdim maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 474218885Sdim 475218885Sdim // Update maximum call frame size. 476249423Sdim if (UpdateMF) 477249423Sdim MFI->setMaxCallFrameSize(maxCallFrameSize); 478218885Sdim 479218885Sdim // Include call frame size in total. 480218885Sdim FrameSize += maxCallFrameSize; 481218885Sdim 482218885Sdim // Make sure the frame is aligned. 483218885Sdim FrameSize = (FrameSize + AlignMask) & ~AlignMask; 484218885Sdim 485218885Sdim // Update frame info. 486249423Sdim if (UpdateMF) 487249423Sdim MFI->setStackSize(FrameSize); 488249423Sdim 489249423Sdim return FrameSize; 490218885Sdim} 491218885Sdim 492218885Sdim// hasFP - Return true if the specified function actually has a dedicated frame 493218885Sdim// pointer register. 494218885Sdimbool PPCFrameLowering::hasFP(const MachineFunction &MF) const { 495218885Sdim const MachineFrameInfo *MFI = MF.getFrameInfo(); 496218885Sdim // FIXME: This is pretty much broken by design: hasFP() might be called really 497218885Sdim // early, before the stack layout was calculated and thus hasFP() might return 498218885Sdim // true or false here depending on the time of call. 499218885Sdim return (MFI->getStackSize()) && needsFP(MF); 500218885Sdim} 501218885Sdim 502218885Sdim// needsFP - Return true if the specified function should have a dedicated frame 503218885Sdim// pointer register. This is true if the function has variable sized allocas or 504218885Sdim// if frame pointer elimination is disabled. 505218885Sdimbool PPCFrameLowering::needsFP(const MachineFunction &MF) const { 506218885Sdim const MachineFrameInfo *MFI = MF.getFrameInfo(); 507218885Sdim 508218885Sdim // Naked functions have no stack frame pushed, so we don't have a frame 509218885Sdim // pointer. 510288943Sdim if (MF.getFunction()->hasFnAttribute(Attribute::Naked)) 511218885Sdim return false; 512218885Sdim 513234353Sdim return MF.getTarget().Options.DisableFramePointerElim(MF) || 514234353Sdim MFI->hasVarSizedObjects() || 515280031Sdim MFI->hasStackMap() || MFI->hasPatchPoint() || 516234353Sdim (MF.getTarget().Options.GuaranteedTailCallOpt && 517234353Sdim MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 518218885Sdim} 519218885Sdim 520249423Sdimvoid PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const { 521249423Sdim bool is31 = needsFP(MF); 522249423Sdim unsigned FPReg = is31 ? PPC::R31 : PPC::R1; 523249423Sdim unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1; 524218885Sdim 525261991Sdim const PPCRegisterInfo *RegInfo = 526288943Sdim static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 527261991Sdim bool HasBP = RegInfo->hasBasePointer(MF); 528276479Sdim unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg; 529261991Sdim unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg; 530261991Sdim 531249423Sdim for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); 532249423Sdim BI != BE; ++BI) 533249423Sdim for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) { 534249423Sdim --MBBI; 535249423Sdim for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) { 536249423Sdim MachineOperand &MO = MBBI->getOperand(I); 537249423Sdim if (!MO.isReg()) 538249423Sdim continue; 539249423Sdim 540249423Sdim switch (MO.getReg()) { 541249423Sdim case PPC::FP: 542249423Sdim MO.setReg(FPReg); 543249423Sdim break; 544249423Sdim case PPC::FP8: 545249423Sdim MO.setReg(FP8Reg); 546249423Sdim break; 547261991Sdim case PPC::BP: 548261991Sdim MO.setReg(BPReg); 549261991Sdim break; 550261991Sdim case PPC::BP8: 551261991Sdim MO.setReg(BP8Reg); 552261991Sdim break; 553261991Sdim 554249423Sdim } 555249423Sdim } 556249423Sdim } 557249423Sdim} 558249423Sdim 559296417Sdim/* This function will do the following: 560296417Sdim - If MBB is an entry or exit block, set SR1 and SR2 to R0 and R12 561296417Sdim respectively (defaults recommended by the ABI) and return true 562296417Sdim - If MBB is not an entry block, initialize the register scavenger and look 563296417Sdim for available registers. 564296417Sdim - If the defaults (R0/R12) are available, return true 565296417Sdim - If TwoUniqueRegsRequired is set to true, it looks for two unique 566296417Sdim registers. Otherwise, look for a single available register. 567296417Sdim - If the required registers are found, set SR1 and SR2 and return true. 568296417Sdim - If the required registers are not found, set SR2 or both SR1 and SR2 to 569296417Sdim PPC::NoRegister and return false. 570296417Sdim 571296417Sdim Note that if both SR1 and SR2 are valid parameters and TwoUniqueRegsRequired 572296417Sdim is not set, this function will attempt to find two different registers, but 573296417Sdim still return true if only one register is available (and set SR1 == SR2). 574296417Sdim*/ 575296417Sdimbool 576296417SdimPPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB, 577296417Sdim bool UseAtEnd, 578296417Sdim bool TwoUniqueRegsRequired, 579296417Sdim unsigned *SR1, 580296417Sdim unsigned *SR2) const { 581296417Sdim RegScavenger RS; 582296417Sdim unsigned R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0; 583296417Sdim unsigned R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12; 584296417Sdim 585296417Sdim // Set the defaults for the two scratch registers. 586296417Sdim if (SR1) 587296417Sdim *SR1 = R0; 588296417Sdim 589296417Sdim if (SR2) { 590296417Sdim assert (SR1 && "Asking for the second scratch register but not the first?"); 591296417Sdim *SR2 = R12; 592296417Sdim } 593296417Sdim 594296417Sdim // If MBB is an entry or exit block, use R0 and R12 as the scratch registers. 595296417Sdim if ((UseAtEnd && MBB->isReturnBlock()) || 596296417Sdim (!UseAtEnd && (&MBB->getParent()->front() == MBB))) 597296417Sdim return true; 598296417Sdim 599296417Sdim RS.enterBasicBlock(MBB); 600296417Sdim 601296417Sdim if (UseAtEnd && !MBB->empty()) { 602296417Sdim // The scratch register will be used at the end of the block, so must 603296417Sdim // consider all registers used within the block 604296417Sdim 605296417Sdim MachineBasicBlock::iterator MBBI = MBB->getFirstTerminator(); 606296417Sdim // If no terminator, back iterator up to previous instruction. 607296417Sdim if (MBBI == MBB->end()) 608296417Sdim MBBI = std::prev(MBBI); 609296417Sdim 610296417Sdim if (MBBI != MBB->begin()) 611296417Sdim RS.forward(MBBI); 612296417Sdim } 613296417Sdim 614296417Sdim // If the two registers are available, we're all good. 615296417Sdim // Note that we only return here if both R0 and R12 are available because 616296417Sdim // although the function may not require two unique registers, it may benefit 617296417Sdim // from having two so we should try to provide them. 618296417Sdim if (!RS.isRegUsed(R0) && !RS.isRegUsed(R12)) 619296417Sdim return true; 620296417Sdim 621296417Sdim // Get the list of callee-saved registers for the target. 622296417Sdim const PPCRegisterInfo *RegInfo = 623296417Sdim static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 624296417Sdim const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent()); 625296417Sdim 626296417Sdim // Get all the available registers in the block. 627296417Sdim BitVector BV = RS.getRegsAvailable(Subtarget.isPPC64() ? &PPC::G8RCRegClass : 628296417Sdim &PPC::GPRCRegClass); 629296417Sdim 630296417Sdim // We shouldn't use callee-saved registers as scratch registers as they may be 631296417Sdim // available when looking for a candidate block for shrink wrapping but not 632296417Sdim // available when the actual prologue/epilogue is being emitted because they 633296417Sdim // were added as live-in to the prologue block by PrologueEpilogueInserter. 634296417Sdim for (int i = 0; CSRegs[i]; ++i) 635296417Sdim BV.reset(CSRegs[i]); 636296417Sdim 637296417Sdim // Set the first scratch register to the first available one. 638296417Sdim if (SR1) { 639296417Sdim int FirstScratchReg = BV.find_first(); 640296417Sdim *SR1 = FirstScratchReg == -1 ? (unsigned)PPC::NoRegister : FirstScratchReg; 641296417Sdim } 642296417Sdim 643296417Sdim // If there is another one available, set the second scratch register to that. 644296417Sdim // Otherwise, set it to either PPC::NoRegister if this function requires two 645296417Sdim // or to whatever SR1 is set to if this function doesn't require two. 646296417Sdim if (SR2) { 647296417Sdim int SecondScratchReg = BV.find_next(*SR1); 648296417Sdim if (SecondScratchReg != -1) 649296417Sdim *SR2 = SecondScratchReg; 650296417Sdim else 651296417Sdim *SR2 = TwoUniqueRegsRequired ? (unsigned)PPC::NoRegister : *SR1; 652296417Sdim } 653296417Sdim 654296417Sdim // Now that we've done our best to provide both registers, double check 655296417Sdim // whether we were unable to provide enough. 656296417Sdim if (BV.count() < (TwoUniqueRegsRequired ? 2 : 1)) 657296417Sdim return false; 658296417Sdim 659296417Sdim return true; 660296417Sdim} 661296417Sdim 662296417Sdim// We need a scratch register for spilling LR and for spilling CR. By default, 663296417Sdim// we use two scratch registers to hide latency. However, if only one scratch 664296417Sdim// register is available, we can adjust for that by not overlapping the spill 665296417Sdim// code. However, if we need to realign the stack (i.e. have a base pointer) 666296417Sdim// and the stack frame is large, we need two scratch registers. 667296417Sdimbool 668296417SdimPPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const { 669296417Sdim const PPCRegisterInfo *RegInfo = 670296417Sdim static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 671296417Sdim MachineFunction &MF = *(MBB->getParent()); 672296417Sdim bool HasBP = RegInfo->hasBasePointer(MF); 673296417Sdim unsigned FrameSize = determineFrameLayout(MF, false); 674296417Sdim int NegFrameSize = -FrameSize; 675296417Sdim bool IsLargeFrame = !isInt<16>(NegFrameSize); 676296417Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 677296417Sdim unsigned MaxAlign = MFI->getMaxAlignment(); 678296417Sdim 679296417Sdim return IsLargeFrame && HasBP && MaxAlign > 1; 680296417Sdim} 681296417Sdim 682296417Sdimbool PPCFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const { 683296417Sdim MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB); 684296417Sdim 685296417Sdim return findScratchRegister(TmpMBB, false, 686296417Sdim twoUniqueScratchRegsRequired(TmpMBB)); 687296417Sdim} 688296417Sdim 689296417Sdimbool PPCFrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const { 690296417Sdim MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB); 691296417Sdim 692296417Sdim return findScratchRegister(TmpMBB, true); 693296417Sdim} 694296417Sdim 695288943Sdimvoid PPCFrameLowering::emitPrologue(MachineFunction &MF, 696288943Sdim MachineBasicBlock &MBB) const { 697218885Sdim MachineBasicBlock::iterator MBBI = MBB.begin(); 698218885Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 699218885Sdim const PPCInstrInfo &TII = 700288943Sdim *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 701261991Sdim const PPCRegisterInfo *RegInfo = 702288943Sdim static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 703218885Sdim 704218885Sdim MachineModuleInfo &MMI = MF.getMMI(); 705261991Sdim const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); 706218885Sdim DebugLoc dl; 707277320Sdim bool needsCFI = MMI.hasDebugInfo() || 708223017Sdim MF.getFunction()->needsUnwindTableEntry(); 709218885Sdim 710261991Sdim // Get processor type. 711261991Sdim bool isPPC64 = Subtarget.isPPC64(); 712261991Sdim // Get the ABI. 713261991Sdim bool isSVR4ABI = Subtarget.isSVR4ABI(); 714276479Sdim bool isELFv2ABI = Subtarget.isELFv2ABI(); 715288943Sdim assert((Subtarget.isDarwinABI() || isSVR4ABI) && 716261991Sdim "Currently only Darwin and SVR4 ABIs are supported for PowerPC."); 717261991Sdim 718218885Sdim // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 719218885Sdim // process it. 720261991Sdim if (!isSVR4ABI) 721243830Sdim for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 722243830Sdim if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 723243830Sdim HandleVRSaveUpdate(MBBI, TII); 724243830Sdim break; 725243830Sdim } 726218885Sdim } 727218885Sdim 728296417Sdim // Move MBBI back to the beginning of the prologue block. 729218885Sdim MBBI = MBB.begin(); 730218885Sdim 731218885Sdim // Work out frame sizes. 732249423Sdim unsigned FrameSize = determineFrameLayout(MF); 733218885Sdim int NegFrameSize = -FrameSize; 734261991Sdim if (!isInt<32>(NegFrameSize)) 735261991Sdim llvm_unreachable("Unhandled stack size!"); 736218885Sdim 737249423Sdim if (MFI->isFrameAddressTaken()) 738249423Sdim replaceFPWithRealFP(MF); 739249423Sdim 740218885Sdim // Check if the link register (LR) must be saved. 741218885Sdim PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 742218885Sdim bool MustSaveLR = FI->mustSaveLR(); 743261991Sdim const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs(); 744296417Sdim bool MustSaveCR = !MustSaveCRs.empty(); 745261991Sdim // Do we have a frame pointer and/or base pointer for this function? 746218885Sdim bool HasFP = hasFP(MF); 747261991Sdim bool HasBP = RegInfo->hasBasePointer(MF); 748218885Sdim 749261991Sdim unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1; 750270147Srdivacky unsigned BPReg = RegInfo->getBaseRegister(MF); 751261991Sdim unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 752261991Sdim unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR; 753296417Sdim unsigned ScratchReg = 0; 754261991Sdim unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg 755261991Sdim // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.) 756261991Sdim const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8 757261991Sdim : PPC::MFLR ); 758261991Sdim const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD 759261991Sdim : PPC::STW ); 760261991Sdim const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU 761261991Sdim : PPC::STWU ); 762261991Sdim const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX 763261991Sdim : PPC::STWUX); 764261991Sdim const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8 765261991Sdim : PPC::LIS ); 766261991Sdim const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8 767261991Sdim : PPC::ORI ); 768261991Sdim const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8 769261991Sdim : PPC::OR ); 770261991Sdim const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8 771261991Sdim : PPC::SUBFC); 772261991Sdim const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8 773261991Sdim : PPC::SUBFIC); 774261991Sdim 775261991Sdim // Regarding this assert: Even though LR is saved in the caller's frame (i.e., 776261991Sdim // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no 777261991Sdim // Red Zone, an asynchronous event (a form of "callee") could claim a frame & 778261991Sdim // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR. 779261991Sdim assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) && 780261991Sdim "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4."); 781261991Sdim 782296417Sdim // Using the same bool variable as below to supress compiler warnings. 783296417Sdim bool SingleScratchReg = 784296417Sdim findScratchRegister(&MBB, false, twoUniqueScratchRegsRequired(&MBB), 785296417Sdim &ScratchReg, &TempReg); 786296417Sdim assert(SingleScratchReg && 787296417Sdim "Required number of registers not available in this block"); 788296417Sdim 789296417Sdim SingleScratchReg = ScratchReg == TempReg; 790296417Sdim 791288943Sdim int LROffset = getReturnSaveOffset(); 792218885Sdim 793218885Sdim int FPOffset = 0; 794218885Sdim if (HasFP) { 795261991Sdim if (isSVR4ABI) { 796218885Sdim MachineFrameInfo *FFI = MF.getFrameInfo(); 797218885Sdim int FPIndex = FI->getFramePointerSaveIndex(); 798218885Sdim assert(FPIndex && "No Frame Pointer Save Slot!"); 799218885Sdim FPOffset = FFI->getObjectOffset(FPIndex); 800218885Sdim } else { 801288943Sdim FPOffset = getFramePointerSaveOffset(); 802218885Sdim } 803218885Sdim } 804218885Sdim 805261991Sdim int BPOffset = 0; 806261991Sdim if (HasBP) { 807261991Sdim if (isSVR4ABI) { 808261991Sdim MachineFrameInfo *FFI = MF.getFrameInfo(); 809261991Sdim int BPIndex = FI->getBasePointerSaveIndex(); 810261991Sdim assert(BPIndex && "No Base Pointer Save Slot!"); 811261991Sdim BPOffset = FFI->getObjectOffset(BPIndex); 812261991Sdim } else { 813288943Sdim BPOffset = getBasePointerSaveOffset(); 814251662Sdim } 815261991Sdim } 816251662Sdim 817280031Sdim int PBPOffset = 0; 818280031Sdim if (FI->usesPICBase()) { 819280031Sdim MachineFrameInfo *FFI = MF.getFrameInfo(); 820280031Sdim int PBPIndex = FI->getPICBasePointerSaveIndex(); 821280031Sdim assert(PBPIndex && "No PIC Base Pointer Save Slot!"); 822280031Sdim PBPOffset = FFI->getObjectOffset(PBPIndex); 823280031Sdim } 824280031Sdim 825261991Sdim // Get stack alignments. 826261991Sdim unsigned MaxAlign = MFI->getMaxAlignment(); 827261991Sdim if (HasBP && MaxAlign > 1) 828261991Sdim assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 829261991Sdim "Invalid alignment!"); 830218885Sdim 831261991Sdim // Frames of 32KB & larger require special handling because they cannot be 832261991Sdim // indexed into with a simple STDU/STWU/STD/STW immediate offset operand. 833261991Sdim bool isLargeFrame = !isInt<16>(NegFrameSize); 834251662Sdim 835296417Sdim assert((isPPC64 || !MustSaveCR) && 836296417Sdim "Prologue CR saving supported only in 64-bit mode"); 837296417Sdim 838296417Sdim // If we need to spill the CR and the LR but we don't have two separate 839296417Sdim // registers available, we must spill them one at a time 840296417Sdim if (MustSaveCR && SingleScratchReg && MustSaveLR) { 841296417Sdim // FIXME: In the ELFv2 ABI, we are not required to save all CR fields. 842296417Sdim // If only one or two CR fields are clobbered, it could be more 843296417Sdim // efficient to use mfocrf to selectively save just those fields. 844296417Sdim MachineInstrBuilder MIB = 845296417Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg); 846296417Sdim for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 847296417Sdim MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill); 848296417Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8)) 849296417Sdim .addReg(TempReg, getKillRegState(true)) 850296417Sdim .addImm(8) 851296417Sdim .addReg(SPReg); 852296417Sdim } 853296417Sdim 854261991Sdim if (MustSaveLR) 855261991Sdim BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg); 856218885Sdim 857296417Sdim if (MustSaveCR && 858296417Sdim !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64 859276479Sdim // FIXME: In the ELFv2 ABI, we are not required to save all CR fields. 860276479Sdim // If only one or two CR fields are clobbered, it could be more 861276479Sdim // efficient to use mfocrf to selectively save just those fields. 862261991Sdim MachineInstrBuilder MIB = 863261991Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg); 864261991Sdim for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 865261991Sdim MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill); 866218885Sdim } 867218885Sdim 868261991Sdim if (HasFP) 869261991Sdim // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 870261991Sdim BuildMI(MBB, MBBI, dl, StoreInst) 871261991Sdim .addReg(FPReg) 872261991Sdim .addImm(FPOffset) 873261991Sdim .addReg(SPReg); 874261991Sdim 875280031Sdim if (FI->usesPICBase()) 876280031Sdim // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 877280031Sdim BuildMI(MBB, MBBI, dl, StoreInst) 878280031Sdim .addReg(PPC::R30) 879280031Sdim .addImm(PBPOffset) 880280031Sdim .addReg(SPReg); 881280031Sdim 882261991Sdim if (HasBP) 883261991Sdim // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 884261991Sdim BuildMI(MBB, MBBI, dl, StoreInst) 885261991Sdim .addReg(BPReg) 886261991Sdim .addImm(BPOffset) 887261991Sdim .addReg(SPReg); 888261991Sdim 889261991Sdim if (MustSaveLR) 890261991Sdim // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 891261991Sdim BuildMI(MBB, MBBI, dl, StoreInst) 892261991Sdim .addReg(ScratchReg) 893261991Sdim .addImm(LROffset) 894261991Sdim .addReg(SPReg); 895261991Sdim 896296417Sdim if (MustSaveCR && 897296417Sdim !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 898261991Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8)) 899261991Sdim .addReg(TempReg, getKillRegState(true)) 900261991Sdim .addImm(8) 901261991Sdim .addReg(SPReg); 902261991Sdim 903261991Sdim // Skip the rest if this is a leaf function & all spills fit in the Red Zone. 904218885Sdim if (!FrameSize) return; 905218885Sdim 906218885Sdim // Adjust stack pointer: r1 += NegFrameSize. 907218885Sdim // If there is a preferred stack alignment, align R1 now 908218885Sdim 909261991Sdim if (HasBP) { 910261991Sdim // Save a copy of r1 as the base pointer. 911261991Sdim BuildMI(MBB, MBBI, dl, OrInst, BPReg) 912261991Sdim .addReg(SPReg) 913261991Sdim .addReg(SPReg); 914261991Sdim } 915261991Sdim 916296417Sdim // This condition must be kept in sync with canUseAsPrologue. 917261991Sdim if (HasBP && MaxAlign > 1) { 918261991Sdim if (isPPC64) 919261991Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg) 920261991Sdim .addReg(SPReg) 921218885Sdim .addImm(0) 922261991Sdim .addImm(64 - Log2_32(MaxAlign)); 923261991Sdim else // PPC32... 924261991Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg) 925261991Sdim .addReg(SPReg) 926261991Sdim .addImm(0) 927218885Sdim .addImm(32 - Log2_32(MaxAlign)) 928218885Sdim .addImm(31); 929261991Sdim if (!isLargeFrame) { 930261991Sdim BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg) 931261991Sdim .addReg(ScratchReg, RegState::Kill) 932218885Sdim .addImm(NegFrameSize); 933218885Sdim } else { 934296417Sdim assert(!SingleScratchReg && "Only a single scratch reg available"); 935261991Sdim BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg) 936218885Sdim .addImm(NegFrameSize >> 16); 937261991Sdim BuildMI(MBB, MBBI, dl, OrImmInst, TempReg) 938261991Sdim .addReg(TempReg, RegState::Kill) 939218885Sdim .addImm(NegFrameSize & 0xFFFF); 940261991Sdim BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg) 941261991Sdim .addReg(ScratchReg, RegState::Kill) 942261991Sdim .addReg(TempReg, RegState::Kill); 943218885Sdim } 944261991Sdim BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg) 945261991Sdim .addReg(SPReg, RegState::Kill) 946261991Sdim .addReg(SPReg) 947261991Sdim .addReg(ScratchReg); 948218885Sdim 949261991Sdim } else if (!isLargeFrame) { 950261991Sdim BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg) 951261991Sdim .addReg(SPReg) 952261991Sdim .addImm(NegFrameSize) 953261991Sdim .addReg(SPReg); 954261991Sdim 955261991Sdim } else { 956261991Sdim BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 957261991Sdim .addImm(NegFrameSize >> 16); 958261991Sdim BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 959261991Sdim .addReg(ScratchReg, RegState::Kill) 960261991Sdim .addImm(NegFrameSize & 0xFFFF); 961261991Sdim BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg) 962261991Sdim .addReg(SPReg, RegState::Kill) 963261991Sdim .addReg(SPReg) 964261991Sdim .addReg(ScratchReg); 965218885Sdim } 966218885Sdim 967277320Sdim // Add Call Frame Information for the instructions we generated above. 968277320Sdim if (needsCFI) { 969277320Sdim unsigned CFIIndex; 970277320Sdim 971277320Sdim if (HasBP) { 972277320Sdim // Define CFA in terms of BP. Do this in preference to using FP/SP, 973277320Sdim // because if the stack needed aligning then CFA won't be at a fixed 974277320Sdim // offset from FP/SP. 975277320Sdim unsigned Reg = MRI->getDwarfRegNum(BPReg, true); 976277320Sdim CFIIndex = MMI.addFrameInst( 977277320Sdim MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); 978277320Sdim } else { 979277320Sdim // Adjust the definition of CFA to account for the change in SP. 980277320Sdim assert(NegFrameSize); 981277320Sdim CFIIndex = MMI.addFrameInst( 982277320Sdim MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize)); 983277320Sdim } 984276479Sdim BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 985276479Sdim .addCFIIndex(CFIIndex); 986218885Sdim 987218885Sdim if (HasFP) { 988277320Sdim // Describe where FP was saved, at a fixed offset from CFA. 989261991Sdim unsigned Reg = MRI->getDwarfRegNum(FPReg, true); 990276479Sdim CFIIndex = MMI.addFrameInst( 991276479Sdim MCCFIInstruction::createOffset(nullptr, Reg, FPOffset)); 992276479Sdim BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 993276479Sdim .addCFIIndex(CFIIndex); 994218885Sdim } 995218885Sdim 996280031Sdim if (FI->usesPICBase()) { 997280031Sdim // Describe where FP was saved, at a fixed offset from CFA. 998280031Sdim unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true); 999280031Sdim CFIIndex = MMI.addFrameInst( 1000280031Sdim MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset)); 1001280031Sdim BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1002280031Sdim .addCFIIndex(CFIIndex); 1003280031Sdim } 1004280031Sdim 1005261991Sdim if (HasBP) { 1006277320Sdim // Describe where BP was saved, at a fixed offset from CFA. 1007261991Sdim unsigned Reg = MRI->getDwarfRegNum(BPReg, true); 1008276479Sdim CFIIndex = MMI.addFrameInst( 1009276479Sdim MCCFIInstruction::createOffset(nullptr, Reg, BPOffset)); 1010276479Sdim BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1011276479Sdim .addCFIIndex(CFIIndex); 1012261991Sdim } 1013261991Sdim 1014218885Sdim if (MustSaveLR) { 1015277320Sdim // Describe where LR was saved, at a fixed offset from CFA. 1016261991Sdim unsigned Reg = MRI->getDwarfRegNum(LRReg, true); 1017276479Sdim CFIIndex = MMI.addFrameInst( 1018276479Sdim MCCFIInstruction::createOffset(nullptr, Reg, LROffset)); 1019276479Sdim BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1020276479Sdim .addCFIIndex(CFIIndex); 1021218885Sdim } 1022218885Sdim } 1023218885Sdim 1024218885Sdim // If there is a frame pointer, copy R1 into R31 1025218885Sdim if (HasFP) { 1026261991Sdim BuildMI(MBB, MBBI, dl, OrInst, FPReg) 1027261991Sdim .addReg(SPReg) 1028261991Sdim .addReg(SPReg); 1029218885Sdim 1030277320Sdim if (!HasBP && needsCFI) { 1031277320Sdim // Change the definition of CFA from SP+offset to FP+offset, because SP 1032277320Sdim // will change at every alloca. 1033276479Sdim unsigned Reg = MRI->getDwarfRegNum(FPReg, true); 1034276479Sdim unsigned CFIIndex = MMI.addFrameInst( 1035276479Sdim MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); 1036218885Sdim 1037276479Sdim BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1038276479Sdim .addCFIIndex(CFIIndex); 1039218885Sdim } 1040218885Sdim } 1041218885Sdim 1042277320Sdim if (needsCFI) { 1043277320Sdim // Describe where callee saved registers were saved, at fixed offsets from 1044277320Sdim // CFA. 1045218885Sdim const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1046218885Sdim for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 1047218885Sdim unsigned Reg = CSI[I].getReg(); 1048218885Sdim if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 1049223017Sdim 1050223017Sdim // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just 1051223017Sdim // subregisters of CR2. We just need to emit a move of CR2. 1052239462Sdim if (PPC::CRBITRCRegClass.contains(Reg)) 1053223017Sdim continue; 1054223017Sdim 1055243830Sdim // For SVR4, don't emit a move for the CR spill slot if we haven't 1056243830Sdim // spilled CRs. 1057261991Sdim if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4) 1058296417Sdim && !MustSaveCR) 1059261991Sdim continue; 1060243830Sdim 1061243830Sdim // For 64-bit SVR4 when we have spilled CRs, the spill location 1062243830Sdim // is SP+8, not a frame-relative slot. 1063261991Sdim if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 1064276479Sdim // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for 1065276479Sdim // the whole CR word. In the ELFv2 ABI, every CR that was 1066276479Sdim // actually saved gets its own CFI record. 1067276479Sdim unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2; 1068276479Sdim unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 1069276479Sdim nullptr, MRI->getDwarfRegNum(CRReg, true), 8)); 1070276479Sdim BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1071276479Sdim .addCFIIndex(CFIIndex); 1072261991Sdim continue; 1073243830Sdim } 1074243830Sdim 1075243830Sdim int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 1076276479Sdim unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 1077276479Sdim nullptr, MRI->getDwarfRegNum(Reg, true), Offset)); 1078276479Sdim BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1079276479Sdim .addCFIIndex(CFIIndex); 1080218885Sdim } 1081218885Sdim } 1082218885Sdim} 1083218885Sdim 1084218885Sdimvoid PPCFrameLowering::emitEpilogue(MachineFunction &MF, 1085296417Sdim MachineBasicBlock &MBB) const { 1086296417Sdim MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(); 1087296417Sdim DebugLoc dl; 1088296417Sdim 1089296417Sdim if (MBBI != MBB.end()) 1090296417Sdim dl = MBBI->getDebugLoc(); 1091296417Sdim 1092218885Sdim const PPCInstrInfo &TII = 1093288943Sdim *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 1094261991Sdim const PPCRegisterInfo *RegInfo = 1095288943Sdim static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 1096218885Sdim 1097261991Sdim // Get alignment info so we know how to restore the SP. 1098218885Sdim const MachineFrameInfo *MFI = MF.getFrameInfo(); 1099218885Sdim 1100218885Sdim // Get the number of bytes allocated from the FrameInfo. 1101218885Sdim int FrameSize = MFI->getStackSize(); 1102218885Sdim 1103218885Sdim // Get processor type. 1104218885Sdim bool isPPC64 = Subtarget.isPPC64(); 1105261991Sdim // Get the ABI. 1106261991Sdim bool isSVR4ABI = Subtarget.isSVR4ABI(); 1107261991Sdim 1108218885Sdim // Check if the link register (LR) has been saved. 1109218885Sdim PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1110218885Sdim bool MustSaveLR = FI->mustSaveLR(); 1111261991Sdim const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs(); 1112296417Sdim bool MustSaveCR = !MustSaveCRs.empty(); 1113261991Sdim // Do we have a frame pointer and/or base pointer for this function? 1114218885Sdim bool HasFP = hasFP(MF); 1115261991Sdim bool HasBP = RegInfo->hasBasePointer(MF); 1116218885Sdim 1117261991Sdim unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1; 1118270147Srdivacky unsigned BPReg = RegInfo->getBaseRegister(MF); 1119261991Sdim unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 1120296417Sdim unsigned ScratchReg = 0; 1121261991Sdim unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg 1122261991Sdim const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8 1123261991Sdim : PPC::MTLR ); 1124261991Sdim const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD 1125261991Sdim : PPC::LWZ ); 1126261991Sdim const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8 1127261991Sdim : PPC::LIS ); 1128261991Sdim const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8 1129261991Sdim : PPC::ORI ); 1130261991Sdim const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8 1131261991Sdim : PPC::ADDI ); 1132261991Sdim const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8 1133261991Sdim : PPC::ADD4 ); 1134261991Sdim 1135288943Sdim int LROffset = getReturnSaveOffset(); 1136218885Sdim 1137218885Sdim int FPOffset = 0; 1138296417Sdim 1139296417Sdim // Using the same bool variable as below to supress compiler warnings. 1140296417Sdim bool SingleScratchReg = findScratchRegister(&MBB, true, false, &ScratchReg, 1141296417Sdim &TempReg); 1142296417Sdim assert(SingleScratchReg && 1143296417Sdim "Could not find an available scratch register"); 1144296417Sdim 1145296417Sdim SingleScratchReg = ScratchReg == TempReg; 1146296417Sdim 1147218885Sdim if (HasFP) { 1148261991Sdim if (isSVR4ABI) { 1149218885Sdim MachineFrameInfo *FFI = MF.getFrameInfo(); 1150218885Sdim int FPIndex = FI->getFramePointerSaveIndex(); 1151218885Sdim assert(FPIndex && "No Frame Pointer Save Slot!"); 1152218885Sdim FPOffset = FFI->getObjectOffset(FPIndex); 1153218885Sdim } else { 1154288943Sdim FPOffset = getFramePointerSaveOffset(); 1155218885Sdim } 1156218885Sdim } 1157218885Sdim 1158261991Sdim int BPOffset = 0; 1159261991Sdim if (HasBP) { 1160261991Sdim if (isSVR4ABI) { 1161261991Sdim MachineFrameInfo *FFI = MF.getFrameInfo(); 1162261991Sdim int BPIndex = FI->getBasePointerSaveIndex(); 1163261991Sdim assert(BPIndex && "No Base Pointer Save Slot!"); 1164261991Sdim BPOffset = FFI->getObjectOffset(BPIndex); 1165261991Sdim } else { 1166288943Sdim BPOffset = getBasePointerSaveOffset(); 1167261991Sdim } 1168261991Sdim } 1169261991Sdim 1170280031Sdim int PBPOffset = 0; 1171280031Sdim if (FI->usesPICBase()) { 1172280031Sdim MachineFrameInfo *FFI = MF.getFrameInfo(); 1173280031Sdim int PBPIndex = FI->getPICBasePointerSaveIndex(); 1174280031Sdim assert(PBPIndex && "No PIC Base Pointer Save Slot!"); 1175280031Sdim PBPOffset = FFI->getObjectOffset(PBPIndex); 1176280031Sdim } 1177280031Sdim 1178296417Sdim bool IsReturnBlock = (MBBI != MBB.end() && MBBI->isReturn()); 1179296417Sdim 1180296417Sdim if (IsReturnBlock) { 1181296417Sdim unsigned RetOpcode = MBBI->getOpcode(); 1182296417Sdim bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 1183296417Sdim RetOpcode == PPC::TCRETURNdi || 1184296417Sdim RetOpcode == PPC::TCRETURNai || 1185296417Sdim RetOpcode == PPC::TCRETURNri8 || 1186296417Sdim RetOpcode == PPC::TCRETURNdi8 || 1187296417Sdim RetOpcode == PPC::TCRETURNai8; 1188218885Sdim 1189296417Sdim if (UsesTCRet) { 1190296417Sdim int MaxTCRetDelta = FI->getTailCallSPDelta(); 1191296417Sdim MachineOperand &StackAdjust = MBBI->getOperand(1); 1192296417Sdim assert(StackAdjust.isImm() && "Expecting immediate value."); 1193296417Sdim // Adjust stack pointer. 1194296417Sdim int StackAdj = StackAdjust.getImm(); 1195296417Sdim int Delta = StackAdj - MaxTCRetDelta; 1196296417Sdim assert((Delta >= 0) && "Delta must be positive"); 1197296417Sdim if (MaxTCRetDelta>0) 1198296417Sdim FrameSize += (StackAdj +Delta); 1199296417Sdim else 1200296417Sdim FrameSize += StackAdj; 1201296417Sdim } 1202218885Sdim } 1203218885Sdim 1204261991Sdim // Frames of 32KB & larger require special handling because they cannot be 1205261991Sdim // indexed into with a simple LD/LWZ immediate offset operand. 1206261991Sdim bool isLargeFrame = !isInt<16>(FrameSize); 1207261991Sdim 1208218885Sdim if (FrameSize) { 1209261991Sdim // In the prologue, the loaded (or persistent) stack pointer value is offset 1210261991Sdim // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now. 1211261991Sdim 1212261991Sdim // If this function contained a fastcc call and GuaranteedTailCallOpt is 1213261991Sdim // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 1214261991Sdim // call which invalidates the stack pointer value in SP(0). So we use the 1215261991Sdim // value of R31 in this case. 1216261991Sdim if (FI->hasFastCall()) { 1217261991Sdim assert(HasFP && "Expecting a valid frame pointer."); 1218261991Sdim if (!isLargeFrame) { 1219261991Sdim BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 1220261991Sdim .addReg(FPReg).addImm(FrameSize); 1221261991Sdim } else { 1222261991Sdim BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 1223218885Sdim .addImm(FrameSize >> 16); 1224261991Sdim BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 1225261991Sdim .addReg(ScratchReg, RegState::Kill) 1226218885Sdim .addImm(FrameSize & 0xFFFF); 1227261991Sdim BuildMI(MBB, MBBI, dl, AddInst) 1228261991Sdim .addReg(SPReg) 1229261991Sdim .addReg(FPReg) 1230261991Sdim .addReg(ScratchReg); 1231218885Sdim } 1232261991Sdim } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) { 1233261991Sdim BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 1234261991Sdim .addReg(SPReg) 1235261991Sdim .addImm(FrameSize); 1236218885Sdim } else { 1237261991Sdim BuildMI(MBB, MBBI, dl, LoadInst, SPReg) 1238261991Sdim .addImm(0) 1239261991Sdim .addReg(SPReg); 1240218885Sdim } 1241296417Sdim } 1242261991Sdim 1243296417Sdim assert((isPPC64 || !MustSaveCR) && 1244296417Sdim "Epilogue CR restoring supported only in 64-bit mode"); 1245296417Sdim 1246296417Sdim // If we need to save both the LR and the CR and we only have one available 1247296417Sdim // scratch register, we must do them one at a time. 1248296417Sdim if (MustSaveCR && SingleScratchReg && MustSaveLR) { 1249296417Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg) 1250296417Sdim .addImm(8) 1251296417Sdim .addReg(SPReg); 1252296417Sdim for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 1253296417Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i]) 1254296417Sdim .addReg(TempReg, getKillRegState(i == e-1)); 1255218885Sdim } 1256218885Sdim 1257261991Sdim if (MustSaveLR) 1258261991Sdim BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg) 1259261991Sdim .addImm(LROffset) 1260261991Sdim .addReg(SPReg); 1261218885Sdim 1262296417Sdim if (MustSaveCR && 1263296417Sdim !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 1264261991Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg) 1265261991Sdim .addImm(8) 1266261991Sdim .addReg(SPReg); 1267218885Sdim 1268261991Sdim if (HasFP) 1269261991Sdim BuildMI(MBB, MBBI, dl, LoadInst, FPReg) 1270261991Sdim .addImm(FPOffset) 1271261991Sdim .addReg(SPReg); 1272251662Sdim 1273280031Sdim if (FI->usesPICBase()) 1274280031Sdim // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 1275280031Sdim BuildMI(MBB, MBBI, dl, LoadInst) 1276280031Sdim .addReg(PPC::R30) 1277280031Sdim .addImm(PBPOffset) 1278280031Sdim .addReg(SPReg); 1279280031Sdim 1280261991Sdim if (HasBP) 1281261991Sdim BuildMI(MBB, MBBI, dl, LoadInst, BPReg) 1282261991Sdim .addImm(BPOffset) 1283261991Sdim .addReg(SPReg); 1284218885Sdim 1285296417Sdim if (MustSaveCR && 1286296417Sdim !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 1287261991Sdim for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 1288261991Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i]) 1289261991Sdim .addReg(TempReg, getKillRegState(i == e-1)); 1290251662Sdim 1291261991Sdim if (MustSaveLR) 1292261991Sdim BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg); 1293218885Sdim 1294218885Sdim // Callee pop calling convention. Pop parameter/linkage area. Used for tail 1295218885Sdim // call optimization 1296296417Sdim if (IsReturnBlock) { 1297296417Sdim unsigned RetOpcode = MBBI->getOpcode(); 1298296417Sdim if (MF.getTarget().Options.GuaranteedTailCallOpt && 1299296417Sdim (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) && 1300296417Sdim MF.getFunction()->getCallingConv() == CallingConv::Fast) { 1301296417Sdim PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1302296417Sdim unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 1303218885Sdim 1304296417Sdim if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 1305296417Sdim BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 1306296417Sdim .addReg(SPReg).addImm(CallerAllocatedAmt); 1307296417Sdim } else { 1308296417Sdim BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 1309218885Sdim .addImm(CallerAllocatedAmt >> 16); 1310296417Sdim BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 1311261991Sdim .addReg(ScratchReg, RegState::Kill) 1312218885Sdim .addImm(CallerAllocatedAmt & 0xFFFF); 1313296417Sdim BuildMI(MBB, MBBI, dl, AddInst) 1314261991Sdim .addReg(SPReg) 1315218885Sdim .addReg(FPReg) 1316261991Sdim .addReg(ScratchReg); 1317296417Sdim } 1318296417Sdim } else if (RetOpcode == PPC::TCRETURNdi) { 1319296417Sdim MBBI = MBB.getLastNonDebugInstr(); 1320296417Sdim MachineOperand &JumpTarget = MBBI->getOperand(0); 1321296417Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 1322296417Sdim addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1323296417Sdim } else if (RetOpcode == PPC::TCRETURNri) { 1324296417Sdim MBBI = MBB.getLastNonDebugInstr(); 1325296417Sdim assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1326296417Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 1327296417Sdim } else if (RetOpcode == PPC::TCRETURNai) { 1328296417Sdim MBBI = MBB.getLastNonDebugInstr(); 1329296417Sdim MachineOperand &JumpTarget = MBBI->getOperand(0); 1330296417Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 1331296417Sdim } else if (RetOpcode == PPC::TCRETURNdi8) { 1332296417Sdim MBBI = MBB.getLastNonDebugInstr(); 1333296417Sdim MachineOperand &JumpTarget = MBBI->getOperand(0); 1334296417Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 1335296417Sdim addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1336296417Sdim } else if (RetOpcode == PPC::TCRETURNri8) { 1337296417Sdim MBBI = MBB.getLastNonDebugInstr(); 1338296417Sdim assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1339296417Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 1340296417Sdim } else if (RetOpcode == PPC::TCRETURNai8) { 1341296417Sdim MBBI = MBB.getLastNonDebugInstr(); 1342296417Sdim MachineOperand &JumpTarget = MBBI->getOperand(0); 1343296417Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 1344296417Sdim } 1345218885Sdim } 1346218885Sdim} 1347218885Sdim 1348288943Sdimvoid PPCFrameLowering::determineCalleeSaves(MachineFunction &MF, 1349288943Sdim BitVector &SavedRegs, 1350288943Sdim RegScavenger *RS) const { 1351288943Sdim TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); 1352218885Sdim 1353261991Sdim const PPCRegisterInfo *RegInfo = 1354288943Sdim static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 1355218885Sdim 1356218885Sdim // Save and clear the LR state. 1357218885Sdim PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1358218885Sdim unsigned LR = RegInfo->getRARegister(); 1359218885Sdim FI->setMustSaveLR(MustSaveLR(MF, LR)); 1360288943Sdim SavedRegs.reset(LR); 1361218885Sdim 1362218885Sdim // Save R31 if necessary 1363218885Sdim int FPSI = FI->getFramePointerSaveIndex(); 1364218885Sdim bool isPPC64 = Subtarget.isPPC64(); 1365218885Sdim bool isDarwinABI = Subtarget.isDarwinABI(); 1366218885Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 1367218885Sdim 1368218885Sdim // If the frame pointer save index hasn't been defined yet. 1369218885Sdim if (!FPSI && needsFP(MF)) { 1370218885Sdim // Find out what the fix offset of the frame pointer save area. 1371288943Sdim int FPOffset = getFramePointerSaveOffset(); 1372218885Sdim // Allocate the frame index for frame pointer save area. 1373218885Sdim FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 1374218885Sdim // Save the result. 1375218885Sdim FI->setFramePointerSaveIndex(FPSI); 1376218885Sdim } 1377218885Sdim 1378261991Sdim int BPSI = FI->getBasePointerSaveIndex(); 1379261991Sdim if (!BPSI && RegInfo->hasBasePointer(MF)) { 1380288943Sdim int BPOffset = getBasePointerSaveOffset(); 1381261991Sdim // Allocate the frame index for the base pointer save area. 1382261991Sdim BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true); 1383261991Sdim // Save the result. 1384261991Sdim FI->setBasePointerSaveIndex(BPSI); 1385261991Sdim } 1386261991Sdim 1387280031Sdim // Reserve stack space for the PIC Base register (R30). 1388280031Sdim // Only used in SVR4 32-bit. 1389280031Sdim if (FI->usesPICBase()) { 1390296417Sdim int PBPSI = MFI->CreateFixedObject(4, -8, true); 1391280031Sdim FI->setPICBasePointerSaveIndex(PBPSI); 1392280031Sdim } 1393280031Sdim 1394218885Sdim // Reserve stack space to move the linkage area to in case of a tail call. 1395218885Sdim int TCSPDelta = 0; 1396234353Sdim if (MF.getTarget().Options.GuaranteedTailCallOpt && 1397234353Sdim (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 1398218885Sdim MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 1399218885Sdim } 1400218885Sdim 1401276479Sdim // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the 1402249423Sdim // function uses CR 2, 3, or 4. 1403276479Sdim if (!isPPC64 && !isDarwinABI && 1404288943Sdim (SavedRegs.test(PPC::CR2) || 1405288943Sdim SavedRegs.test(PPC::CR3) || 1406288943Sdim SavedRegs.test(PPC::CR4))) { 1407249423Sdim int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true); 1408249423Sdim FI->setCRSpillFrameIndex(FrameIdx); 1409249423Sdim } 1410218885Sdim} 1411218885Sdim 1412249423Sdimvoid PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, 1413249423Sdim RegScavenger *RS) const { 1414218885Sdim // Early exit if not using the SVR4 ABI. 1415249423Sdim if (!Subtarget.isSVR4ABI()) { 1416249423Sdim addScavengingSpillSlot(MF, RS); 1417218885Sdim return; 1418249423Sdim } 1419218885Sdim 1420218885Sdim // Get callee saved register information. 1421218885Sdim MachineFrameInfo *FFI = MF.getFrameInfo(); 1422218885Sdim const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 1423218885Sdim 1424218885Sdim // Early exit if no callee saved registers are modified! 1425218885Sdim if (CSI.empty() && !needsFP(MF)) { 1426249423Sdim addScavengingSpillSlot(MF, RS); 1427218885Sdim return; 1428218885Sdim } 1429218885Sdim 1430218885Sdim unsigned MinGPR = PPC::R31; 1431218885Sdim unsigned MinG8R = PPC::X31; 1432218885Sdim unsigned MinFPR = PPC::F31; 1433218885Sdim unsigned MinVR = PPC::V31; 1434218885Sdim 1435218885Sdim bool HasGPSaveArea = false; 1436218885Sdim bool HasG8SaveArea = false; 1437218885Sdim bool HasFPSaveArea = false; 1438218885Sdim bool HasVRSAVESaveArea = false; 1439218885Sdim bool HasVRSaveArea = false; 1440218885Sdim 1441218885Sdim SmallVector<CalleeSavedInfo, 18> GPRegs; 1442218885Sdim SmallVector<CalleeSavedInfo, 18> G8Regs; 1443218885Sdim SmallVector<CalleeSavedInfo, 18> FPRegs; 1444218885Sdim SmallVector<CalleeSavedInfo, 18> VRegs; 1445218885Sdim 1446218885Sdim for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1447218885Sdim unsigned Reg = CSI[i].getReg(); 1448239462Sdim if (PPC::GPRCRegClass.contains(Reg)) { 1449218885Sdim HasGPSaveArea = true; 1450218885Sdim 1451218885Sdim GPRegs.push_back(CSI[i]); 1452218885Sdim 1453218885Sdim if (Reg < MinGPR) { 1454218885Sdim MinGPR = Reg; 1455218885Sdim } 1456239462Sdim } else if (PPC::G8RCRegClass.contains(Reg)) { 1457218885Sdim HasG8SaveArea = true; 1458218885Sdim 1459218885Sdim G8Regs.push_back(CSI[i]); 1460218885Sdim 1461218885Sdim if (Reg < MinG8R) { 1462218885Sdim MinG8R = Reg; 1463218885Sdim } 1464239462Sdim } else if (PPC::F8RCRegClass.contains(Reg)) { 1465218885Sdim HasFPSaveArea = true; 1466218885Sdim 1467218885Sdim FPRegs.push_back(CSI[i]); 1468218885Sdim 1469218885Sdim if (Reg < MinFPR) { 1470218885Sdim MinFPR = Reg; 1471218885Sdim } 1472239462Sdim } else if (PPC::CRBITRCRegClass.contains(Reg) || 1473239462Sdim PPC::CRRCRegClass.contains(Reg)) { 1474243830Sdim ; // do nothing, as we already know whether CRs are spilled 1475239462Sdim } else if (PPC::VRSAVERCRegClass.contains(Reg)) { 1476218885Sdim HasVRSAVESaveArea = true; 1477239462Sdim } else if (PPC::VRRCRegClass.contains(Reg)) { 1478218885Sdim HasVRSaveArea = true; 1479218885Sdim 1480218885Sdim VRegs.push_back(CSI[i]); 1481218885Sdim 1482218885Sdim if (Reg < MinVR) { 1483218885Sdim MinVR = Reg; 1484218885Sdim } 1485218885Sdim } else { 1486218885Sdim llvm_unreachable("Unknown RegisterClass!"); 1487218885Sdim } 1488218885Sdim } 1489218885Sdim 1490218885Sdim PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 1491288943Sdim const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 1492218885Sdim 1493218885Sdim int64_t LowerBound = 0; 1494218885Sdim 1495218885Sdim // Take into account stack space reserved for tail calls. 1496218885Sdim int TCSPDelta = 0; 1497234353Sdim if (MF.getTarget().Options.GuaranteedTailCallOpt && 1498234353Sdim (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 1499218885Sdim LowerBound = TCSPDelta; 1500218885Sdim } 1501218885Sdim 1502218885Sdim // The Floating-point register save area is right below the back chain word 1503218885Sdim // of the previous stack frame. 1504218885Sdim if (HasFPSaveArea) { 1505218885Sdim for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 1506218885Sdim int FI = FPRegs[i].getFrameIdx(); 1507218885Sdim 1508218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1509218885Sdim } 1510218885Sdim 1511249423Sdim LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8; 1512218885Sdim } 1513218885Sdim 1514218885Sdim // Check whether the frame pointer register is allocated. If so, make sure it 1515218885Sdim // is spilled to the correct offset. 1516218885Sdim if (needsFP(MF)) { 1517218885Sdim HasGPSaveArea = true; 1518218885Sdim 1519218885Sdim int FI = PFI->getFramePointerSaveIndex(); 1520218885Sdim assert(FI && "No Frame Pointer Save Slot!"); 1521218885Sdim 1522218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1523218885Sdim } 1524218885Sdim 1525280031Sdim if (PFI->usesPICBase()) { 1526280031Sdim HasGPSaveArea = true; 1527280031Sdim 1528280031Sdim int FI = PFI->getPICBasePointerSaveIndex(); 1529280031Sdim assert(FI && "No PIC Base Pointer Save Slot!"); 1530280031Sdim 1531280031Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1532280031Sdim } 1533280031Sdim 1534261991Sdim const PPCRegisterInfo *RegInfo = 1535288943Sdim static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 1536261991Sdim if (RegInfo->hasBasePointer(MF)) { 1537261991Sdim HasGPSaveArea = true; 1538261991Sdim 1539261991Sdim int FI = PFI->getBasePointerSaveIndex(); 1540261991Sdim assert(FI && "No Base Pointer Save Slot!"); 1541261991Sdim 1542261991Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1543261991Sdim } 1544261991Sdim 1545218885Sdim // General register save area starts right below the Floating-point 1546218885Sdim // register save area. 1547218885Sdim if (HasGPSaveArea || HasG8SaveArea) { 1548218885Sdim // Move general register save area spill slots down, taking into account 1549218885Sdim // the size of the Floating-point register save area. 1550218885Sdim for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 1551218885Sdim int FI = GPRegs[i].getFrameIdx(); 1552218885Sdim 1553218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1554218885Sdim } 1555218885Sdim 1556218885Sdim // Move general register save area spill slots down, taking into account 1557218885Sdim // the size of the Floating-point register save area. 1558218885Sdim for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 1559218885Sdim int FI = G8Regs[i].getFrameIdx(); 1560218885Sdim 1561218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1562218885Sdim } 1563218885Sdim 1564218885Sdim unsigned MinReg = 1565249423Sdim std::min<unsigned>(TRI->getEncodingValue(MinGPR), 1566249423Sdim TRI->getEncodingValue(MinG8R)); 1567218885Sdim 1568218885Sdim if (Subtarget.isPPC64()) { 1569218885Sdim LowerBound -= (31 - MinReg + 1) * 8; 1570218885Sdim } else { 1571218885Sdim LowerBound -= (31 - MinReg + 1) * 4; 1572218885Sdim } 1573218885Sdim } 1574218885Sdim 1575243830Sdim // For 32-bit only, the CR save area is below the general register 1576243830Sdim // save area. For 64-bit SVR4, the CR save area is addressed relative 1577243830Sdim // to the stack pointer and hence does not need an adjustment here. 1578243830Sdim // Only CR2 (the first nonvolatile spilled) has an associated frame 1579243830Sdim // index so that we have a single uniform save area. 1580243830Sdim if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) { 1581218885Sdim // Adjust the frame index of the CR spill slot. 1582218885Sdim for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1583218885Sdim unsigned Reg = CSI[i].getReg(); 1584218885Sdim 1585243830Sdim if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2) 1586276479Sdim // Leave Darwin logic as-is. 1587276479Sdim || (!Subtarget.isSVR4ABI() && 1588276479Sdim (PPC::CRBITRCRegClass.contains(Reg) || 1589276479Sdim PPC::CRRCRegClass.contains(Reg)))) { 1590218885Sdim int FI = CSI[i].getFrameIdx(); 1591218885Sdim 1592218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1593218885Sdim } 1594218885Sdim } 1595218885Sdim 1596218885Sdim LowerBound -= 4; // The CR save area is always 4 bytes long. 1597218885Sdim } 1598218885Sdim 1599218885Sdim if (HasVRSAVESaveArea) { 1600218885Sdim // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1601218885Sdim // which have the VRSAVE register class? 1602218885Sdim // Adjust the frame index of the VRSAVE spill slot. 1603218885Sdim for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1604218885Sdim unsigned Reg = CSI[i].getReg(); 1605218885Sdim 1606239462Sdim if (PPC::VRSAVERCRegClass.contains(Reg)) { 1607218885Sdim int FI = CSI[i].getFrameIdx(); 1608218885Sdim 1609218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1610218885Sdim } 1611218885Sdim } 1612218885Sdim 1613218885Sdim LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 1614218885Sdim } 1615218885Sdim 1616218885Sdim if (HasVRSaveArea) { 1617218885Sdim // Insert alignment padding, we need 16-byte alignment. 1618218885Sdim LowerBound = (LowerBound - 15) & ~(15); 1619218885Sdim 1620218885Sdim for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 1621218885Sdim int FI = VRegs[i].getFrameIdx(); 1622218885Sdim 1623218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1624218885Sdim } 1625218885Sdim } 1626249423Sdim 1627249423Sdim addScavengingSpillSlot(MF, RS); 1628218885Sdim} 1629243830Sdim 1630249423Sdimvoid 1631249423SdimPPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF, 1632249423Sdim RegScavenger *RS) const { 1633249423Sdim // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 1634249423Sdim // a large stack, which will require scavenging a register to materialize a 1635249423Sdim // large offset. 1636249423Sdim 1637249423Sdim // We need to have a scavenger spill slot for spills if the frame size is 1638249423Sdim // large. In case there is no free register for large-offset addressing, 1639249423Sdim // this slot is used for the necessary emergency spill. Also, we need the 1640249423Sdim // slot for dynamic stack allocations. 1641249423Sdim 1642249423Sdim // The scavenger might be invoked if the frame offset does not fit into 1643249423Sdim // the 16-bit immediate. We don't know the complete frame size here 1644249423Sdim // because we've not yet computed callee-saved register spills or the 1645249423Sdim // needed alignment padding. 1646249423Sdim unsigned StackSize = determineFrameLayout(MF, false, true); 1647249423Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 1648249423Sdim if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) || 1649249423Sdim hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) { 1650249423Sdim const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 1651249423Sdim const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 1652249423Sdim const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 1653249423Sdim RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1654249423Sdim RC->getAlignment(), 1655249423Sdim false)); 1656249423Sdim 1657261991Sdim // Might we have over-aligned allocas? 1658261991Sdim bool HasAlVars = MFI->hasVarSizedObjects() && 1659261991Sdim MFI->getMaxAlignment() > getStackAlignment(); 1660261991Sdim 1661249423Sdim // These kinds of spills might need two registers. 1662261991Sdim if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars) 1663249423Sdim RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1664249423Sdim RC->getAlignment(), 1665249423Sdim false)); 1666249423Sdim 1667249423Sdim } 1668249423Sdim} 1669249423Sdim 1670276479Sdimbool 1671243830SdimPPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1672276479Sdim MachineBasicBlock::iterator MI, 1673276479Sdim const std::vector<CalleeSavedInfo> &CSI, 1674276479Sdim const TargetRegisterInfo *TRI) const { 1675243830Sdim 1676243830Sdim // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1677243830Sdim // Return false otherwise to maintain pre-existing behavior. 1678243830Sdim if (!Subtarget.isSVR4ABI()) 1679243830Sdim return false; 1680243830Sdim 1681243830Sdim MachineFunction *MF = MBB.getParent(); 1682243830Sdim const PPCInstrInfo &TII = 1683288943Sdim *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 1684243830Sdim DebugLoc DL; 1685243830Sdim bool CRSpilled = false; 1686251662Sdim MachineInstrBuilder CRMIB; 1687276479Sdim 1688243830Sdim for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1689243830Sdim unsigned Reg = CSI[i].getReg(); 1690261991Sdim // Only Darwin actually uses the VRSAVE register, but it can still appear 1691261991Sdim // here if, for example, @llvm.eh.unwind.init() is used. If we're not on 1692261991Sdim // Darwin, ignore it. 1693261991Sdim if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI()) 1694261991Sdim continue; 1695261991Sdim 1696243830Sdim // CR2 through CR4 are the nonvolatile CR fields. 1697243830Sdim bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; 1698243830Sdim 1699243830Sdim // Add the callee-saved register as live-in; it's killed at the spill. 1700243830Sdim MBB.addLiveIn(Reg); 1701243830Sdim 1702251662Sdim if (CRSpilled && IsCRField) { 1703251662Sdim CRMIB.addReg(Reg, RegState::ImplicitKill); 1704251662Sdim continue; 1705251662Sdim } 1706251662Sdim 1707243830Sdim // Insert the spill to the stack frame. 1708243830Sdim if (IsCRField) { 1709251662Sdim PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>(); 1710243830Sdim if (Subtarget.isPPC64()) { 1711251662Sdim // The actual spill will happen at the start of the prologue. 1712251662Sdim FuncInfo->addMustSaveCR(Reg); 1713243830Sdim } else { 1714251662Sdim CRSpilled = true; 1715251662Sdim FuncInfo->setSpillsCR(); 1716251662Sdim 1717276479Sdim // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have 1718276479Sdim // the same frame index in PPCRegisterInfo::hasReservedSpillSlot. 1719276479Sdim CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12) 1720251662Sdim .addReg(Reg, RegState::ImplicitKill); 1721251662Sdim 1722276479Sdim MBB.insert(MI, CRMIB); 1723276479Sdim MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW)) 1724276479Sdim .addReg(PPC::R12, 1725276479Sdim getKillRegState(true)), 1726276479Sdim CSI[i].getFrameIdx())); 1727243830Sdim } 1728243830Sdim } else { 1729243830Sdim const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1730243830Sdim TII.storeRegToStackSlot(MBB, MI, Reg, true, 1731276479Sdim CSI[i].getFrameIdx(), RC, TRI); 1732243830Sdim } 1733243830Sdim } 1734243830Sdim return true; 1735243830Sdim} 1736243830Sdim 1737243830Sdimstatic void 1738251662SdimrestoreCRs(bool isPPC64, bool is31, 1739251662Sdim bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, 1740276479Sdim MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 1741276479Sdim const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) { 1742243830Sdim 1743243830Sdim MachineFunction *MF = MBB.getParent(); 1744288943Sdim const PPCInstrInfo &TII = *MF->getSubtarget<PPCSubtarget>().getInstrInfo(); 1745243830Sdim DebugLoc DL; 1746243830Sdim unsigned RestoreOp, MoveReg; 1747243830Sdim 1748251662Sdim if (isPPC64) 1749251662Sdim // This is handled during epilogue generation. 1750251662Sdim return; 1751251662Sdim else { 1752243830Sdim // 32-bit: FP-relative 1753243830Sdim MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), 1754276479Sdim PPC::R12), 1755276479Sdim CSI[CSIIndex].getFrameIdx())); 1756261991Sdim RestoreOp = PPC::MTOCRF; 1757243830Sdim MoveReg = PPC::R12; 1758243830Sdim } 1759276479Sdim 1760243830Sdim if (CR2Spilled) 1761243830Sdim MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2) 1762249423Sdim .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled))); 1763243830Sdim 1764243830Sdim if (CR3Spilled) 1765243830Sdim MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3) 1766249423Sdim .addReg(MoveReg, getKillRegState(!CR4Spilled))); 1767243830Sdim 1768243830Sdim if (CR4Spilled) 1769243830Sdim MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4) 1770249423Sdim .addReg(MoveReg, getKillRegState(true))); 1771243830Sdim} 1772243830Sdim 1773249423Sdimvoid PPCFrameLowering:: 1774249423SdimeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1775249423Sdim MachineBasicBlock::iterator I) const { 1776288943Sdim const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1777249423Sdim if (MF.getTarget().Options.GuaranteedTailCallOpt && 1778249423Sdim I->getOpcode() == PPC::ADJCALLSTACKUP) { 1779249423Sdim // Add (actually subtract) back the amount the callee popped on return. 1780249423Sdim if (int CalleeAmt = I->getOperand(1).getImm()) { 1781249423Sdim bool is64Bit = Subtarget.isPPC64(); 1782249423Sdim CalleeAmt *= -1; 1783249423Sdim unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 1784249423Sdim unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 1785249423Sdim unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 1786249423Sdim unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 1787249423Sdim unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 1788249423Sdim unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 1789249423Sdim MachineInstr *MI = I; 1790249423Sdim DebugLoc dl = MI->getDebugLoc(); 1791249423Sdim 1792249423Sdim if (isInt<16>(CalleeAmt)) { 1793249423Sdim BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) 1794249423Sdim .addReg(StackReg, RegState::Kill) 1795249423Sdim .addImm(CalleeAmt); 1796249423Sdim } else { 1797249423Sdim MachineBasicBlock::iterator MBBI = I; 1798249423Sdim BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 1799249423Sdim .addImm(CalleeAmt >> 16); 1800249423Sdim BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 1801249423Sdim .addReg(TmpReg, RegState::Kill) 1802249423Sdim .addImm(CalleeAmt & 0xFFFF); 1803249423Sdim BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg) 1804249423Sdim .addReg(StackReg, RegState::Kill) 1805249423Sdim .addReg(TmpReg); 1806249423Sdim } 1807249423Sdim } 1808249423Sdim } 1809249423Sdim // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 1810249423Sdim MBB.erase(I); 1811249423Sdim} 1812249423Sdim 1813276479Sdimbool 1814243830SdimPPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1815276479Sdim MachineBasicBlock::iterator MI, 1816276479Sdim const std::vector<CalleeSavedInfo> &CSI, 1817276479Sdim const TargetRegisterInfo *TRI) const { 1818243830Sdim 1819243830Sdim // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1820243830Sdim // Return false otherwise to maintain pre-existing behavior. 1821243830Sdim if (!Subtarget.isSVR4ABI()) 1822243830Sdim return false; 1823243830Sdim 1824243830Sdim MachineFunction *MF = MBB.getParent(); 1825243830Sdim const PPCInstrInfo &TII = 1826288943Sdim *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 1827243830Sdim bool CR2Spilled = false; 1828243830Sdim bool CR3Spilled = false; 1829243830Sdim bool CR4Spilled = false; 1830243830Sdim unsigned CSIIndex = 0; 1831243830Sdim 1832243830Sdim // Initialize insertion-point logic; we will be restoring in reverse 1833243830Sdim // order of spill. 1834243830Sdim MachineBasicBlock::iterator I = MI, BeforeI = I; 1835243830Sdim bool AtStart = I == MBB.begin(); 1836243830Sdim 1837243830Sdim if (!AtStart) 1838243830Sdim --BeforeI; 1839243830Sdim 1840243830Sdim for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1841243830Sdim unsigned Reg = CSI[i].getReg(); 1842243830Sdim 1843261991Sdim // Only Darwin actually uses the VRSAVE register, but it can still appear 1844261991Sdim // here if, for example, @llvm.eh.unwind.init() is used. If we're not on 1845261991Sdim // Darwin, ignore it. 1846261991Sdim if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI()) 1847261991Sdim continue; 1848261991Sdim 1849243830Sdim if (Reg == PPC::CR2) { 1850243830Sdim CR2Spilled = true; 1851243830Sdim // The spill slot is associated only with CR2, which is the 1852243830Sdim // first nonvolatile spilled. Save it here. 1853243830Sdim CSIIndex = i; 1854243830Sdim continue; 1855243830Sdim } else if (Reg == PPC::CR3) { 1856243830Sdim CR3Spilled = true; 1857243830Sdim continue; 1858243830Sdim } else if (Reg == PPC::CR4) { 1859243830Sdim CR4Spilled = true; 1860243830Sdim continue; 1861243830Sdim } else { 1862243830Sdim // When we first encounter a non-CR register after seeing at 1863243830Sdim // least one CR register, restore all spilled CRs together. 1864243830Sdim if ((CR2Spilled || CR3Spilled || CR4Spilled) 1865276479Sdim && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 1866251662Sdim bool is31 = needsFP(*MF); 1867251662Sdim restoreCRs(Subtarget.isPPC64(), is31, 1868251662Sdim CR2Spilled, CR3Spilled, CR4Spilled, 1869276479Sdim MBB, I, CSI, CSIIndex); 1870276479Sdim CR2Spilled = CR3Spilled = CR4Spilled = false; 1871243830Sdim } 1872243830Sdim 1873243830Sdim // Default behavior for non-CR saves. 1874243830Sdim const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1875243830Sdim TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(), 1876276479Sdim RC, TRI); 1877243830Sdim assert(I != MBB.begin() && 1878276479Sdim "loadRegFromStackSlot didn't insert any code!"); 1879243830Sdim } 1880243830Sdim 1881243830Sdim // Insert in reverse order. 1882243830Sdim if (AtStart) 1883243830Sdim I = MBB.begin(); 1884243830Sdim else { 1885243830Sdim I = BeforeI; 1886243830Sdim ++I; 1887276479Sdim } 1888243830Sdim } 1889243830Sdim 1890243830Sdim // If we haven't yet spilled the CRs, do so now. 1891251662Sdim if (CR2Spilled || CR3Spilled || CR4Spilled) { 1892276479Sdim bool is31 = needsFP(*MF); 1893251662Sdim restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled, 1894276479Sdim MBB, I, CSI, CSIIndex); 1895251662Sdim } 1896243830Sdim 1897243830Sdim return true; 1898243830Sdim} 1899296417Sdim 1900296417Sdimbool PPCFrameLowering::enableShrinkWrapping(const MachineFunction &MF) const { 1901296417Sdim return (MF.getSubtarget<PPCSubtarget>().isSVR4ABI() && 1902296417Sdim MF.getSubtarget<PPCSubtarget>().isPPC64()); 1903296417Sdim} 1904