Searched refs:BaseReg (Results 1 - 25 of 50) sorted by relevance

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/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.h77 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
79 void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
82 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
H A DAArch64StorePairSuppress.cpp143 unsigned BaseReg; local
145 if (TII->getMemOpBaseRegImmOfs(&MI, BaseReg, Offset, TRI)) {
146 if (PrevBaseReg == BaseReg) {
155 PrevBaseReg = BaseReg;
H A DAArch64RegisterInfo.cpp306 unsigned BaseReg,
314 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
317 unsigned BaseReg,
329 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
332 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
338 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, argument
350 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
305 isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const argument
316 materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const argument
H A DAArch64LoadStoreOptimizer.cpp133 unsigned BaseReg, int Offset);
1014 unsigned BaseReg = getLdStBaseOp(FirstMI).getReg(); local
1035 // it's unnecessary to check if BaseReg is modified by the store itself.
1037 BaseReg == getLdStBaseOp(MI).getReg() &&
1052 if (ModifiedRegs[BaseReg])
1076 unsigned BaseReg = getLdStBaseOp(FirstMI).getReg(); local
1086 if (FirstMI->modifiesRegister(BaseReg, TRI))
1142 if (BaseReg == MIBaseReg && ((Offset == MIOffset + OffsetStride) ||
1228 if (ModifiedRegs[BaseReg])
1301 unsigned BaseReg, in
1299 isMatchingUpdateInsn(MachineInstr *MemMI, MachineInstr *MI, unsigned BaseReg, int Offset) argument
1359 unsigned BaseReg = getLdStBaseOp(MemMI).getReg(); local
1415 unsigned BaseReg = getLdStBaseOp(MemMI).getReg(); local
[all...]
H A DAArch64InstrInfo.h93 bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
97 bool getMemOpBaseRegImmOfsWidth(MachineInstr *LdSt, unsigned &BaseReg,
/freebsd-11.0-release/contrib/llvm/lib/CodeGen/
H A DLocalStackSlotAllocation.cpp255 lookupCandidateBaseReg(unsigned BaseReg, argument
264 return TRI->isFrameOffsetLegal(MI, BaseReg, Offset);
330 unsigned BaseReg = 0; local
366 if (UsedBaseReg && lookupCandidateBaseReg(BaseReg, BaseOffset,
369 DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n");
387 BaseReg, BaseOffset, FrameSizeAdjust,
396 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
398 DEBUG(dbgs() << " Materializing base register " << BaseReg <<
404 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx,
415 assert(BaseReg !
[all...]
H A DImplicitNullChecks.cpp327 unsigned BaseReg, Offset; local
328 if (TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI))
329 if (MI->mayLoad() && !MI->isPredicable() && BaseReg == PointerReg &&
H A DCodeGenPrepare.cpp2027 Value *BaseReg; member in struct:__anon2445::ExtAddrMode
2029 ExtAddrMode() : BaseReg(nullptr), ScaledReg(nullptr) {}
2034 return (BaseReg == O.BaseReg) && (ScaledReg == O.ScaledReg) &&
2063 if (BaseReg) {
2066 BaseReg->printAsOperand(OS, /*PrintType=*/false);
3234 AddrMode.BaseReg = AddrInst->getOperand(0);
3247 AddrMode.BaseReg = AddrInst->getOperand(0);
3381 AddrMode.BaseReg = Addr;
3386 AddrMode.BaseReg
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp127 unsigned DestReg, unsigned BaseReg,
134 (BaseReg != 0 && !isARMLowRegister(BaseReg));
146 assert(BaseReg == ARM::SP && "Unexpected!");
170 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
172 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
183 unsigned DestReg, unsigned BaseReg,
203 // DestReg and BaseReg are low, high or the stack pointer.
204 // * CopyOpc - DestReg = BaseReg + imm
205 // This will be emitted once if DestReg != BaseReg, an
124 emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags = MachineInstr::NoFlags) argument
180 emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags) argument
[all...]
H A DARMBaseRegisterInfo.h151 unsigned BaseReg, int FrameIdx,
153 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
155 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
H A DThumbRegisterInfo.h52 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
H A DThumb2InstrInfo.cpp218 unsigned DestReg, unsigned BaseReg, int NumBytes,
221 if (NumBytes == 0 && DestReg != BaseReg) {
223 .addReg(BaseReg, RegState::Kill)
233 if (DestReg != ARM::SP && DestReg != BaseReg &&
255 .addReg(BaseReg)
261 // know anything about BaseReg. t2ADDrr is an invalid
264 // do not generate invalid encoding, put BaseReg first.
266 .addReg(BaseReg)
278 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
281 .addReg(BaseReg)
216 emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
[all...]
H A DARMBaseInstrInfo.h74 /// \p [out] BaseReg and \p [out] InsertedReg contain
77 /// - BaseReg: vreg0:sub0
86 RegSubRegPair &BaseReg,
470 unsigned DestReg, unsigned BaseReg, int NumBytes,
476 unsigned DestReg, unsigned BaseReg, int NumBytes,
481 unsigned DestReg, unsigned BaseReg,
H A DARMLoadStoreOptimizer.cpp1494 unsigned BaseReg, bool BaseKill, bool BaseUndef,
1502 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1508 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1521 unsigned BaseReg = BaseOp.getReg();
1529 bool Errata602117 = EvenReg == BaseReg &&
1562 .addReg(BaseReg, getKillRegState(BaseKill))
1569 .addReg(BaseReg, getKillRegState(BaseKill))
1592 (TRI->regsOverlap(EvenReg, BaseReg))) {
1593 assert(!TRI->regsOverlap(OddReg, BaseReg));
1596 BaseReg, fals
[all...]
H A DARMBaseRegisterInfo.cpp577 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
581 unsigned BaseReg, int FrameIdx,
596 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
598 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
605 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, argument
624 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
627 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
633 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, argument
677 NumBits = (BaseReg == ARM::SP ? 8 : 5);
580 materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const argument
H A DThumb2SizeReduction.cpp421 unsigned BaseReg = MI->getOperand(0).getReg(); local
422 assert(isARMLowRegister(BaseReg));
428 if (MI->getOperand(i).getReg() == BaseReg) {
450 unsigned BaseReg = MI->getOperand(1).getReg(); local
451 if (BaseReg != ARM::SP)
463 unsigned BaseReg = MI->getOperand(1).getReg(); local
464 if (BaseReg == ARM::SP &&
469 } else if (!isARMLowRegister(BaseReg) ||
/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.h127 unsigned BaseReg, int FrameIdx,
129 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
131 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
/freebsd-11.0-release/contrib/llvm/lib/Target/X86/InstPrinter/
H A DX86ATTInstPrinter.cpp190 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); local
205 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
212 if (IndexReg.getReg() || BaseReg.getReg()) {
214 if (BaseReg.getReg())
H A DX86IntelInstPrinter.cpp159 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); local
174 if (BaseReg.getReg()) {
193 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
/freebsd-11.0-release/contrib/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp265 unsigned BaseReg, IndexReg, TmpReg, Scale; member in class:__anon3052::X86AsmParser::IntelExprStateMachine
275 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
279 unsigned getBaseReg() { return BaseReg; }
383 // If we already have a BaseReg, then assume this is the IndexReg with
385 if (!BaseReg) {
386 BaseReg = TmpReg;
388 assert (!IndexReg && "BaseReg/IndexReg already set!");
420 // If we already have a BaseReg, then assume this is the IndexReg with
422 if (!BaseReg) {
423 BaseReg
832 CheckBaseRegAndIndexReg(unsigned BaseReg, unsigned IndexReg, StringRef &ErrMsg) argument
1066 CreateMemForInlineAsm( unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier, InlineAsmIdentifierInfo &Info) argument
1343 int BaseReg = SM.getBaseReg(); local
1958 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; local
[all...]
H A DX86Operand.h55 unsigned BaseReg; member in struct:llvm::X86Operand::MemOp
117 return Mem.BaseReg;
502 Res->Mem.BaseReg = 0;
516 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
521 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
529 Res->Mem.BaseReg = BaseReg;
515 CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc, SMLoc EndLoc, unsigned Size = 0, StringRef SymName = StringRef(), void *OpDecl = nullptr) argument
/freebsd-11.0-release/contrib/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); local
64 if (is16BitMode(STI) && BaseReg.getReg() == 0 &&
67 if ((BaseReg.getReg() != 0 &&
68 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
226 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
229 if ((BaseReg.getReg() != 0 &&
230 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
241 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
244 if ((BaseReg.getReg() != 0 &&
245 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg
372 unsigned BaseReg = Base.getReg(); local
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Target/X86/
H A DX86AsmPrinter.cpp245 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); local
250 bool HasBaseReg = BaseReg.getReg() != 0;
252 BaseReg.getReg() == X86::RIP)
310 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); local
325 if (BaseReg.getReg()) {
343 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp122 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); local
123 emitMask(BaseReg, LoadStoreStackMaskReg, STI);
/freebsd-11.0-release/contrib/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h819 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
822 unsigned BaseReg, int FrameIdx,
830 virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
837 virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,

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