1283625Sdim//===- ThumbRegisterInfo.h - Thumb Register Information Impl -*- C++ -*-===// 2283625Sdim// 3283625Sdim// The LLVM Compiler Infrastructure 4283625Sdim// 5283625Sdim// This file is distributed under the University of Illinois Open Source 6283625Sdim// License. See LICENSE.TXT for details. 7283625Sdim// 8283625Sdim//===----------------------------------------------------------------------===// 9283625Sdim// 10283625Sdim// This file contains the Thumb implementation of the TargetRegisterInfo 11283625Sdim// class. With the exception of emitLoadConstPool Thumb2 tracks 12283625Sdim// ARMBaseRegisterInfo, Thumb1 overloads the functions below. 13283625Sdim// 14283625Sdim//===----------------------------------------------------------------------===// 15283625Sdim 16283625Sdim#ifndef LLVM_LIB_TARGET_ARM_THUMB1REGISTERINFO_H 17283625Sdim#define LLVM_LIB_TARGET_ARM_THUMB1REGISTERINFO_H 18283625Sdim 19283625Sdim#include "ARMBaseRegisterInfo.h" 20283625Sdim#include "llvm/Target/TargetRegisterInfo.h" 21283625Sdim 22283625Sdimnamespace llvm { 23283625Sdim class ARMSubtarget; 24283625Sdim class ARMBaseInstrInfo; 25283625Sdim 26283625Sdimstruct ThumbRegisterInfo : public ARMBaseRegisterInfo { 27283625Sdimpublic: 28283625Sdim ThumbRegisterInfo(); 29283625Sdim 30283625Sdim const TargetRegisterClass * 31283625Sdim getLargestLegalSuperClass(const TargetRegisterClass *RC, 32283625Sdim const MachineFunction &MF) const override; 33283625Sdim 34283625Sdim const TargetRegisterClass * 35283625Sdim getPointerRegClass(const MachineFunction &MF, 36283625Sdim unsigned Kind = 0) const override; 37283625Sdim 38283625Sdim /// emitLoadConstPool - Emits a load from constpool to materialize the 39283625Sdim /// specified immediate. 40283625Sdim void 41283625Sdim emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 42283625Sdim DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, 43283625Sdim ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0, 44283625Sdim unsigned MIFlags = MachineInstr::NoFlags) const override; 45283625Sdim 46283625Sdim // rewrite MI to access 'Offset' bytes from the FP. Update Offset to be 47283625Sdim // however much remains to be handled. Return 'true' if no further 48283625Sdim // work is required. 49283625Sdim bool rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx, 50283625Sdim unsigned FrameReg, int &Offset, 51283625Sdim const ARMBaseInstrInfo &TII) const; 52283625Sdim void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 53283625Sdim int64_t Offset) const override; 54283625Sdim bool saveScavengerRegister(MachineBasicBlock &MBB, 55283625Sdim MachineBasicBlock::iterator I, 56283625Sdim MachineBasicBlock::iterator &UseMI, 57283625Sdim const TargetRegisterClass *RC, 58283625Sdim unsigned Reg) const override; 59283625Sdim void eliminateFrameIndex(MachineBasicBlock::iterator II, 60283625Sdim int SPAdj, unsigned FIOperandNum, 61283625Sdim RegScavenger *RS = nullptr) const override; 62283625Sdim}; 63285181Sdim} 64283625Sdim 65283625Sdim#endif 66