1//===- ThumbRegisterInfo.h - Thumb Register Information Impl -*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Thumb implementation of the TargetRegisterInfo
11// class. With the exception of emitLoadConstPool Thumb2 tracks
12// ARMBaseRegisterInfo, Thumb1 overloads the functions below.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_LIB_TARGET_ARM_THUMB1REGISTERINFO_H
17#define LLVM_LIB_TARGET_ARM_THUMB1REGISTERINFO_H
18
19#include "ARMBaseRegisterInfo.h"
20#include "llvm/Target/TargetRegisterInfo.h"
21
22namespace llvm {
23  class ARMSubtarget;
24  class ARMBaseInstrInfo;
25
26struct ThumbRegisterInfo : public ARMBaseRegisterInfo {
27public:
28  ThumbRegisterInfo();
29
30  const TargetRegisterClass *
31  getLargestLegalSuperClass(const TargetRegisterClass *RC,
32                            const MachineFunction &MF) const override;
33
34  const TargetRegisterClass *
35  getPointerRegClass(const MachineFunction &MF,
36                     unsigned Kind = 0) const override;
37
38  /// emitLoadConstPool - Emits a load from constpool to materialize the
39  /// specified immediate.
40  void
41  emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
42                    DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val,
43                    ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
44                    unsigned MIFlags = MachineInstr::NoFlags) const override;
45
46  // rewrite MI to access 'Offset' bytes from the FP. Update Offset to be
47  // however much remains to be handled. Return 'true' if no further
48  // work is required.
49  bool rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
50                         unsigned FrameReg, int &Offset,
51                         const ARMBaseInstrInfo &TII) const;
52  void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
53                         int64_t Offset) const override;
54  bool saveScavengerRegister(MachineBasicBlock &MBB,
55                             MachineBasicBlock::iterator I,
56                             MachineBasicBlock::iterator &UseMI,
57                             const TargetRegisterClass *RC,
58                             unsigned Reg) const override;
59  void eliminateFrameIndex(MachineBasicBlock::iterator II,
60                           int SPAdj, unsigned FIOperandNum,
61                           RegScavenger *RS = nullptr) const override;
62};
63}
64
65#endif
66