/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMFeatures.h | 1 //===-- ARMFeatures.h - Checks for ARM instruction features -----*- C++ -*-===// 10 // This file contains the code shared between ARM CodeGen and ARM MC 29 case ARM::tADC: 30 case ARM::tADDi3: 31 case ARM::tADDi8: 32 case ARM::tADDrr: 33 case ARM::tAND: 34 case ARM::tASRri: 35 case ARM [all...] |
H A D | ARMInstrInfo.cpp | 1 //===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===// 10 // This file contains the ARM implementation of the TargetInstrInfo class. 15 #include "ARM.h" 38 NopInst.setOpcode(ARM::HINT); 43 NopInst.setOpcode(ARM::MOVr); 44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); 45 NopInst.addOperand(MCOperand::createReg(ARM::R0)); 56 case ARM::LDR_PRE_IMM: 57 case ARM::LDR_PRE_REG: 58 case ARM [all...] |
H A D | ARMExpandPseudoInsts.cpp | 17 #include "ARM.h" 38 cl::desc("Verify machine code after expanding ARM pseudos")); 54 return "ARM pseudo instruction expansion pass"; 135 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true}, 136 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true}, 137 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true}, 138 { ARM [all...] |
H A D | Thumb2SizeReduction.cpp | 10 #include "ARM.h" 63 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 }, 64 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 }, 65 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 }, 66 { ARM [all...] |
H A D | ARMBaseInstrInfo.cpp | 1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===// 10 // This file contains the Base ARM implementation of the TargetInstrInfo class. 14 #include "ARM.h" 52 cl::desc("Enable ARM 2-addr to 3-addr conv")); 56 cl::desc("Widen ARM vmovs to vmovd when possible")); 75 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false }, 76 { ARM::VMLSS, ARM [all...] |
H A D | ARMCallingConv.h | 1 //=== ARMCallingConv.h - ARM Custom Calling Convention Routines -*- C++ -*-===// 10 // This file contains the custom routines for the ARM Calling Convention that 18 #include "ARM.h" 31 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; 74 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; 75 static const MCPhysReg LoRegList[] = { ARM [all...] |
H A D | Thumb2InstrInfo.cpp | 37 NopInst.setOpcode(ARM::tHINT); 79 if (MBBI->getOpcode() == ARM::t2IT) { 117 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) 120 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) 138 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass || 139 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass || 140 RC == &ARM::GPRnopcRegClass) { 141 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM [all...] |
H A D | ARMLoadStoreOptimizer.cpp | 1 //===-- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass ------------===// 15 #include "ARM.h" 67 #define ARM_LOAD_STORE_OPT_NAME "ARM load / store optimization pass" 165 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead()) 176 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD; 180 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 || 181 Opcode == ARM::t2STRi12 || Opcode == ARM [all...] |
H A D | ARMMCInstLower.cpp | 1 //===-- ARMMCInstLower.cpp - Convert ARM MachineInstr to an MCInst --------===// 10 // This file contains code to lower ARM MachineInstrs to their corresponding 15 #include "ARM.h" 74 if (MO.isImplicit() && MO.getReg() != ARM::CPSR) 126 case ARM::MOVi: 127 case ARM::MVNi: 128 case ARM::CMPri: 129 case ARM::CMNri: 130 case ARM::TSTri: 131 case ARM [all...] |
H A D | ARMAsmPrinter.cpp | 1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===// 11 // of machine-dependent LLVM code to GAS-format ARM assembly language. 16 #include "ARM.h" 162 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX) 186 if(ARM::GPRPairRegClass.contains(Reg)) { 189 Reg = TRI->getSubReg(Reg, ARM::gsub_0); 272 if (!ARM::DPRRegClass.contains(*SR)) 274 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg; 299 if (ARM::GPRPairRegClass.contains(RegBegin)) { 301 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM [all...] |
H A D | Thumb1InstrInfo.cpp | 29 NopInst.setOpcode(ARM::tMOVr); 30 NopInst.addOperand(MCOperand::createReg(ARM::R8)); 31 NopInst.addOperand(MCOperand::createReg(ARM::R8)); 48 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && 51 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg) 52 || !ARM::tGPRRegClass.contains(DestReg)) 53 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) 63 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tPUSH))) 65 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tPOP))) 75 assert((RC == &ARM [all...] |
H A D | ARMFrameLowering.cpp | 1 //===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===// 10 // This file contains the ARM implementation of TargetFrameLowering class. 37 cl::desc("Align ARM NEON spills in prolog and epilog")); 83 // stack frame. ARM (especially Thumb) has small immediate offset to 113 if ((MI->getOpcode() == ARM::LDR_POST_IMM || 114 MI->getOpcode() == ARM::LDR_POST_REG || 115 MI->getOpcode() == ARM::t2LDR_POST) && 117 MI->getOperand(1).getReg() == ARM::SP) 144 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM [all...] |
H A D | ARMISelDAGToDAG.cpp | 1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===// 10 // This file defines an instruction selector for the ARM target. 14 #include "ARM.h" 53 /// ARMDAGToDAGISel - ARM specific code to select ARM machine 80 return "ARM Instruction Selection"; 139 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32); 204 /// ARM. 242 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM. 424 /// least on current ARM implementation [all...] |
H A D | ThumbRegisterInfo.cpp | 49 if (ARM::tGPRRegClass.hasSubClassEq(RC)) 50 return &ARM::tGPRRegClass; 59 return &ARM::tGPRRegClass; 76 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci)) 95 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci)) 145 if (DestReg == ARM::SP) 146 assert(BaseReg == ARM::SP && "Unexpected!"); 148 LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass); 151 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)) 154 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Support/ |
H A D | TargetParser.cpp | 23 using namespace ARM; 30 // The entries must appear in the order listed in ARM::FPUKind for correct indexing 34 ARM::FPUKind ID; 35 ARM::FPUVersion FPUVersion; 36 ARM::NeonSupportLevel NeonSupport; 37 ARM::FPURestriction Restriction; 48 // and Arch ID, according to the Addenda to the ARM ABI, chapters 63 ARM::ArchKind ID; 118 ARM::ArchKind ArchID; 135 StringRef llvm::ARM [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMAsmBackend.cpp | 1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===// 51 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = { 95 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = { 163 bool HasThumb2 = STI->getFeatureBits()[ARM::FeatureThumb2]; 168 case ARM::tBcc: 169 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op; 170 case ARM::tLDRpci: 171 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op; 172 case ARM::tADR: 173 return HasThumb2 ? (unsigned)ARM [all...] |
H A D | ARMUnwindOpAsm.cpp | 1 //===-- ARMUnwindOpAsm.cpp - ARM Unwind Opcodes Assembler -------*- C++ -*-===// 10 // This file implements the unwind opcode assmebler for ARM exception handling 52 assert(PI < ARM::EHABI::NUM_PERSONALITY_INDEX && 54 EmitByte(ARM::EHABI::EHT_COMPACT | PI); 60 EmitByte(ARM::EHABI::UNWIND_OPCODE_FINISH); 84 EmitInt8(ARM::EHABI::UNWIND_OPCODE_POP_REG_RANGE_R4 | Range); 88 EmitInt8(ARM::EHABI::UNWIND_OPCODE_POP_REG_RANGE_R4_R14 | Range); 95 EmitInt16(ARM::EHABI::UNWIND_OPCODE_POP_REG_MASK_R4 | (RegSave >> 4)); 99 EmitInt16(ARM::EHABI::UNWIND_OPCODE_POP_REG_MASK | (RegSave & 0x000fu)); 114 ? ARM [all...] |
H A D | ARMWinCOFFObjectWriter.cpp | 1 //===-- ARMWinCOFFObjectWriter.cpp - ARM Windows COFF Object Writer -- C++ -==// 66 case ARM::fixup_t2_condbranch: 68 case ARM::fixup_t2_uncondbranch: 70 case ARM::fixup_arm_thumb_bl: 71 case ARM::fixup_arm_thumb_blx: 73 case ARM::fixup_t2_movw_lo16: 74 case ARM::fixup_t2_movt_hi16: 80 return static_cast<unsigned>(Fixup.getKind()) != ARM::fixup_t2_movt_hi16;
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H A D | ARMELFObjectWriter.cpp | 1 //===-- ARMELFObjectWriter.cpp - ARM ELF Writer ---------------------------===// 103 case ARM::fixup_arm_blx: 104 case ARM::fixup_arm_uncondbl: 117 case ARM::fixup_arm_condbl: 118 case ARM::fixup_arm_condbranch: 119 case ARM::fixup_arm_uncondbranch: 122 case ARM::fixup_t2_condbranch: 123 case ARM::fixup_t2_uncondbranch: 126 case ARM::fixup_arm_movt_hi16: 129 case ARM [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 87 /// ARM disassembler for all ARM platforms. 418 case ARM::HVC: { 438 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 439 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 460 // VFP and NEON instructions, similarly, are shared between ARM 575 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 577 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 582 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM [all...] |
/freebsd-11.0-release/lib/clang/libllvmarmasmparser/ |
H A D | Makefile | 7 SRCDIR= lib/Target/ARM/AsmParser 8 INCDIR= lib/Target/ARM
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/freebsd-11.0-release/lib/clang/libllvmarmasmprinter/ |
H A D | Makefile | 7 SRCDIR= lib/Target/ARM/InstPrinter 8 INCDIR= lib/Target/ARM
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/freebsd-11.0-release/lib/clang/libllvmarmdisassembler/ |
H A D | Makefile | 7 SRCDIR= lib/Target/ARM/Disassembler 8 INCDIR= lib/Target/ARM
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/freebsd-11.0-release/lib/clang/libllvmarminfo/ |
H A D | Makefile | 7 SRCDIR= lib/Target/ARM/TargetInfo 8 INCDIR= lib/Target/ARM
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/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 72 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} 127 FPReg = ARM::SP; 249 return getSTI().getFeatureBits()[ARM::ModeThumb]; 252 return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2]; 255 return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2]; 258 return getSTI().getFeatureBits()[ARM::HasV4TOps]; 261 return getSTI().getFeatureBits()[ARM::HasV6Ops]; 264 return getSTI().getFeatureBits()[ARM::HasV6MOps]; 267 return getSTI().getFeatureBits()[ARM [all...] |