Target/ARM/ARMFeatures.h

1 //===-- ARMFeatures.h - Checks for ARM instruction features -----*- C++ -*-===//
10 // This file contains the code shared between ARM CodeGen and ARM MC
29   case ARM::tADC:
30   case ARM::tADDi3:
31   case ARM::tADDi8:
32   case ARM::tADDrr:
33   case ARM::tAND:
34   case ARM::tASRri:
35   case ARM::tASRrr:
36   case ARM::tBIC:
37   case ARM::tEOR:
38   case ARM::tLSLri:
39   case ARM::tLSLrr:
40   case ARM::tLSRri:
41   case ARM::tLSRrr:
42   case ARM::tMOVi8:
43   case ARM::tMUL:
44   case ARM::tMVN:
45   case ARM::tORR:
46   case ARM::tROR:
47   case ARM::tRSB:
48   case ARM::tSBC:
49   case ARM::tSUBi3:
50   case ARM::tSUBi8:
51   case ARM::tSUBrr:
54   case ARM::tADDrSPi:
55   case ARM::tCMNz:
56   case ARM::tCMPi8:
57   case ARM::tCMPr:
58   case ARM::tLDRBi:
59   case ARM::tLDRBr:
60   case ARM::tLDRHi:
61   case ARM::tLDRHr:
62   case ARM::tLDRSB:
63   case ARM::tLDRSH:
64   case ARM::tLDRi:
65   case ARM::tLDRr:
66   case ARM::tLDRspi:
67   case ARM::tSTRBi:
68   case ARM::tSTRBr:
69   case ARM::tSTRHi:
70   case ARM::tSTRHr:
71   case ARM::tSTRi:
72   case ARM::tSTRr:
73   case ARM::tSTRspi:
74   case ARM::tTST:
77   case ARM::tADDspr:
78   case ARM::tBLXr:
79     return Instr->getOperand(2).getReg() != ARM::PC;
82   case ARM::tADDrSP:
83   case ARM::tBX:
84     return Instr->getOperand(0).getReg() != ARM::PC;
85   case ARM::tADDhirr:
86     return Instr->getOperand(0).getReg() != ARM::PC &&
87            Instr->getOperand(2).getReg() != ARM::PC;
88   case ARM::tCMPhir:
89   case ARM::tMOVr:
90     return Instr->getOperand(0).getReg() != ARM::PC &&
91            Instr->getOperand(1).getReg() != ARM::PC;