Target/ARM/ThumbRegisterInfo.cpp

49   if (ARM::tGPRRegClass.hasSubClassEq(RC))
50     return &ARM::tGPRRegClass;
59   return &ARM::tGPRRegClass;
76   BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
95   BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
145     if (DestReg == ARM::SP)
146       assert(BaseReg == ARM::SP && "Unexpected!");
148       LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
151       AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
154       AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
156       AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
163     int Opc = (isSub) ? ARM::tSUBrr : ((isHigh || !CanChangeCC) ? ARM::tADDhirr
164                                                                 : ARM::tADDrr);
167     if (Opc != ARM::tADDhirr)
169     if (DestReg == ARM::SP || isSub)
213   if (DestReg == ARM::SP) {
214     if (BaseReg == ARM::SP) {
219       CopyOpc = ARM::tMOVr;
222     ExtraOpc = isSub ? ARM::tSUBspi : ARM::tADDspi;
226     if (BaseReg == ARM::SP) {
229       CopyOpc = ARM::tADDrSPi;
237       CopyOpc = isSub ? ARM::tSUBi3 : ARM::tADDi3;
242       CopyOpc = ARM::tMOVr;
245     ExtraOpc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
254       CopyOpc = ARM::tMOVr;
268     CopyOpc = ARM::tMOVr;
291   unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
310     if (CopyOpc != ARM::tMOVr) {
342   case ARM::tLDRspi:
343     return ARM::tLDRi;
345   case ARM::tSTRspi:
346     return ARM::tSTRi;
366   if (Opcode == ARM::tADDframe) {
380     unsigned NumBits = (FrameReg == ARM::SP) ? 8 : 5;
399       if (NewOpc != Opcode && FrameReg != ARM::SP)
410     if (Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) {
431   int Off = Offset; // ARM doesn't need the general 64-bit offsets
461   AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))
462     .addReg(ARM::R12, RegState::Define)
475       if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) {
483       if (MO.getReg() == ARM::R12) {
491   AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVr)).
492     addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill));
514   unsigned FrameReg = ARM::SP;
535   if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
574     if (Opcode == ARM::tLDRspi) {
575       if (FrameReg == ARM::SP)
587     MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi));
595       VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
598       if (Opcode == ARM::tSTRspi) {
599         if (FrameReg == ARM::SP)
609       MI.setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi));