Lines Matching refs:ARM
1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
87 /// ARM disassembler for all ARM platforms.
418 case ARM::HVC: {
438 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
439 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
460 // VFP and NEON instructions, similarly, are shared between ARM
575 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
577 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
582 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
596 case ARM::tBcc:
597 case ARM::t2Bcc:
598 case ARM::tCBZ:
599 case ARM::tCBNZ:
600 case ARM::tCPS:
601 case ARM::t2CPS3p:
602 case ARM::t2CPS2p:
603 case ARM::t2CPS1p:
604 case ARM::tMOVSr:
605 case ARM::tSETEND:
613 case ARM::tB:
614 case ARM::t2B:
615 case ARM::t2TBB:
616 case ARM::t2TBH:
646 MI.insert(I, MCOperand::createReg(ARM::CPSR));
656 MI.insert(I, MCOperand::createReg(ARM::CPSR));
662 // encodings between ARM and Thumb modes, and they are predicable in ARM
682 I->setReg(ARM::CPSR);
695 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
696 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
730 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
738 if (MI.getOpcode() == ARM::t2IT) {
865 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
866 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
867 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
868 ARM::R12, ARM::SP, ARM::LR, ARM::PC
901 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
917 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
918 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
941 Register = ARM::R0;
944 Register = ARM::R1;
947 Register = ARM::R2;
950 Register = ARM::R3;
953 Register = ARM::R9;
956 Register = ARM::R12;
973 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
981 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
982 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
983 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
984 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
985 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
986 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
987 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
988 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1002 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1003 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1004 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1005 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1006 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1007 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1008 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1009 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1017 bool hasD16 = featureBits[ARM::FeatureD16];
1043 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1044 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1045 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1046 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1062 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1063 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1064 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1065 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1066 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1067 ARM::Q15
1081 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1082 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1083 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1084 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1085 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1086 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1087 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1088 ARM::D28_D30, ARM::D29_D31
1107 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1113 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1120 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1207 case ARM::LDMIA_UPD:
1208 case ARM::LDMDB_UPD:
1209 case ARM::LDMIB_UPD:
1210 case ARM::LDMDA_UPD:
1211 case ARM::t2LDMIA_UPD:
1212 case ARM::t2LDMDB_UPD:
1213 case ARM::t2STMIA_UPD:
1214 case ARM::t2STMDB_UPD:
1323 case ARM::LDC_OFFSET:
1324 case ARM::LDC_PRE:
1325 case ARM::LDC_POST:
1326 case ARM::LDC_OPTION:
1327 case ARM::LDCL_OFFSET:
1328 case ARM::LDCL_PRE:
1329 case ARM::LDCL_POST:
1330 case ARM::LDCL_OPTION:
1331 case ARM::STC_OFFSET:
1332 case ARM::STC_PRE:
1333 case ARM::STC_POST:
1334 case ARM::STC_OPTION:
1335 case ARM::STCL_OFFSET:
1336 case ARM::STCL_PRE:
1337 case ARM::STCL_POST:
1338 case ARM::STCL_OPTION:
1339 case ARM::t2LDC_OFFSET:
1340 case ARM::t2LDC_PRE:
1341 case ARM::t2LDC_POST:
1342 case ARM::t2LDC_OPTION:
1343 case ARM::t2LDCL_OFFSET:
1344 case ARM::t2LDCL_PRE:
1345 case ARM::t2LDCL_POST:
1346 case ARM::t2LDCL_OPTION:
1347 case ARM::t2STC_OFFSET:
1348 case ARM::t2STC_PRE:
1349 case ARM::t2STC_POST:
1350 case ARM::t2STC_OPTION:
1351 case ARM::t2STCL_OFFSET:
1352 case ARM::t2STCL_PRE:
1353 case ARM::t2STCL_POST:
1354 case ARM::t2STCL_OPTION:
1364 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1373 case ARM::t2LDC2_OFFSET:
1374 case ARM::t2LDC2L_OFFSET:
1375 case ARM::t2LDC2_PRE:
1376 case ARM::t2LDC2L_PRE:
1377 case ARM::t2STC2_OFFSET:
1378 case ARM::t2STC2L_OFFSET:
1379 case ARM::t2STC2_PRE:
1380 case ARM::t2STC2L_PRE:
1381 case ARM::LDC2_OFFSET:
1382 case ARM::LDC2L_OFFSET:
1383 case ARM::LDC2_PRE:
1384 case ARM::LDC2L_PRE:
1385 case ARM::STC2_OFFSET:
1386 case ARM::STC2L_OFFSET:
1387 case ARM::STC2_PRE:
1388 case ARM::STC2L_PRE:
1389 case ARM::t2LDC_OFFSET:
1390 case ARM::t2LDCL_OFFSET:
1391 case ARM::t2LDC_PRE:
1392 case ARM::t2LDCL_PRE:
1393 case ARM::t2STC_OFFSET:
1394 case ARM::t2STCL_OFFSET:
1395 case ARM::t2STC_PRE:
1396 case ARM::t2STCL_PRE:
1397 case ARM::LDC_OFFSET:
1398 case ARM::LDCL_OFFSET:
1399 case ARM::LDC_PRE:
1400 case ARM::LDCL_PRE:
1401 case ARM::STC_OFFSET:
1402 case ARM::STCL_OFFSET:
1403 case ARM::STC_PRE:
1404 case ARM::STCL_PRE:
1408 case ARM::t2LDC2_POST:
1409 case ARM::t2LDC2L_POST:
1410 case ARM::t2STC2_POST:
1411 case ARM::t2STC2L_POST:
1412 case ARM::LDC2_POST:
1413 case ARM::LDC2L_POST:
1414 case ARM::STC2_POST:
1415 case ARM::STC2L_POST:
1416 case ARM::t2LDC_POST:
1417 case ARM::t2LDCL_POST:
1418 case ARM::t2STC_POST:
1419 case ARM::t2STCL_POST:
1420 case ARM::LDC_POST:
1421 case ARM::LDCL_POST:
1422 case ARM::STC_POST:
1423 case ARM::STCL_POST:
1434 case ARM::LDC_OFFSET:
1435 case ARM::LDC_PRE:
1436 case ARM::LDC_POST:
1437 case ARM::LDC_OPTION:
1438 case ARM::LDCL_OFFSET:
1439 case ARM::LDCL_PRE:
1440 case ARM::LDCL_POST:
1441 case ARM::LDCL_OPTION:
1442 case ARM::STC_OFFSET:
1443 case ARM::STC_PRE:
1444 case ARM::STC_POST:
1445 case ARM::STC_OPTION:
1446 case ARM::STCL_OFFSET:
1447 case ARM::STCL_PRE:
1448 case ARM::STCL_POST:
1449 case ARM::STCL_OPTION:
1476 case ARM::STR_POST_IMM:
1477 case ARM::STR_POST_REG:
1478 case ARM::STRB_POST_IMM:
1479 case ARM::STRB_POST_REG:
1480 case ARM::STRT_POST_REG:
1481 case ARM::STRT_POST_IMM:
1482 case ARM::STRBT_POST_REG:
1483 case ARM::STRBT_POST_IMM:
1496 case ARM::LDR_POST_IMM:
1497 case ARM::LDR_POST_REG:
1498 case ARM::LDRB_POST_IMM:
1499 case ARM::LDRB_POST_REG:
1500 case ARM::LDRBT_POST_REG:
1501 case ARM::LDRBT_POST_IMM:
1502 case ARM::LDRT_POST_REG:
1503 case ARM::LDRT_POST_IMM:
1629 case ARM::STRD:
1630 case ARM::STRD_PRE:
1631 case ARM::STRD_POST:
1632 case ARM::LDRD:
1633 case ARM::LDRD_PRE:
1634 case ARM::LDRD_POST:
1641 case ARM::STRD:
1642 case ARM::STRD_PRE:
1643 case ARM::STRD_POST:
1656 case ARM::STRH:
1657 case ARM::STRH_PRE:
1658 case ARM::STRH_POST:
1666 case ARM::LDRD:
1667 case ARM::LDRD_PRE:
1668 case ARM::LDRD_POST:
1683 case ARM::LDRH:
1684 case ARM::LDRH_PRE:
1685 case ARM::LDRH_POST:
1698 case ARM::LDRSH:
1699 case ARM::LDRSH_PRE:
1700 case ARM::LDRSH_POST:
1701 case ARM::LDRSB:
1702 case ARM::LDRSB_PRE:
1703 case ARM::LDRSB_POST:
1728 case ARM::STRD:
1729 case ARM::STRD_PRE:
1730 case ARM::STRD_POST:
1731 case ARM::STRH:
1732 case ARM::STRH_PRE:
1733 case ARM::STRH_POST:
1745 case ARM::STRD:
1746 case ARM::STRD_PRE:
1747 case ARM::STRD_POST:
1748 case ARM::LDRD:
1749 case ARM::LDRD_PRE:
1750 case ARM::LDRD_POST:
1761 case ARM::LDRD:
1762 case ARM::LDRD_PRE:
1763 case ARM::LDRD_POST:
1764 case ARM::LDRH:
1765 case ARM::LDRH_PRE:
1766 case ARM::LDRH_POST:
1767 case ARM::LDRSH:
1768 case ARM::LDRSH_PRE:
1769 case ARM::LDRSH_POST:
1770 case ARM::LDRSB:
1771 case ARM::LDRSB_PRE:
1772 case ARM::LDRSB_POST:
1773 case ARM::LDRHTr:
1774 case ARM::LDRSBTr:
1865 case ARM::LDMDA:
1866 Inst.setOpcode(ARM::RFEDA);
1868 case ARM::LDMDA_UPD:
1869 Inst.setOpcode(ARM::RFEDA_UPD);
1871 case ARM::LDMDB:
1872 Inst.setOpcode(ARM::RFEDB);
1874 case ARM::LDMDB_UPD:
1875 Inst.setOpcode(ARM::RFEDB_UPD);
1877 case ARM::LDMIA:
1878 Inst.setOpcode(ARM::RFEIA);
1880 case ARM::LDMIA_UPD:
1881 Inst.setOpcode(ARM::RFEIA_UPD);
1883 case ARM::LDMIB:
1884 Inst.setOpcode(ARM::RFEIB);
1886 case ARM::LDMIB_UPD:
1887 Inst.setOpcode(ARM::RFEIB_UPD);
1889 case ARM::STMDA:
1890 Inst.setOpcode(ARM::SRSDA);
1892 case ARM::STMDA_UPD:
1893 Inst.setOpcode(ARM::SRSDA_UPD);
1895 case ARM::STMDB:
1896 Inst.setOpcode(ARM::SRSDB);
1898 case ARM::STMDB_UPD:
1899 Inst.setOpcode(ARM::SRSDB_UPD);
1901 case ARM::STMIA:
1902 Inst.setOpcode(ARM::SRSIA);
1904 case ARM::STMIA_UPD:
1905 Inst.setOpcode(ARM::SRSIA_UPD);
1907 case ARM::STMIB:
1908 Inst.setOpcode(ARM::SRSIB);
1910 case ARM::STMIB_UPD:
1911 Inst.setOpcode(ARM::SRSIB_UPD);
1968 Inst.setOpcode(ARM::CPS3p);
1973 Inst.setOpcode(ARM::CPS2p);
1978 Inst.setOpcode(ARM::CPS1p);
1983 Inst.setOpcode(ARM::CPS1p);
2008 Inst.setOpcode(ARM::t2CPS3p);
2013 Inst.setOpcode(ARM::t2CPS2p);
2018 Inst.setOpcode(ARM::t2CPS1p);
2026 Inst.setOpcode(ARM::t2HINT);
2045 if (Inst.getOpcode() == ARM::t2MOVTi16)
2068 if (Inst.getOpcode() == ARM::MOVTi16)
2142 if (!FeatureBits[ARM::HasV8_1aOps] ||
2143 !FeatureBits[ARM::HasV8Ops])
2155 Inst.setOpcode(ARM::SETPAN);
2241 Inst.setOpcode(ARM::BLXi);
2289 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2290 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2291 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2292 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2293 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2294 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2295 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2296 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2297 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2301 case ARM::VLD2b16:
2302 case ARM::VLD2b32:
2303 case ARM::VLD2b8:
2304 case ARM::VLD2b16wb_fixed:
2305 case ARM::VLD2b16wb_register:
2306 case ARM::VLD2b32wb_fixed:
2307 case ARM::VLD2b32wb_register:
2308 case ARM::VLD2b8wb_fixed:
2309 case ARM::VLD2b8wb_register:
2320 case ARM::VLD3d8:
2321 case ARM::VLD3d16:
2322 case ARM::VLD3d32:
2323 case ARM::VLD3d8_UPD:
2324 case ARM::VLD3d16_UPD:
2325 case ARM::VLD3d32_UPD:
2326 case ARM::VLD4d8:
2327 case ARM::VLD4d16:
2328 case ARM::VLD4d32:
2329 case ARM::VLD4d8_UPD:
2330 case ARM::VLD4d16_UPD:
2331 case ARM::VLD4d32_UPD:
2335 case ARM::VLD3q8:
2336 case ARM::VLD3q16:
2337 case ARM::VLD3q32:
2338 case ARM::VLD3q8_UPD:
2339 case ARM::VLD3q16_UPD:
2340 case ARM::VLD3q32_UPD:
2341 case ARM::VLD4q8:
2342 case ARM::VLD4q16:
2343 case ARM::VLD4q32:
2344 case ARM::VLD4q8_UPD:
2345 case ARM::VLD4q16_UPD:
2346 case ARM::VLD4q32_UPD:
2355 case ARM::VLD3d8:
2356 case ARM::VLD3d16:
2357 case ARM::VLD3d32:
2358 case ARM::VLD3d8_UPD:
2359 case ARM::VLD3d16_UPD:
2360 case ARM::VLD3d32_UPD:
2361 case ARM::VLD4d8:
2362 case ARM::VLD4d16:
2363 case ARM::VLD4d32:
2364 case ARM::VLD4d8_UPD:
2365 case ARM::VLD4d16_UPD:
2366 case ARM::VLD4d32_UPD:
2370 case ARM::VLD3q8:
2371 case ARM::VLD3q16:
2372 case ARM::VLD3q32:
2373 case ARM::VLD3q8_UPD:
2374 case ARM::VLD3q16_UPD:
2375 case ARM::VLD3q32_UPD:
2376 case ARM::VLD4q8:
2377 case ARM::VLD4q16:
2378 case ARM::VLD4q32:
2379 case ARM::VLD4q8_UPD:
2380 case ARM::VLD4q16_UPD:
2381 case ARM::VLD4q32_UPD:
2391 case ARM::VLD4d8:
2392 case ARM::VLD4d16:
2393 case ARM::VLD4d32:
2394 case ARM::VLD4d8_UPD:
2395 case ARM::VLD4d16_UPD:
2396 case ARM::VLD4d32_UPD:
2400 case ARM::VLD4q8:
2401 case ARM::VLD4q16:
2402 case ARM::VLD4q32:
2403 case ARM::VLD4q8_UPD:
2404 case ARM::VLD4q16_UPD:
2405 case ARM::VLD4q32_UPD:
2415 case ARM::VLD1d8wb_fixed:
2416 case ARM::VLD1d16wb_fixed:
2417 case ARM::VLD1d32wb_fixed:
2418 case ARM::VLD1d64wb_fixed:
2419 case ARM::VLD1d8wb_register:
2420 case ARM::VLD1d16wb_register:
2421 case ARM::VLD1d32wb_register:
2422 case ARM::VLD1d64wb_register:
2423 case ARM::VLD1q8wb_fixed:
2424 case ARM::VLD1q16wb_fixed:
2425 case ARM::VLD1q32wb_fixed:
2426 case ARM::VLD1q64wb_fixed:
2427 case ARM::VLD1q8wb_register:
2428 case ARM::VLD1q16wb_register:
2429 case ARM::VLD1q32wb_register:
2430 case ARM::VLD1q64wb_register:
2431 case ARM::VLD1d8Twb_fixed:
2432 case ARM::VLD1d8Twb_register:
2433 case ARM::VLD1d16Twb_fixed:
2434 case ARM::VLD1d16Twb_register:
2435 case ARM::VLD1d32Twb_fixed:
2436 case ARM::VLD1d32Twb_register:
2437 case ARM::VLD1d64Twb_fixed:
2438 case ARM::VLD1d64Twb_register:
2439 case ARM::VLD1d8Qwb_fixed:
2440 case ARM::VLD1d8Qwb_register:
2441 case ARM::VLD1d16Qwb_fixed:
2442 case ARM::VLD1d16Qwb_register:
2443 case ARM::VLD1d32Qwb_fixed:
2444 case ARM::VLD1d32Qwb_register:
2445 case ARM::VLD1d64Qwb_fixed:
2446 case ARM::VLD1d64Qwb_register:
2447 case ARM::VLD2d8wb_fixed:
2448 case ARM::VLD2d16wb_fixed:
2449 case ARM::VLD2d32wb_fixed:
2450 case ARM::VLD2q8wb_fixed:
2451 case ARM::VLD2q16wb_fixed:
2452 case ARM::VLD2q32wb_fixed:
2453 case ARM::VLD2d8wb_register:
2454 case ARM::VLD2d16wb_register:
2455 case ARM::VLD2d32wb_register:
2456 case ARM::VLD2q8wb_register:
2457 case ARM::VLD2q16wb_register:
2458 case ARM::VLD2q32wb_register:
2459 case ARM::VLD2b8wb_fixed:
2460 case ARM::VLD2b16wb_fixed:
2461 case ARM::VLD2b32wb_fixed:
2462 case ARM::VLD2b8wb_register:
2463 case ARM::VLD2b16wb_register:
2464 case ARM::VLD2b32wb_register:
2467 case ARM::VLD3d8_UPD:
2468 case ARM::VLD3d16_UPD:
2469 case ARM::VLD3d32_UPD:
2470 case ARM::VLD3q8_UPD:
2471 case ARM::VLD3q16_UPD:
2472 case ARM::VLD3q32_UPD:
2473 case ARM::VLD4d8_UPD:
2474 case ARM::VLD4d16_UPD:
2475 case ARM::VLD4d32_UPD:
2476 case ARM::VLD4q8_UPD:
2477 case ARM::VLD4q16_UPD:
2478 case ARM::VLD4q32_UPD:
2504 case ARM::VLD1d8wb_fixed:
2505 case ARM::VLD1d16wb_fixed:
2506 case ARM::VLD1d32wb_fixed:
2507 case ARM::VLD1d64wb_fixed:
2508 case ARM::VLD1d8Twb_fixed:
2509 case ARM::VLD1d16Twb_fixed:
2510 case ARM::VLD1d32Twb_fixed:
2511 case ARM::VLD1d64Twb_fixed:
2512 case ARM::VLD1d8Qwb_fixed:
2513 case ARM::VLD1d16Qwb_fixed:
2514 case ARM::VLD1d32Qwb_fixed:
2515 case ARM::VLD1d64Qwb_fixed:
2516 case ARM::VLD1d8wb_register:
2517 case ARM::VLD1d16wb_register:
2518 case ARM::VLD1d32wb_register:
2519 case ARM::VLD1d64wb_register:
2520 case ARM::VLD1q8wb_fixed:
2521 case ARM::VLD1q16wb_fixed:
2522 case ARM::VLD1q32wb_fixed:
2523 case ARM::VLD1q64wb_fixed:
2524 case ARM::VLD1q8wb_register:
2525 case ARM::VLD1q16wb_register:
2526 case ARM::VLD1q32wb_register:
2527 case ARM::VLD1q64wb_register:
2535 case ARM::VLD2d8wb_fixed:
2536 case ARM::VLD2d16wb_fixed:
2537 case ARM::VLD2d32wb_fixed:
2538 case ARM::VLD2b8wb_fixed:
2539 case ARM::VLD2b16wb_fixed:
2540 case ARM::VLD2b32wb_fixed:
2541 case ARM::VLD2q8wb_fixed:
2542 case ARM::VLD2q16wb_fixed:
2543 case ARM::VLD2q32wb_fixed:
2614 case ARM::VST1d8wb_fixed:
2615 case ARM::VST1d16wb_fixed:
2616 case ARM::VST1d32wb_fixed:
2617 case ARM::VST1d64wb_fixed:
2618 case ARM::VST1d8wb_register:
2619 case ARM::VST1d16wb_register:
2620 case ARM::VST1d32wb_register:
2621 case ARM::VST1d64wb_register:
2622 case ARM::VST1q8wb_fixed:
2623 case ARM::VST1q16wb_fixed:
2624 case ARM::VST1q32wb_fixed:
2625 case ARM::VST1q64wb_fixed:
2626 case ARM::VST1q8wb_register:
2627 case ARM::VST1q16wb_register:
2628 case ARM::VST1q32wb_register:
2629 case ARM::VST1q64wb_register:
2630 case ARM::VST1d8Twb_fixed:
2631 case ARM::VST1d16Twb_fixed:
2632 case ARM::VST1d32Twb_fixed:
2633 case ARM::VST1d64Twb_fixed:
2634 case ARM::VST1d8Twb_register:
2635 case ARM::VST1d16Twb_register:
2636 case ARM::VST1d32Twb_register:
2637 case ARM::VST1d64Twb_register:
2638 case ARM::VST1d8Qwb_fixed:
2639 case ARM::VST1d16Qwb_fixed:
2640 case ARM::VST1d32Qwb_fixed:
2641 case ARM::VST1d64Qwb_fixed:
2642 case ARM::VST1d8Qwb_register:
2643 case ARM::VST1d16Qwb_register:
2644 case ARM::VST1d32Qwb_register:
2645 case ARM::VST1d64Qwb_register:
2646 case ARM::VST2d8wb_fixed:
2647 case ARM::VST2d16wb_fixed:
2648 case ARM::VST2d32wb_fixed:
2649 case ARM::VST2d8wb_register:
2650 case ARM::VST2d16wb_register:
2651 case ARM::VST2d32wb_register:
2652 case ARM::VST2q8wb_fixed:
2653 case ARM::VST2q16wb_fixed:
2654 case ARM::VST2q32wb_fixed:
2655 case ARM::VST2q8wb_register:
2656 case ARM::VST2q16wb_register:
2657 case ARM::VST2q32wb_register:
2658 case ARM::VST2b8wb_fixed:
2659 case ARM::VST2b16wb_fixed:
2660 case ARM::VST2b32wb_fixed:
2661 case ARM::VST2b8wb_register:
2662 case ARM::VST2b16wb_register:
2663 case ARM::VST2b32wb_register:
2668 case ARM::VST3d8_UPD:
2669 case ARM::VST3d16_UPD:
2670 case ARM::VST3d32_UPD:
2671 case ARM::VST3q8_UPD:
2672 case ARM::VST3q16_UPD:
2673 case ARM::VST3q32_UPD:
2674 case ARM::VST4d8_UPD:
2675 case ARM::VST4d16_UPD:
2676 case ARM::VST4d32_UPD:
2677 case ARM::VST4q8_UPD:
2678 case ARM::VST4q16_UPD:
2679 case ARM::VST4q32_UPD:
2701 case ARM::VST1d8wb_fixed:
2702 case ARM::VST1d16wb_fixed:
2703 case ARM::VST1d32wb_fixed:
2704 case ARM::VST1d64wb_fixed:
2705 case ARM::VST1q8wb_fixed:
2706 case ARM::VST1q16wb_fixed:
2707 case ARM::VST1q32wb_fixed:
2708 case ARM::VST1q64wb_fixed:
2709 case ARM::VST1d8Twb_fixed:
2710 case ARM::VST1d16Twb_fixed:
2711 case ARM::VST1d32Twb_fixed:
2712 case ARM::VST1d64Twb_fixed:
2713 case ARM::VST1d8Qwb_fixed:
2714 case ARM::VST1d16Qwb_fixed:
2715 case ARM::VST1d32Qwb_fixed:
2716 case ARM::VST1d64Qwb_fixed:
2717 case ARM::VST2d8wb_fixed:
2718 case ARM::VST2d16wb_fixed:
2719 case ARM::VST2d32wb_fixed:
2720 case ARM::VST2q8wb_fixed:
2721 case ARM::VST2q16wb_fixed:
2722 case ARM::VST2q32wb_fixed:
2723 case ARM::VST2b8wb_fixed:
2724 case ARM::VST2b16wb_fixed:
2725 case ARM::VST2b32wb_fixed:
2732 case ARM::VST1q16:
2733 case ARM::VST1q32:
2734 case ARM::VST1q64:
2735 case ARM::VST1q8:
2736 case ARM::VST1q16wb_fixed:
2737 case ARM::VST1q16wb_register:
2738 case ARM::VST1q32wb_fixed:
2739 case ARM::VST1q32wb_register:
2740 case ARM::VST1q64wb_fixed:
2741 case ARM::VST1q64wb_register:
2742 case ARM::VST1q8wb_fixed:
2743 case ARM::VST1q8wb_register:
2744 case ARM::VST2d16:
2745 case ARM::VST2d32:
2746 case ARM::VST2d8:
2747 case ARM::VST2d16wb_fixed:
2748 case ARM::VST2d16wb_register:
2749 case ARM::VST2d32wb_fixed:
2750 case ARM::VST2d32wb_register:
2751 case ARM::VST2d8wb_fixed:
2752 case ARM::VST2d8wb_register:
2756 case ARM::VST2b16:
2757 case ARM::VST2b32:
2758 case ARM::VST2b8:
2759 case ARM::VST2b16wb_fixed:
2760 case ARM::VST2b16wb_register:
2761 case ARM::VST2b32wb_fixed:
2762 case ARM::VST2b32wb_register:
2763 case ARM::VST2b8wb_fixed:
2764 case ARM::VST2b8wb_register:
2775 case ARM::VST3d8:
2776 case ARM::VST3d16:
2777 case ARM::VST3d32:
2778 case ARM::VST3d8_UPD:
2779 case ARM::VST3d16_UPD:
2780 case ARM::VST3d32_UPD:
2781 case ARM::VST4d8:
2782 case ARM::VST4d16:
2783 case ARM::VST4d32:
2784 case ARM::VST4d8_UPD:
2785 case ARM::VST4d16_UPD:
2786 case ARM::VST4d32_UPD:
2790 case ARM::VST3q8:
2791 case ARM::VST3q16:
2792 case ARM::VST3q32:
2793 case ARM::VST3q8_UPD:
2794 case ARM::VST3q16_UPD:
2795 case ARM::VST3q32_UPD:
2796 case ARM::VST4q8:
2797 case ARM::VST4q16:
2798 case ARM::VST4q32:
2799 case ARM::VST4q8_UPD:
2800 case ARM::VST4q16_UPD:
2801 case ARM::VST4q32_UPD:
2811 case ARM::VST3d8:
2812 case ARM::VST3d16:
2813 case ARM::VST3d32:
2814 case ARM::VST3d8_UPD:
2815 case ARM::VST3d16_UPD:
2816 case ARM::VST3d32_UPD:
2817 case ARM::VST4d8:
2818 case ARM::VST4d16:
2819 case ARM::VST4d32:
2820 case ARM::VST4d8_UPD:
2821 case ARM::VST4d16_UPD:
2822 case ARM::VST4d32_UPD:
2826 case ARM::VST3q8:
2827 case ARM::VST3q16:
2828 case ARM::VST3q32:
2829 case ARM::VST3q8_UPD:
2830 case ARM::VST3q16_UPD:
2831 case ARM::VST3q32_UPD:
2832 case ARM::VST4q8:
2833 case ARM::VST4q16:
2834 case ARM::VST4q32:
2835 case ARM::VST4q8_UPD:
2836 case ARM::VST4q16_UPD:
2837 case ARM::VST4q32_UPD:
2847 case ARM::VST4d8:
2848 case ARM::VST4d16:
2849 case ARM::VST4d32:
2850 case ARM::VST4d8_UPD:
2851 case ARM::VST4d16_UPD:
2852 case ARM::VST4d32_UPD:
2856 case ARM::VST4q8:
2857 case ARM::VST4q16:
2858 case ARM::VST4q32:
2859 case ARM::VST4q8_UPD:
2860 case ARM::VST4q16_UPD:
2861 case ARM::VST4q32_UPD:
2888 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2889 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2890 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2891 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2932 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2933 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2934 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2935 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2939 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2940 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2941 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2942 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
3079 case ARM::VORRiv4i16:
3080 case ARM::VORRiv2i32:
3081 case ARM::VBICiv4i16:
3082 case ARM::VBICiv2i32:
3086 case ARM::VORRiv8i16:
3087 case ARM::VORRiv4i32:
3088 case ARM::VBICiv8i16:
3089 case ARM::VBICiv4i32:
3163 case ARM::VTBL2:
3164 case ARM::VTBX2:
3192 case ARM::tADR:
3194 case ARM::tADDrSPi:
3195 Inst.addOperand(MCOperand::createReg(ARM::SP));
3268 Inst.addOperand(MCOperand::createReg(ARM::SP));
3284 case ARM::t2STRHs:
3285 case ARM::t2STRBs:
3286 case ARM::t2STRs:
3312 bool hasMP = featureBits[ARM::FeatureMP];
3313 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3317 case ARM::t2LDRBs:
3318 Inst.setOpcode(ARM::t2LDRBpci);
3320 case ARM::t2LDRHs:
3321 Inst.setOpcode(ARM::t2LDRHpci);
3323 case ARM::t2LDRSHs:
3324 Inst.setOpcode(ARM::t2LDRSHpci);
3326 case ARM::t2LDRSBs:
3327 Inst.setOpcode(ARM::t2LDRSBpci);
3329 case ARM::t2LDRs:
3330 Inst.setOpcode(ARM::t2LDRpci);
3332 case ARM::t2PLDs:
3333 Inst.setOpcode(ARM::t2PLDpci);
3335 case ARM::t2PLIs:
3336 Inst.setOpcode(ARM::t2PLIpci);
3347 case ARM::t2LDRSHs:
3349 case ARM::t2LDRHs:
3350 Inst.setOpcode(ARM::t2PLDWs);
3352 case ARM::t2LDRSBs:
3353 Inst.setOpcode(ARM::t2PLIs);
3360 case ARM::t2PLDs:
3362 case ARM::t2PLIs:
3366 case ARM::t2PLDWs:
3399 bool hasMP = featureBits[ARM::FeatureMP];
3400 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3404 case ARM::t2LDRi8:
3405 Inst.setOpcode(ARM::t2LDRpci);
3407 case ARM::t2LDRBi8:
3408 Inst.setOpcode(ARM::t2LDRBpci);
3410 case ARM::t2LDRSBi8:
3411 Inst.setOpcode(ARM::t2LDRSBpci);
3413 case ARM::t2LDRHi8:
3414 Inst.setOpcode(ARM::t2LDRHpci);
3416 case ARM::t2LDRSHi8:
3417 Inst.setOpcode(ARM::t2LDRSHpci);
3419 case ARM::t2PLDi8:
3420 Inst.setOpcode(ARM::t2PLDpci);
3422 case ARM::t2PLIi8:
3423 Inst.setOpcode(ARM::t2PLIpci);
3433 case ARM::t2LDRSHi8:
3435 case ARM::t2LDRHi8:
3437 Inst.setOpcode(ARM::t2PLDWi8);
3439 case ARM::t2LDRSBi8:
3440 Inst.setOpcode(ARM::t2PLIi8);
3448 case ARM::t2PLDi8:
3450 case ARM::t2PLIi8:
3454 case ARM::t2PLDWi8:
3480 bool hasMP = featureBits[ARM::FeatureMP];
3481 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3485 case ARM::t2LDRi12:
3486 Inst.setOpcode(ARM::t2LDRpci);
3488 case ARM::t2LDRHi12:
3489 Inst.setOpcode(ARM::t2LDRHpci);
3491 case ARM::t2LDRSHi12:
3492 Inst.setOpcode(ARM::t2LDRSHpci);
3494 case ARM::t2LDRBi12:
3495 Inst.setOpcode(ARM::t2LDRBpci);
3497 case ARM::t2LDRSBi12:
3498 Inst.setOpcode(ARM::t2LDRSBpci);
3500 case ARM::t2PLDi12:
3501 Inst.setOpcode(ARM::t2PLDpci);
3503 case ARM::t2PLIi12:
3504 Inst.setOpcode(ARM::t2PLIpci);
3514 case ARM::t2LDRSHi12:
3516 case ARM::t2LDRHi12:
3517 Inst.setOpcode(ARM::t2PLDWi12);
3519 case ARM::t2LDRSBi12:
3520 Inst.setOpcode(ARM::t2PLIi12);
3528 case ARM::t2PLDi12:
3530 case ARM::t2PLIi12:
3534 case ARM::t2PLDWi12:
3559 case ARM::t2LDRT:
3560 Inst.setOpcode(ARM::t2LDRpci);
3562 case ARM::t2LDRBT:
3563 Inst.setOpcode(ARM::t2LDRBpci);
3565 case ARM::t2LDRHT:
3566 Inst.setOpcode(ARM::t2LDRHpci);
3568 case ARM::t2LDRSBT:
3569 Inst.setOpcode(ARM::t2LDRSBpci);
3571 case ARM::t2LDRSHT:
3572 Inst.setOpcode(ARM::t2LDRSHpci);
3598 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3602 case ARM::t2LDRBpci:
3603 case ARM::t2LDRHpci:
3604 Inst.setOpcode(ARM::t2PLDpci);
3606 case ARM::t2LDRSBpci:
3607 Inst.setOpcode(ARM::t2PLIpci);
3609 case ARM::t2LDRSHpci:
3617 case ARM::t2PLDpci:
3619 case ARM::t2PLIpci:
3706 case ARM::t2STRT:
3707 case ARM::t2STRBT:
3708 case ARM::t2STRHT:
3709 case ARM::t2STRi8:
3710 case ARM::t2STRHi8:
3711 case ARM::t2STRBi8:
3721 case ARM::t2LDRT:
3722 case ARM::t2LDRBT:
3723 case ARM::t2LDRHT:
3724 case ARM::t2LDRSBT:
3725 case ARM::t2LDRSHT:
3726 case ARM::t2STRT:
3727 case ARM::t2STRBT:
3728 case ARM::t2STRHT:
3756 case ARM::t2LDR_PRE:
3757 case ARM::t2LDR_POST:
3758 Inst.setOpcode(ARM::t2LDRpci);
3760 case ARM::t2LDRB_PRE:
3761 case ARM::t2LDRB_POST:
3762 Inst.setOpcode(ARM::t2LDRBpci);
3764 case ARM::t2LDRH_PRE:
3765 case ARM::t2LDRH_POST:
3766 Inst.setOpcode(ARM::t2LDRHpci);
3768 case ARM::t2LDRSB_PRE:
3769 case ARM::t2LDRSB_POST:
3771 Inst.setOpcode(ARM::t2PLIpci);
3773 Inst.setOpcode(ARM::t2LDRSBpci);
3775 case ARM::t2LDRSH_PRE:
3776 case ARM::t2LDRSH_POST:
3777 Inst.setOpcode(ARM::t2LDRSHpci);
3813 case ARM::t2STRi12:
3814 case ARM::t2STRBi12:
3815 case ARM::t2STRHi12:
3834 Inst.addOperand(MCOperand::createReg(ARM::SP));
3835 Inst.addOperand(MCOperand::createReg(ARM::SP));
3845 if (Inst.getOpcode() == ARM::tADDrSP) {
3851 Inst.addOperand(MCOperand::createReg(ARM::SP));
3854 } else if (Inst.getOpcode() == ARM::tADDspr) {
3857 Inst.addOperand(MCOperand::createReg(ARM::SP));
3858 Inst.addOperand(MCOperand::createReg(ARM::SP));
3922 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
3937 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3957 Inst.setOpcode(ARM::t2DSB);
3960 Inst.setOpcode(ARM::t2DMB);
3963 Inst.setOpcode(ARM::t2ISB);
4075 if (FeatureBits[ARM::FeatureMClass]) {
4095 if (!(FeatureBits[ARM::HasV7Ops]))
4103 if (Inst.getOpcode() == ARM::t2MSR_M) {
4105 if (!(FeatureBits[ARM::HasV7Ops])) {
4119 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4139 // ARM ARM. There are patterns, but nothing regular enough to make this logic
5055 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5071 Inst.setOpcode(ARM::VMOVv2f32);
5076 Inst.setOpcode(ARM::VMOVv1i64);
5078 Inst.setOpcode(ARM::VMOVv8i8);
5083 Inst.setOpcode(ARM::VMVNv2i32);
5085 Inst.setOpcode(ARM::VMOVv2i32);
5090 Inst.setOpcode(ARM::VMVNv2i32);
5092 Inst.setOpcode(ARM::VMOVv2i32);
5114 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5130 Inst.setOpcode(ARM::VMOVv4f32);
5135 Inst.setOpcode(ARM::VMOVv2i64);
5137 Inst.setOpcode(ARM::VMOVv16i8);
5142 Inst.setOpcode(ARM::VMVNv4i32);
5144 Inst.setOpcode(ARM::VMOVv4i32);
5149 Inst.setOpcode(ARM::VMVNv4i32);
5151 Inst.setOpcode(ARM::VMOVv4i32);