/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ResourcePriorityQueue.cpp | 95 && (TLI->getRegClassFor(VT)->getID() == RCId)) { 133 && (TLI->getRegClassFor(VT)->getID() == RCId)) { 329 && TLI->getRegClassFor(VT) 330 && TLI->getRegClassFor(VT)->getID() == RCId) 340 if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT) 341 && TLI->getRegClassFor(VT)->getID() == RCId) 478 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); 489 const TargetRegisterClass *RC = TLI->getRegClassFor(VT);
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H A D | InstrEmitter.cpp | 108 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); 167 DstRC = TLI->getRegClassFor(VT, Node->isDivergent()); 210 const TargetRegisterClass *VTRC = TLI->getRegClassFor( 273 const TargetRegisterClass *RC = TLI->getRegClassFor( 383 ? TLI->getRegClassFor(OpVT, 465 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx); 500 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent()); 570 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
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H A D | FastISel.cpp | 460 Reg = createResultReg(TLI.getRegClassFor(VT)); 957 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64)); 1567 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT); 1568 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT); 2247 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
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H A D | FunctionLoweringInfo.cpp | 359 MF->getSubtarget().getTargetLowering()->getRegClassFor(VT, isDivergent));
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H A D | SelectionDAGISel.cpp | 1250 TLI->getRegClassFor(TLI->getPointerTy(CurDAG->getDataLayout()));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | SwiftErrorValueTracking.cpp | 36 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); 58 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); 126 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); 241 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
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H A D | CallingConvLower.cpp | 251 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT);
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H A D | MachineScheduler.cpp | 2761 TLI->getRegClassFor(LegalIntVT));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 401 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); 411 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); 437 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); 453 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); 517 ResultReg = createResultReg(TLI.getRegClassFor(VT)); 610 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); 624 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); 675 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); 981 RC = TLI.getRegClassFor(VT); 993 RC = TLI.getRegClassFor(V [all...] |
H A D | ARMISelLowering.h | 479 /// getRegClassFor - Return the register class that should be used for the 482 getRegClassFor(MVT VT, bool isDivergent = false) const override;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 468 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 2025 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); 2200 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); 2352 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); 2380 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); 2450 const TargetRegisterClass *RC = TLI.getRegClassFor(DstVT); 2510 return X86SelectFPExtOrFPTrunc(I, Opc, TLI.getRegClassFor(MVT::f64)); 2524 return X86SelectFPExtOrFPTrunc(I, Opc, TLI.getRegClassFor(MVT::f32)); 2626 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::v8i16); 2838 const TargetRegisterClass *RC = TLI.getRegClassFor(V [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 1634 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1653 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1656 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1849 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1901 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1904 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 2527 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 3652 const TargetRegisterClass *RC = getRegClassFor(RegVT); 3719 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); 4057 RC = getRegClassFor(V [all...] |
H A D | MipsSEISelDAGToDAG.cpp | 1191 TLI->getRegClassFor(ViaVecTy.getSimpleVT()); 1260 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
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H A D | MipsFastISel.cpp | 1300 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.h | 405 getRegClassFor(MVT VT, bool isDivergent) const override;
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H A D | SIISelLowering.cpp | 4575 unsigned Reg = MF.addLiveIn(TRI->getReturnAddressReg(MF), getRegClassFor(VT, Op.getNode()->isDivergent())); 10376 getRegClassFor(VT, Src0.getNode()->isDivergent()); 10993 SITargetLowering::getRegClassFor(MVT VT, bool isDivergent) const { function in class:SITargetLowering 10994 const TargetRegisterClass *RC = TargetLoweringBase::getRegClassFor(VT, false);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 414 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); 427 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); 447 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); 562 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true); 2945 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg, 3178 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); 3646 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); 3820 ResultReg1 = createResultReg(TLI.getRegClassFor(VT));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 516 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); 1071 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 567 const TargetRegisterClass *RC = getRegClassFor(MVT::i64);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 1521 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT); 1526 ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetLowering.h | 707 virtual const TargetRegisterClass *getRegClassFor(MVT VT, bool isDivergent = false) const { function
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 712 getRegClassFor(MVT::i16));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 944 MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrVT));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 792 const TargetRegisterClass *RC = getRegClassFor(RegVT); 1041 unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 601 getRegClassFor(VA.getLocVT())); 2673 unsigned RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT));
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