Searched refs:getRegClassFor (Results 1 - 25 of 32) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp95 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
133 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
329 && TLI->getRegClassFor(VT)
330 && TLI->getRegClassFor(VT)->getID() == RCId)
340 if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT)
341 && TLI->getRegClassFor(VT)->getID() == RCId)
478 const TargetRegisterClass *RC = TLI->getRegClassFor(VT);
489 const TargetRegisterClass *RC = TLI->getRegClassFor(VT);
H A DInstrEmitter.cpp108 UseRC = TLI->getRegClassFor(VT, Node->isDivergent());
167 DstRC = TLI->getRegClassFor(VT, Node->isDivergent());
210 const TargetRegisterClass *VTRC = TLI->getRegClassFor(
273 const TargetRegisterClass *RC = TLI->getRegClassFor(
383 ? TLI->getRegClassFor(OpVT,
465 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
500 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
570 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
H A DFastISel.cpp460 Reg = createResultReg(TLI.getRegClassFor(VT));
957 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64));
1567 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT);
1568 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT);
2247 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
H A DFunctionLoweringInfo.cpp359 MF->getSubtarget().getTargetLowering()->getRegClassFor(VT, isDivergent));
H A DSelectionDAGISel.cpp1250 TLI->getRegClassFor(TLI->getPointerTy(CurDAG->getDataLayout()));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DSwiftErrorValueTracking.cpp36 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
58 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
126 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
241 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
H A DCallingConvLower.cpp251 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT);
H A DMachineScheduler.cpp2761 TLI->getRegClassFor(LegalIntVT));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp401 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
411 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
437 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
453 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
517 ResultReg = createResultReg(TLI.getRegClassFor(VT));
610 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
624 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
675 const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
981 RC = TLI.getRegClassFor(VT);
993 RC = TLI.getRegClassFor(V
[all...]
H A DARMISelLowering.h479 /// getRegClassFor - Return the register class that should be used for the
482 getRegClassFor(MVT VT, bool isDivergent = false) const override;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp468 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
2025 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
2200 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
2352 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
2380 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
2450 const TargetRegisterClass *RC = TLI.getRegClassFor(DstVT);
2510 return X86SelectFPExtOrFPTrunc(I, Opc, TLI.getRegClassFor(MVT::f64));
2524 return X86SelectFPExtOrFPTrunc(I, Opc, TLI.getRegClassFor(MVT::f32));
2626 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::v8i16);
2838 const TargetRegisterClass *RC = TLI.getRegClassFor(V
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1634 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1653 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1656 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1849 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1901 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1904 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
2527 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
3652 const TargetRegisterClass *RC = getRegClassFor(RegVT);
3719 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));
4057 RC = getRegClassFor(V
[all...]
H A DMipsSEISelDAGToDAG.cpp1191 TLI->getRegClassFor(ViaVecTy.getSimpleVT());
1260 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
H A DMipsFastISel.cpp1300 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.h405 getRegClassFor(MVT VT, bool isDivergent) const override;
H A DSIISelLowering.cpp4575 unsigned Reg = MF.addLiveIn(TRI->getReturnAddressReg(MF), getRegClassFor(VT, Op.getNode()->isDivergent()));
10376 getRegClassFor(VT, Src0.getNode()->isDivergent());
10993 SITargetLowering::getRegClassFor(MVT VT, bool isDivergent) const { function in class:SITargetLowering
10994 const TargetRegisterClass *RC = TargetLoweringBase::getRegClassFor(VT, false);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp414 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm);
427 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
447 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
562 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true);
2945 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg,
3178 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
3646 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
3820 ResultReg1 = createResultReg(TLI.getRegClassFor(VT));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp516 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1071 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp567 const TargetRegisterClass *RC = getRegClassFor(MVT::i64);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1521 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
1526 ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h707 virtual const TargetRegisterClass *getRegClassFor(MVT VT, bool isDivergent = false) const { function
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp712 getRegClassFor(MVT::i16));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp944 MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrVT));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp792 const TargetRegisterClass *RC = getRegClassFor(RegVT);
1041 unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp601 getRegClassFor(VA.getLocVT()));
2673 unsigned RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT));

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