1284677Sdim//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 2284677Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6284677Sdim// 7284677Sdim//===----------------------------------------------------------------------===// 8284677Sdim// 9284677Sdim/// \file 10341825Sdim/// SI DAG Lowering interface definition 11284677Sdim// 12284677Sdim//===----------------------------------------------------------------------===// 13284677Sdim 14309124Sdim#ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 15309124Sdim#define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 16284677Sdim 17284677Sdim#include "AMDGPUISelLowering.h" 18327952Sdim#include "AMDGPUArgumentUsageInfo.h" 19284677Sdim#include "SIInstrInfo.h" 20284677Sdim 21284677Sdimnamespace llvm { 22284677Sdim 23309124Sdimclass SITargetLowering final : public AMDGPUTargetLowering { 24341825Sdimprivate: 25341825Sdim const GCNSubtarget *Subtarget; 26341825Sdim 27341825Sdimpublic: 28341825Sdim MVT getRegisterTypeForCallingConv(LLVMContext &Context, 29341825Sdim CallingConv::ID CC, 30341825Sdim EVT VT) const override; 31341825Sdim unsigned getNumRegistersForCallingConv(LLVMContext &Context, 32341825Sdim CallingConv::ID CC, 33341825Sdim EVT VT) const override; 34341825Sdim 35341825Sdim unsigned getVectorTypeBreakdownForCallingConv( 36341825Sdim LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 37341825Sdim unsigned &NumIntermediates, MVT &RegisterVT) const override; 38341825Sdim 39341825Sdimprivate: 40321369Sdim SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL, 41321369Sdim SDValue Chain, uint64_t Offset) const; 42327952Sdim SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const; 43321369Sdim SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, 44321369Sdim const SDLoc &SL, SDValue Chain, 45341825Sdim uint64_t Offset, unsigned Align, bool Signed, 46321369Sdim const ISD::InputArg *Arg = nullptr) const; 47321369Sdim 48321369Sdim SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA, 49321369Sdim const SDLoc &SL, SDValue Chain, 50321369Sdim const ISD::InputArg &Arg) const; 51327952Sdim SDValue getPreloadedValue(SelectionDAG &DAG, 52327952Sdim const SIMachineFunctionInfo &MFI, 53327952Sdim EVT VT, 54327952Sdim AMDGPUFunctionArgInfo::PreloadedValue) const; 55321369Sdim 56284677Sdim SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 57284677Sdim SelectionDAG &DAG) const override; 58296417Sdim SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, 59296417Sdim MVT VT, unsigned Offset) const; 60341825Sdim SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr, 61341825Sdim SelectionDAG &DAG) const; 62344779Sdim SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset, 63353358Sdim SDValue GLC, SDValue DLC, SelectionDAG &DAG) const; 64296417Sdim 65284677Sdim SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 66309124Sdim SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 67284677Sdim SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 68341825Sdim 69344779Sdim // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset 70344779Sdim // (the offset that is included in bounds checking and swizzling, to be split 71344779Sdim // between the instruction's voffset and immoffset fields) and soffset (the 72344779Sdim // offset that is excluded from bounds checking and swizzling, to go in the 73344779Sdim // instruction's soffset field). This function takes the first kind of 74344779Sdim // offset and figures out how to split it between voffset and immoffset. 75344779Sdim std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset, 76344779Sdim SelectionDAG &DAG) const; 77344779Sdim 78341825Sdim SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const; 79284677Sdim SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 80284677Sdim SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 81309124Sdim SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const; 82309124Sdim SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const; 83314564Sdim SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const; 84284677Sdim SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const; 85284677Sdim SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const; 86284677Sdim SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const; 87284677Sdim SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const; 88284677Sdim SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 89284677Sdim SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; 90309124Sdim SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 91284677Sdim SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 92353358Sdim SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 93341825Sdim SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M, 94344779Sdim SelectionDAG &DAG, ArrayRef<SDValue> Ops, 95341825Sdim bool IsIntrinsic = false) const; 96341825Sdim 97360784Sdim SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG, 98360784Sdim ArrayRef<SDValue> Ops) const; 99360784Sdim 100353358Sdim // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to 101353358Sdim // dwordx4 if on SI. 102353358Sdim SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, 103353358Sdim ArrayRef<SDValue> Ops, EVT MemVT, 104353358Sdim MachineMemOperand *MMO, SelectionDAG &DAG) const; 105353358Sdim 106341825Sdim SDValue handleD16VData(SDValue VData, SelectionDAG &DAG) const; 107341825Sdim 108341825Sdim /// Converts \p Op, which must be of floating point type, to the 109314564Sdim /// floating point type \p VT, by either extending or truncating it. 110314564Sdim SDValue getFPExtOrFPTrunc(SelectionDAG &DAG, 111314564Sdim SDValue Op, 112314564Sdim const SDLoc &DL, 113314564Sdim EVT VT) const; 114314564Sdim 115321369Sdim SDValue convertArgType( 116321369Sdim SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val, 117321369Sdim bool Signed, const ISD::InputArg *Arg = nullptr) const; 118321369Sdim 119341825Sdim /// Custom lowering for ISD::FP_ROUND for MVT::f16. 120314564Sdim SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 121344779Sdim SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const; 122314564Sdim 123321369Sdim SDValue getSegmentAperture(unsigned AS, const SDLoc &DL, 124321369Sdim SelectionDAG &DAG) const; 125321369Sdim 126309124Sdim SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const; 127353358Sdim SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 128321369Sdim SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 129321369Sdim SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 130353358Sdim SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 131341825Sdim SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 132309124Sdim SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const; 133341825Sdim SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const; 134309124Sdim 135327952Sdim SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; 136284677Sdim 137284677Sdim SDValue performUCharToFloatCombine(SDNode *N, 138284677Sdim DAGCombinerInfo &DCI) const; 139284677Sdim SDValue performSHLPtrCombine(SDNode *N, 140284677Sdim unsigned AS, 141327952Sdim EVT MemVT, 142284677Sdim DAGCombinerInfo &DCI) const; 143314564Sdim 144314564Sdim SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const; 145314564Sdim 146314564Sdim SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL, 147314564Sdim unsigned Opc, SDValue LHS, 148314564Sdim const ConstantSDNode *CRHS) const; 149314564Sdim 150284677Sdim SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const; 151284677Sdim SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const; 152314564Sdim SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const; 153321369Sdim SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const; 154353358Sdim SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const; 155284677Sdim SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const; 156344779Sdim SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT, 157344779Sdim const APFloat &C) const; 158309124Sdim SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const; 159284677Sdim 160321369Sdim SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 161321369Sdim SDValue Op0, SDValue Op1) const; 162321369Sdim SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 163321369Sdim SDValue Op0, SDValue Op1, bool Signed) const; 164309124Sdim SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const; 165321369Sdim SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const; 166321369Sdim SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const; 167321369Sdim SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 168344779Sdim SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 169309124Sdim 170353358Sdim SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const; 171314564Sdim unsigned getFusedOpcode(const SelectionDAG &DAG, 172314564Sdim const SDNode *N0, const SDNode *N1) const; 173321369Sdim SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 174321369Sdim SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const; 175321369Sdim SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 176314564Sdim SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 177314564Sdim SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 178341825Sdim SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const; 179284677Sdim SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; 180314564Sdim SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const; 181341825Sdim SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const; 182341825Sdim SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const; 183284677Sdim 184287521Sdim bool isLegalFlatAddressingMode(const AddrMode &AM) const; 185296417Sdim bool isLegalMUBUFAddressingMode(const AddrMode &AM) const; 186309124Sdim 187321369Sdim unsigned isCFIntrinsic(const SDNode *Intr) const; 188309124Sdim 189360784Sdimpublic: 190314564Sdim /// \returns True if fixup needs to be emitted for given global value \p GV, 191314564Sdim /// false otherwise. 192314564Sdim bool shouldEmitFixup(const GlobalValue *GV) const; 193314564Sdim 194314564Sdim /// \returns True if GOT relocation needs to be emitted for given global value 195314564Sdim /// \p GV, false otherwise. 196314564Sdim bool shouldEmitGOTReloc(const GlobalValue *GV) const; 197314564Sdim 198314564Sdim /// \returns True if PC-relative relocation needs to be emitted for given 199314564Sdim /// global value \p GV, false otherwise. 200314564Sdim bool shouldEmitPCReloc(const GlobalValue *GV) const; 201314564Sdim 202360784Sdimprivate: 203344779Sdim // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the 204344779Sdim // three offsets (voffset, soffset and instoffset) into the SDValue[3] array 205344779Sdim // pointed to by Offsets. 206360784Sdim /// \returns 0 If there is a non-constant offset or if the offset is 0. 207360784Sdim /// Otherwise returns the constant offset. 208360784Sdim unsigned setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG, 209360784Sdim SDValue *Offsets, unsigned Align = 4) const; 210344779Sdim 211353358Sdim // Handle 8 bit and 16 bit buffer loads 212353358Sdim SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL, 213353358Sdim ArrayRef<SDValue> Ops, MemSDNode *M) const; 214353358Sdim 215353358Sdim // Handle 8 bit and 16 bit buffer stores 216353358Sdim SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType, 217353358Sdim SDLoc DL, SDValue Ops[], 218353358Sdim MemSDNode *M) const; 219353358Sdim 220284677Sdimpublic: 221341825Sdim SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI); 222284677Sdim 223341825Sdim const GCNSubtarget *getSubtarget() const; 224309124Sdim 225360784Sdim bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, 226360784Sdim EVT SrcVT) const override; 227341825Sdim 228327952Sdim bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override; 229321369Sdim 230309124Sdim bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 231327952Sdim MachineFunction &MF, 232309124Sdim unsigned IntrinsicID) const override; 233309124Sdim 234321369Sdim bool getAddrModeArguments(IntrinsicInst * /*I*/, 235321369Sdim SmallVectorImpl<Value*> &/*Ops*/, 236321369Sdim Type *&/*AccessTy*/) const override; 237284677Sdim 238344779Sdim bool isLegalGlobalAddressingMode(const AddrMode &AM) const; 239286684Sdim bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 240327952Sdim unsigned AS, 241327952Sdim Instruction *I = nullptr) const override; 242284677Sdim 243321369Sdim bool canMergeStoresTo(unsigned AS, EVT MemVT, 244321369Sdim const SelectionDAG &DAG) const override; 245321369Sdim 246360784Sdim bool allowsMisalignedMemoryAccessesImpl( 247360784Sdim unsigned Size, unsigned AS, unsigned Align, 248360784Sdim MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 249360784Sdim bool *IsFast = nullptr) const; 250360784Sdim 251353358Sdim bool allowsMisalignedMemoryAccesses( 252353358Sdim EVT VT, unsigned AS, unsigned Align, 253353358Sdim MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 254353358Sdim bool *IsFast = nullptr) const override; 255284677Sdim 256284677Sdim EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 257284677Sdim unsigned SrcAlign, bool IsMemset, 258284677Sdim bool ZeroMemset, 259284677Sdim bool MemcpyStrSrc, 260353358Sdim const AttributeList &FuncAttributes) const override; 261284677Sdim 262296417Sdim bool isMemOpUniform(const SDNode *N) const; 263314564Sdim bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const; 264360784Sdim 265360784Sdim static bool isFlatGlobalAddrSpace(unsigned AS) { 266360784Sdim return AS == AMDGPUAS::GLOBAL_ADDRESS || 267360784Sdim AS == AMDGPUAS::FLAT_ADDRESS || 268360784Sdim AS == AMDGPUAS::CONSTANT_ADDRESS || 269360784Sdim AS > AMDGPUAS::MAX_AMDGPU_ADDRESS; 270360784Sdim } 271360784Sdim 272296417Sdim bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 273353358Sdim bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 274296417Sdim 275284677Sdim TargetLoweringBase::LegalizeTypeAction 276344779Sdim getPreferredVectorAction(MVT VT) const override; 277284677Sdim 278284677Sdim bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 279284677Sdim Type *Ty) const override; 280284677Sdim 281309124Sdim bool isTypeDesirableForOp(unsigned Op, EVT VT) const override; 282309124Sdim 283309124Sdim bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 284309124Sdim 285327952Sdim bool supportSplitCSR(MachineFunction *MF) const override; 286327952Sdim void initializeSplitCSR(MachineBasicBlock *Entry) const override; 287327952Sdim void insertCopiesSplitCSR( 288327952Sdim MachineBasicBlock *Entry, 289327952Sdim const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 290327952Sdim 291284677Sdim SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 292284677Sdim bool isVarArg, 293284677Sdim const SmallVectorImpl<ISD::InputArg> &Ins, 294309124Sdim const SDLoc &DL, SelectionDAG &DAG, 295284677Sdim SmallVectorImpl<SDValue> &InVals) const override; 296284677Sdim 297321369Sdim bool CanLowerReturn(CallingConv::ID CallConv, 298321369Sdim MachineFunction &MF, bool isVarArg, 299296417Sdim const SmallVectorImpl<ISD::OutputArg> &Outs, 300321369Sdim LLVMContext &Context) const override; 301321369Sdim 302321369Sdim SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 303321369Sdim const SmallVectorImpl<ISD::OutputArg> &Outs, 304309124Sdim const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 305309124Sdim SelectionDAG &DAG) const override; 306296417Sdim 307327952Sdim void passSpecialInputs( 308327952Sdim CallLoweringInfo &CLI, 309344779Sdim CCState &CCInfo, 310327952Sdim const SIMachineFunctionInfo &Info, 311327952Sdim SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, 312327952Sdim SmallVectorImpl<SDValue> &MemOpChains, 313344779Sdim SDValue Chain) const; 314327952Sdim 315327952Sdim SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 316327952Sdim CallingConv::ID CallConv, bool isVarArg, 317327952Sdim const SmallVectorImpl<ISD::InputArg> &Ins, 318327952Sdim const SDLoc &DL, SelectionDAG &DAG, 319327952Sdim SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 320327952Sdim SDValue ThisVal) const; 321327952Sdim 322327952Sdim bool mayBeEmittedAsTailCall(const CallInst *) const override; 323327952Sdim 324327952Sdim bool isEligibleForTailCallOptimization( 325327952Sdim SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 326327952Sdim const SmallVectorImpl<ISD::OutputArg> &Outs, 327327952Sdim const SmallVectorImpl<SDValue> &OutVals, 328327952Sdim const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const; 329327952Sdim 330327952Sdim SDValue LowerCall(CallLoweringInfo &CLI, 331327952Sdim SmallVectorImpl<SDValue> &InVals) const override; 332327952Sdim 333360784Sdim Register getRegisterByName(const char* RegName, LLT VT, 334360784Sdim const MachineFunction &MF) const override; 335309124Sdim 336309124Sdim MachineBasicBlock *splitKillBlock(MachineInstr &MI, 337309124Sdim MachineBasicBlock *BB) const; 338309124Sdim 339360784Sdim void bundleInstWithWaitcnt(MachineInstr &MI) const; 340353358Sdim MachineBasicBlock *emitGWSMemViolTestLoop(MachineInstr &MI, 341353358Sdim MachineBasicBlock *BB) const; 342353358Sdim 343309124Sdim MachineBasicBlock * 344309124Sdim EmitInstrWithCustomInserter(MachineInstr &MI, 345309124Sdim MachineBasicBlock *BB) const override; 346327952Sdim 347327952Sdim bool hasBitPreservingFPLogic(EVT VT) const override; 348284677Sdim bool enableAggressiveFMAFusion(EVT VT) const override; 349286684Sdim EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 350286684Sdim EVT VT) const override; 351286684Sdim MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; 352360784Sdim bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 353360784Sdim EVT VT) const override; 354360784Sdim bool isFMADLegalForFAddFSub(const SelectionDAG &DAG, 355360784Sdim const SDNode *N) const override; 356360784Sdim 357341825Sdim SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 358341825Sdim SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 359360784Sdim SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 360284677Sdim SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 361341825Sdim 362321369Sdim void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 363321369Sdim SelectionDAG &DAG) const override; 364321369Sdim 365284677Sdim SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 366284677Sdim SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; 367309124Sdim void AdjustInstrPostInstrSelection(MachineInstr &MI, 368284677Sdim SDNode *Node) const override; 369284677Sdim 370321369Sdim SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const; 371284677Sdim 372309124Sdim MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, 373309124Sdim SDValue Ptr) const; 374309124Sdim MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, 375309124Sdim uint32_t RsrcDword1, uint64_t RsrcDword2And3) const; 376286684Sdim std::pair<unsigned, const TargetRegisterClass *> 377286684Sdim getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 378286684Sdim StringRef Constraint, MVT VT) const override; 379296417Sdim ConstraintType getConstraintType(StringRef Constraint) const override; 380309124Sdim SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, 381309124Sdim SDValue V) const; 382321369Sdim 383321369Sdim void finalizeLowering(MachineFunction &MF) const override; 384327952Sdim 385327952Sdim void computeKnownBitsForFrameIndex(const SDValue Op, 386327952Sdim KnownBits &Known, 387327952Sdim const APInt &DemandedElts, 388327952Sdim const SelectionDAG &DAG, 389327952Sdim unsigned Depth = 0) const override; 390341825Sdim 391341825Sdim bool isSDNodeSourceOfDivergence(const SDNode *N, 392344779Sdim FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override; 393344779Sdim 394344779Sdim bool isCanonicalized(SelectionDAG &DAG, SDValue Op, 395344779Sdim unsigned MaxDepth = 5) const; 396360784Sdim bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const; 397344779Sdim 398344779Sdim bool isKnownNeverNaNForTargetNode(SDValue Op, 399344779Sdim const SelectionDAG &DAG, 400344779Sdim bool SNaN = false, 401344779Sdim unsigned Depth = 0) const override; 402353358Sdim AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override; 403353358Sdim 404360784Sdim virtual const TargetRegisterClass * 405360784Sdim getRegClassFor(MVT VT, bool isDivergent) const override; 406360784Sdim virtual bool requiresUniformRegister(MachineFunction &MF, 407360784Sdim const Value *V) const override; 408360784Sdim Align getPrefLoopAlignment(MachineLoop *ML) const override; 409360784Sdim 410360784Sdim void allocateHSAUserSGPRs(CCState &CCInfo, 411360784Sdim MachineFunction &MF, 412360784Sdim const SIRegisterInfo &TRI, 413360784Sdim SIMachineFunctionInfo &Info) const; 414360784Sdim 415360784Sdim void allocateSystemSGPRs(CCState &CCInfo, 416360784Sdim MachineFunction &MF, 417360784Sdim SIMachineFunctionInfo &Info, 418360784Sdim CallingConv::ID CallConv, 419360784Sdim bool IsShader) const; 420360784Sdim 421360784Sdim void allocateSpecialEntryInputVGPRs(CCState &CCInfo, 422360784Sdim MachineFunction &MF, 423360784Sdim const SIRegisterInfo &TRI, 424360784Sdim SIMachineFunctionInfo &Info) const; 425360784Sdim void allocateSpecialInputSGPRs( 426360784Sdim CCState &CCInfo, 427360784Sdim MachineFunction &MF, 428360784Sdim const SIRegisterInfo &TRI, 429360784Sdim SIMachineFunctionInfo &Info) const; 430360784Sdim 431360784Sdim void allocateSpecialInputVGPRs(CCState &CCInfo, 432360784Sdim MachineFunction &MF, 433360784Sdim const SIRegisterInfo &TRI, 434360784Sdim SIMachineFunctionInfo &Info) const; 435284677Sdim}; 436284677Sdim 437284677Sdim} // End namespace llvm 438284677Sdim 439284677Sdim#endif 440