/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 1042 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, 1070 SETLT, // 1 X 1 0 0 True if less than enumerator in enum:llvm::ISD::CondCode 1081 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 490 case ISD::SETLT: 693 SET_NEWCC(SETLT, JSLT); 704 CC == ISD::SETLT ||
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 2984 // Handle SETLT -1 (which is equivalent to SETGE 0). 3007 case ISD::SETLT: { 3011 // Handle SETLT 1 (which is equivalent to SETLE 0). 3186 case ISD::SETLT: { 3341 case ISD::SETLT: { 3501 case ISD::SETLT: { 3798 case ISD::SETLT: 3825 case ISD::SETLT: 3871 case ISD::SETLT: 3898 case ISD::SETLT [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 329 case ISD::SETLT: 735 // if we don't care about FP signed-zero. The use of SETLT with FP means 737 if (CC == ISD::SETLT && Op1.getValueType().isInteger() && 1305 // if we don't care about FP signed-zero. The use of SETLT with FP means 1307 if (CC == ISD::SETLT && Op1.getValueType().isInteger() && 3382 case ISD::SETLT: 3599 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; 3611 if (Cond == ISD::SETLT || Cond == ISD::SETULT) { 3659 // SETUGT X, SINTMAX -> SETLT X, 0 3664 ISD::SETLT); [all...] |
H A D | LegalizeIntegerTypes.cpp | 1400 case ISD::SETLT: 2225 return std::make_pair(ISD::SETLT, ISD::UMIN); 3062 SDValue ProdNeg = DAG.getSetCC(dl, BoolVT, Product, Zero, ISD::SETLT); 3203 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT); 3212 SDValue HLNeg = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETLT); 3216 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT); 3230 SatMin = DAG.getSetCC(dl, BoolNVT, ResultHH, HHHiMask, ISD::SETLT); 3846 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 3857 case ISD::SETLT: 3927 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperand [all...] |
H A D | SelectionDAGDumper.cpp | 427 case ISD::SETLT: return "setlt";
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H A D | LegalizeDAG.cpp | 1710 case ISD::SETLT: 2433 DAG.getConstant(0, dl, SrcVT), ISD::SETLT); 3176 case ISD::SMIN: Pred = ISD::SETLT; break;
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H A D | DAGCombiner.cpp | 3869 SDValue IsNeg = DAG.getSetCC(DL, CCVT, N1, Zero, ISD::SETLT); 4568 bool OrLtZero = !IsAnd && CC1 == ISD::SETLT && IsZero; 4583 bool AndLtZero = IsAnd && CC1 == ISD::SETLT && IsZero; 8330 case ISD::SETLT: 8393 if (CC == ISD::SETLT && isNullOrNullSplat(CondC) && isNullOrNullSplat(C2)) { 8903 else if ((RHSIsAllZeros && (CC == ISD::SETLT || CC == ISD::SETLE)) && 12506 case ISD::SETLT: 20072 CC == ISD::SETULT || CC == ISD::SETLT)) { 20254 } else if (CC == ISD::SETLT) { 20785 SDValue IsDenorm = DAG.getSetCC(DL, CCVT, Fabs, NormC, ISD::SETLT); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | Analysis.cpp | 227 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; 246 case ICmpInst::ICMP_SLT: return ISD::SETLT;
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H A D | TargetLoweringBase.cpp | 550 CCs[RTLIB::OLT_F32] = ISD::SETLT; 551 CCs[RTLIB::OLT_F64] = ISD::SETLT; 552 CCs[RTLIB::OLT_F128] = ISD::SETLT; 553 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInsertSkips.cpp | 208 case ISD::SETLT:
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H A D | AMDGPUISelLowering.cpp | 1289 case ISD::SETLT: { 1996 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT); 1997 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT); 2119 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT); 2237 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT); 2682 SDValue V = DAG.getSelectCC(DL, E, One, D, N, ISD::SETLT);
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H A D | R600ISelLowering.cpp | 128 setCondCodeAction(ISD::SETLT, MVT::f32, Expand); 140 setCondCodeAction(ISD::SETLT, MVT::i32, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 432 case ISD::SETLT: 474 CC = ISD::SETLT; 489 CC = ISD::SETLT; 492 case ISD::SETLT: {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86IntrinsicsInfo.h | 1005 X86_INTRINSIC_DATA(sse_comilt_ss, COMI, X86ISD::COMI, ISD::SETLT), 1022 X86_INTRINSIC_DATA(sse_ucomilt_ss, COMI, X86ISD::UCOMI, ISD::SETLT), 1029 X86_INTRINSIC_DATA(sse2_comilt_sd, COMI, X86ISD::COMI, ISD::SETLT), 1076 X86_INTRINSIC_DATA(sse2_ucomilt_sd, COMI, X86ISD::UCOMI, ISD::SETLT),
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H A D | X86ISelLowering.cpp | 935 setCondCodeAction(ISD::SETLT, VT, Custom); 1254 setCondCodeAction(ISD::SETLT, VT, Custom); 1577 setCondCodeAction(ISD::SETLT, VT, Custom); 1829 setCondCodeAction(ISD::SETLT, VT, Custom); 4836 case ISD::SETLT: return X86::COND_L; 4859 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 4867 if (SetCCOpcode == ISD::SETLT && RHSC->isOne()) { 4914 case ISD::SETLT: return X86::COND_B; 18737 SDValue IsNeg = DAG.getSetCC(DL, MVT::v4i64, Src, Zero, ISD::SETLT); 19385 Op.getOperand(OpNo), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 203 { RTLIB::OLT_F64, "__mspabi_cmpd", ISD::SETLT }, 209 { RTLIB::OLT_F32, "__mspabi_cmpf", ISD::SETLT }, 1111 case ISD::SETLT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCISelLowering.cpp | 61 case ISD::SETLT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 380 case ISD::SETLT: 771 SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusXLen, Zero, ISD::SETLT); 823 SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusXLen, Zero, ISD::SETLT);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 956 case ISD::SETLT: 1755 Op->getOperand(2), ISD::SETLT); 1761 lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLT);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 805 // For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT, 822 case ISD::SETLT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 1532 case ISD::SETLT: 1593 case ISD::SETLT: 2085 case ISD::SETLT: 2091 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 2112 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 5036 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) { 9713 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 118 setCondCodeAction(ISD::SETLT, T, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 1840 case ISD::SETLT: return ARMCC::LT; 1869 case ISD::SETLT: 4225 case ISD::SETLT: 4228 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 4242 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 4658 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT) 4664 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT) 4729 return CC == ISD::SETLT || CC == ISD::SETLE; 6280 case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH; 6327 case ISD::SETLT [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1369 case ISD::SETLT: return SPCC::ICC_L; 1389 case ISD::SETLT:
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