/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 1042 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, 1068 SETGT, // 1 X 0 1 0 True if greater than enumerator in enum:llvm::ISD::CondCode 1081 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 2980 case ISD::SETGT: { 3161 case ISD::SETGT: { 3318 case ISD::SETGT: { 3479 case ISD::SETGT: { 3806 case ISD::SETGT: 3833 case ISD::SETGT: 3877 case ISD::SETGT: 3900 case ISD::SETGT: return 1; // Bit #1 = SETOGT 3934 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break; 3958 case ISD::SETGT [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | Analysis.cpp | 229 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT; 248 case ICmpInst::ICMP_SGT: return ISD::SETGT;
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H A D | TargetLoweringBase.cpp | 558 CCs[RTLIB::OGT_F32] = ISD::SETGT; 559 CCs[RTLIB::OGT_F64] = ISD::SETGT; 560 CCs[RTLIB::OGT_F128] = ISD::SETGT; 561 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 687 SET_NEWCC(SETGT, JSGT); 702 bool isSignedCmp = (CC == ISD::SETGT ||
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInsertSkips.cpp | 200 case ISD::SETGT:
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H A D | AMDGPUISelLowering.cpp | 1311 case ISD::SETGT: 2120 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT); 2238 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT); 2690 One, Zero, ISD::SETGT); 2695 DAG.getConstant(0x7c00, DL, MVT::i32), V, ISD::SETGT);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86IntrinsicsInfo.h | 1003 X86_INTRINSIC_DATA(sse_comigt_ss, COMI, X86ISD::COMI, ISD::SETGT), 1020 X86_INTRINSIC_DATA(sse_ucomigt_ss, COMI, X86ISD::UCOMI, ISD::SETGT), 1027 X86_INTRINSIC_DATA(sse2_comigt_sd, COMI, X86ISD::COMI, ISD::SETGT), 1074 X86_INTRINSIC_DATA(sse2_ucomigt_sd, COMI, X86ISD::UCOMI, ISD::SETGT),
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H A D | X86ISelLowering.cpp | 934 // setcc all the way to isel and prefer SETGT in some isel patterns. 1253 // setcc all the way to isel and prefer SETGT in some isel patterns. 1576 // setcc all the way to isel and prefer SETGT in some isel patterns. 1828 // setcc all the way to isel and prefer SETGT in some isel patterns. 4834 case ISD::SETGT: return X86::COND_G; 4854 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 4908 case ISD::SETGT: return X86::COND_A; 9678 ISD::CondCode::SETGT); 9717 ISD::CondCode::SETGT); 9753 ISD::CondCode::SETGT); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 1399 case ISD::SETGT: 2221 return std::make_pair(ISD::SETGT, ISD::UMAX); 2624 DAG.getConstant(0, dl, NVT), Hi, ISD::SETGT); 3197 SDValue HHGT0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETGT); 3210 SDValue HHGT0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETGT); 3229 SatMax = DAG.getSetCC(dl, BoolNVT, ResultHH, HHLoMask, ISD::SETGT); 3847 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 3859 case ISD::SETGT: 3927 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break;
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H A D | SelectionDAGDumper.cpp | 425 case ISD::SETGT: return "setgt";
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H A D | TargetLowering.cpp | 341 case ISD::SETGT: 3378 case ISD::SETGT: 3579 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; 3629 if (Cond == ISD::SETGT || Cond == ISD::SETUGT) { 3666 // SETULT X, SINTMIN -> SETGT X, -1 3672 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 3958 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 6090 ISD::SETGT); 6360 Node->getOpcode() == ISD::FMINNUM ? ISD::SETLT : ISD::SETGT; 7306 Result = DAG.getSelectCC(dl, Hi, LowMask, SatMax, Result, ISD::SETGT); [all...] |
H A D | DAGCombiner.cpp | 4564 bool AndGtNeg1 = IsAnd && CC1 == ISD::SETGT && IsNeg1; 4587 bool OrGtNeg1 = !IsAnd && CC1 == ISD::SETGT && IsNeg1; 8348 case ISD::SETGT: 8385 if (CC == ISD::SETGT && isAllOnesOrAllOnesSplat(CondC) && 8899 if (((RHSIsAllZeros && (CC == ISD::SETGT || CC == ISD::SETGE)) || 8900 (ISD::isBuildVectorAllOnes(RHS.getNode()) && CC == ISD::SETGT)) && 9591 if (CC == ISD::SETGT && isAllOnesConstant(Ones) && VT == XVT) { 12514 case ISD::SETGT: 20249 if (CC == ISD::SETGT && TLI.hasAndNot(N2)) { 20279 if (CC == ISD::SETGT) [all...] |
H A D | LegalizeDAG.cpp | 1708 case ISD::SETGT: 3175 case ISD::SMAX: Pred = ISD::SETGT; break;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 205 { RTLIB::OGT_F64, "__mspabi_cmpd", ISD::SETGT }, 211 { RTLIB::OGT_F32, "__mspabi_cmpf", ISD::SETGT }, 1108 case ISD::SETGT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCISelLowering.cpp | 57 case ISD::SETGT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 365 setCondCodeAction(ISD::SETGT, Ty, Expand); 405 setCondCodeAction(ISD::SETGT, Ty, Expand); 958 case ISD::SETGT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 805 // For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT, 812 case ISD::SETGT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 160 ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE, ISD::SETGT, 359 case ISD::SETGT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 459 case ISD::SETGT: {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1370 case ISD::SETGT: return SPCC::ICC_G; 1391 case ISD::SETGT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 1838 case ISD::SETGT: return ARMCC::GT; 1857 case ISD::SETGT: 4228 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 4240 case ISD::SETGT: 4658 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT) 4725 return CC == ISD::SETGT || CC == ISD::SETGE; 6282 case ISD::SETGT: Opc = ARMCC::GT; break; 6328 case ISD::SETGT: Opc = ARMCC::GT; break; 14334 (CC == ISD::SETGT && Imm == 0) ||
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 1528 case ISD::SETGT: 1559 case ISD::SETGT: 2091 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 2107 case ISD::SETGT: 5045 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 573 case ISD::SETGT:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 2509 else if (Cond == ISD::SETGT || Cond == ISD::SETUGT) 2682 case ISD::SETGT:
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