Searched refs:SETGE (Results 1 - 25 of 33) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1043 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.
1069 SETGE, // 1 X 0 1 1 True if greater than or equal enumerator in enum:llvm::ISD::CondCode
1081 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp230 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE;
244 case ICmpInst::ICMP_SGE: return ISD::SETGE;
H A DTargetLoweringBase.cpp546 CCs[RTLIB::OGE_F32] = ISD::SETGE;
547 CCs[RTLIB::OGE_F64] = ISD::SETGE;
548 CCs[RTLIB::OGE_F128] = ISD::SETGE;
549 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp689 SET_NEWCC(SETGE, JSGE);
703 CC == ISD::SETGE ||
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInsertSkips.cpp204 case ISD::SETGE:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp430 case ISD::SETGE:
456 CC = ISD::SETGE;
481 CC = ISD::SETGE;
500 CC = ISD::SETGE;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h1002 X86_INTRINSIC_DATA(sse_comige_ss, COMI, X86ISD::COMI, ISD::SETGE),
1019 X86_INTRINSIC_DATA(sse_ucomige_ss, COMI, X86ISD::UCOMI, ISD::SETGE),
1026 X86_INTRINSIC_DATA(sse2_comige_sd, COMI, X86ISD::COMI, ISD::SETGE),
1073 X86_INTRINSIC_DATA(sse2_ucomige_sd, COMI, X86ISD::UCOMI, ISD::SETGE),
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp2943 case ISD::SETGE: {
2984 // Handle SETLT -1 (which is equivalent to SETGE 0).
3127 case ISD::SETGE: {
3286 case ISD::SETGE: {
3445 case ISD::SETGE: {
3799 case ISD::SETGE:
3826 case ISD::SETGE:
3880 case ISD::SETGE:
3905 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
3933 case ISD::SETLE: CC = ISD::SETGE; Swa
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp202 { RTLIB::OGE_F64, "__mspabi_cmpd", ISD::SETGE },
208 { RTLIB::OGE_F32, "__mspabi_cmpf", ISD::SETGE },
1097 case ISD::SETGE:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp805 // For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT,
840 case ISD::SETGE:
1270 SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp1398 case ISD::SETGE:
3218 SDValue HLPos = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETGE);
3279 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3280 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3285 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3863 case ISD::SETGE:
3895 bool EqAllowed = (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
3929 case ISD::SETLE: CCCode = ISD::SETGE; FlipOperands = true; break;
H A DSelectionDAGDumper.cpp426 case ISD::SETGE: return "setge";
H A DTargetLowering.cpp323 case ISD::SETGE:
3379 case ISD::SETGE:
3571 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
3579 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
3973 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
H A DSelectionDAG.cpp392 case ISD::SETGE: return 1;
2068 case ISD::SETGE: return getBoolConstant(C1.sge(C2), dl, VT, OpVT);
2107 case ISD::SETGE: if (R==APFloat::cmpUnordered)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp59 case ISD::SETGE:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp364 setCondCodeAction(ISD::SETGE, Ty, Expand);
404 setCondCodeAction(ISD::SETGE, Ty, Expand);
959 case ISD::SETGE: return IsV216;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp161 ISD::SETGE, ISD::SETNE};
382 case ISD::SETGE:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1839 case ISD::SETGE: return ARMCC::GE;
1859 case ISD::SETGE:
4226 case ISD::SETGE:
4242 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
4653 CC == ISD::SETULE || CC == ISD::SETGE || CC == ISD::SETLE)
4725 return CC == ISD::SETGT || CC == ISD::SETGE;
5870 ISD::SETGE, ARMcc, DAG, dl);
5880 ISD::SETGE, ARMcc, DAG, dl);
5913 ISD::SETGE, ARMcc, DAG, dl);
5918 ISD::SETGE, ARMc
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp117 setCondCodeAction(ISD::SETGE, T, Expand);
H A DHexagonISelLowering.cpp1566 setCondCodeAction(ISD::SETGE, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2009 ISD::SETGE);
2069 ISD::SETGE);
H A DNVPTXISelDAGToDAG.cpp575 case ISD::SETGE:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1372 case ISD::SETGE: return SPCC::ICC_GE;
1395 case ISD::SETGE:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1530 case ISD::SETGE:
1563 case ISD::SETGE:
2086 case ISD::SETGE:
2112 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
5913 Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64), ISD::SETGE,
5969 Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64), ISD::SETGE,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2502 else if (Cond == ISD::SETGE || Cond == ISD::SETUGE)
2672 case ISD::SETGE:

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