/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.h | 40 // SETCC - Store the conditional code to a register. 41 SETCC, enumerator in enum:llvm::LanaiISD::__anon2285
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H A D | LanaiISelLowering.cpp | 88 setOperationAction(ISD::SETCC, MVT::i32, Custom); 192 case ISD::SETCC: 980 return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag); 1104 case LanaiISD::SETCC: 1105 return "LanaiISD::SETCC"; 1495 case LanaiISD::SETCC:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 1756 { ISD::SETCC, MVT::v2i64, 2 }, 1760 { ISD::SETCC, MVT::v32i16, 1 }, 1761 { ISD::SETCC, MVT::v64i8, 1 }, 1768 { ISD::SETCC, MVT::v8i64, 1 }, 1769 { ISD::SETCC, MVT::v16i32, 1 }, 1770 { ISD::SETCC, MVT::v8f64, 1 }, 1771 { ISD::SETCC, MVT::v16f32, 1 }, 1780 { ISD::SETCC, MVT::v4i64, 1 }, 1781 { ISD::SETCC, MVT::v8i32, 1 }, 1782 { ISD::SETCC, MV [all...] |
H A D | X86ISelLowering.cpp | 407 setOperationAction(ISD::SETCC, VT, Custom); 415 setOperationAction(ISD::SETCC, VT, Custom); 730 setOperationAction(ISD::SETCC, MVT::f128, Custom); 800 setOperationAction(ISD::SETCC, VT, Expand); 927 setOperationAction(ISD::SETCC, VT, Custom); 1246 setOperationAction(ISD::SETCC, VT, Custom); 1419 setOperationAction(ISD::SETCC, VT, Custom); 1570 setOperationAction(ISD::SETCC, VT, Custom); 1743 setOperationAction(ISD::SETCC, VT, Custom); 1820 setOperationAction(ISD::SETCC, V [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 349 /// STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used 504 SETCC, enumerator in enum:llvm::ISD::NodeType
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.h | 54 SETCC,
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H A D | MSP430ISelLowering.cpp | 93 setOperationAction(ISD::SETCC, MVT::i8, Custom); 94 setOperationAction(ISD::SETCC, MVT::i16, Custom); 348 case ISD::SETCC: return LowerSETCC(Op, DAG); 1385 case MSP430ISD::SETCC: return "MSP430ISD::SETCC";
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorTypes.cpp | 63 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; 442 if (Cond->getOpcode() == ISD::SETCC) { 534 // Turn it into a scalar SETCC. 535 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, 592 case ISD::SETCC: 712 /// result must be v1i1, so just convert to a scalar SETCC and wrap 727 // Turn it into a scalar SETCC. 728 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, 849 case ISD::SETCC: 1549 if (Mask.getOpcode() == ISD::SETCC) { [all...] |
H A D | LegalizeDAG.cpp | 1036 case ISD::SETCC: 1041 Node->getOpcode() == ISD::SETCC ? 2 : 1; 1619 /// Legalize a SETCC with given LHS and RHS and condition code CC on the current 1622 /// If the SETCC has been legalized using AND / OR, then the legalized node 1626 /// If the SETCC has been legalized by using getSetCCSwappedOperands(), 1630 /// If the SETCC has been legalized using the inverse condcode, then LHS and 1632 /// will be set to true. The caller must invert the result of the SETCC with 3522 if (Tmp1.getOpcode() == ISD::SETCC) { 3581 if (Tmp2.getOpcode() == ISD::SETCC) { 3603 case ISD::SETCC [all...] |
H A D | DAGCombiner.cpp | 818 if (N.getOpcode() == ISD::SETCC) { 1564 case ISD::SETCC: return visitSETCC(N); 2024 if (Z.getOperand(0).getOpcode() != ISD::SETCC || 4669 TLI.isOperationLegal(ISD::SETCC, OpVT)))) 7076 case ISD::SETCC: 7478 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC && 8376 if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse() || 8490 // can find the SETCC that produced it and inspect its operands. This is 8491 // fairly easy if C is the SETCC node, but it can potentially be 8638 if (N0.getOpcode() == ISD::SETCC) { 20024 SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0), local [all...] |
H A D | LegalizeVectorOps.cpp | 403 case ISD::SETCC: 881 case ISD::SETCC: 1560 Ops[i] = DAG.getNode(ISD::SETCC, dl,
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H A D | SelectionDAGDumper.cpp | 273 case ISD::SETCC: return "setcc";
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H A D | LegalizeFloatTypes.cpp | 795 case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break; 960 NewLHS = DAG.getNode(ISD::SETCC, SDLoc(N), N->getValueType(0), NewLHS, 1671 case ISD::SETCC: Res = ExpandFloatOp_SETCC(N); break; 1692 /// is shared among BR_CC, SELECT_CC, and SETCC handlers. 1976 case ISD::SETCC: R = PromoteFloatOp_SETCC(N, OpNo); break; 2041 // Construct a SETCC that compares the promoted values and sets the conditional
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H A D | LegalizeTypesGeneric.cpp | 523 else if (Cond.getOpcode() == ISD::SETCC) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 106 setOperationAction(ISD::SETCC, MVT::i8, Custom); 107 setOperationAction(ISD::SETCC, MVT::i16, Custom); 108 setOperationAction(ISD::SETCC, MVT::i32, Custom); 109 setOperationAction(ISD::SETCC, MVT::i64, Custom); 701 case ISD::SETCC:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 105 setTargetDAGCombine(ISD::SETCC); 128 setOperationAction(ISD::SETCC, MVT::f16, Promote); 247 setOperationAction(ISD::SETCC, MVT::i32, Legal); 251 setOperationAction(ISD::SETCC, MVT::f32, Legal); 256 setOperationAction(ISD::SETCC, MVT::f64, Legal); 294 setOperationAction(ISD::SETCC, MVT::i64, Legal); 362 setOperationAction(ISD::SETCC, Ty, Legal); 399 setOperationAction(ISD::SETCC, Ty, Legal); 1051 case ISD::SETCC:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 156 setOperationAction(ISD::SETCC, T, Custom); 178 setOperationAction(ISD::SETCC, BoolW, Custom); 1551 case ISD::SETCC: 1581 case ISD::SETCC:
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H A D | HexagonISelLowering.cpp | 1369 setOperationAction(ISD::SETCC, MVT::i8, Custom); 1370 setOperationAction(ISD::SETCC, MVT::i16, Custom); 1371 setOperationAction(ISD::SETCC, MVT::v4i8, Custom); 1372 setOperationAction(ISD::SETCC, MVT::v2i16, Custom); 1575 setOperationAction(ISD::SETCC, MVT::v2i16, Custom); 2933 case ISD::SETCC: return LowerSETCC(Op, DAG);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.h | 366 // This is SETCC with the full mask result which is used for a compare with a 368 SETCC,
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H A D | R600ISelLowering.cpp | 147 setOperationAction(ISD::SETCC, MVT::v4i32, Expand); 148 setOperationAction(ISD::SETCC, MVT::v2i32, Expand); 164 setOperationAction(ISD::SETCC, MVT::i32, Expand); 165 setOperationAction(ISD::SETCC, MVT::f32, Expand); 886 ISD::SETCC, 896 ISD::SETCC,
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H A D | SIISelLowering.cpp | 220 setOperationAction(ISD::SETCC, MVT::i1, Promote); 221 setOperationAction(ISD::SETCC, MVT::v2i1, Expand); 222 setOperationAction(ISD::SETCC, MVT::v4i1, Expand); 223 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 731 setTargetDAGCombine(ISD::SETCC); 1403 if (VT == MVT::i1 && Op == ISD::SETCC) 4232 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS, 4264 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0, 4465 if (Intr->getOpcode() == ISD::SETCC) { 8181 case ISD::SETCC [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 209 setOperationAction(ISD::SETCC, MVT::i32, Custom); 210 setOperationAction(ISD::SETCC, MVT::i64, Custom); 211 setOperationAction(ISD::SETCC, MVT::f16, Custom); 212 setOperationAction(ISD::SETCC, MVT::f32, Custom); 213 setOperationAction(ISD::SETCC, MVT::f64, Custom); 274 setOperationAction(ISD::SETCC, MVT::f128, Custom); 436 setOperationAction(ISD::SETCC, MVT::f16, Promote); 471 setOperationAction(ISD::SETCC, MVT::v4f16, Expand); 498 setOperationAction(ISD::SETCC, MVT::v8f16, Expand); 725 setOperationAction(ISD::SETCC, MV [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 101 setOperationAction(ISD::SETCC, VT, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 2474 // Modifiers to guide how an ISD::SETCC node's result is to be computed 2557 else if (N->getOperand(0).getOpcode() != ISD::SETCC) 2663 // - SETCC 2680 // For SETCC, it produces the respective comparison, for TRUNCATE it truncates 2685 if (OperandOpcode == ISD::SETCC) 3570 assert(Compare.getOpcode() == ISD::SETCC && 3571 "An ISD::SETCC node required here."); 3590 /// Returns an equivalent of a SETCC node but with the result the same width as 3595 assert((Compare.getOpcode() == ISD::SETCC || 3597 "An ISD::SETCC nod [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1529 setOperationAction(ISD::SETCC, MVT::i32, Expand); 1530 setOperationAction(ISD::SETCC, MVT::f32, Expand); 1531 setOperationAction(ISD::SETCC, MVT::f64, Expand); 1532 setOperationAction(ISD::SETCC, MVT::f128, Expand); 1561 setOperationAction(ISD::SETCC, MVT::i64, Expand);
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