1//===-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that MSP430 uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H
15#define LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H
16
17#include "MSP430.h"
18#include "llvm/CodeGen/SelectionDAG.h"
19#include "llvm/CodeGen/TargetLowering.h"
20
21namespace llvm {
22  namespace MSP430ISD {
23    enum NodeType : unsigned {
24      FIRST_NUMBER = ISD::BUILTIN_OP_END,
25
26      /// Return with a flag operand. Operand 0 is the chain operand.
27      RET_FLAG,
28
29      /// Same as RET_FLAG, but used for returning from ISRs.
30      RETI_FLAG,
31
32      /// Y = R{R,L}A X, rotate right (left) arithmetically
33      RRA, RLA,
34
35      /// Y = RRC X, rotate right via carry
36      RRC,
37
38      /// Rotate right via carry, carry gets cleared beforehand by clrc
39      RRCL,
40
41      /// CALL - These operations represent an abstract call
42      /// instruction, which includes a bunch of information.
43      CALL,
44
45      /// Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
46      /// and TargetGlobalAddress.
47      Wrapper,
48
49      /// CMP - Compare instruction.
50      CMP,
51
52      /// SetCC - Operand 0 is condition code, and operand 1 is the flag
53      /// operand produced by a CMP instruction.
54      SETCC,
55
56      /// MSP430 conditional branches. Operand 0 is the chain operand, operand 1
57      /// is the block to branch if condition is true, operand 2 is the
58      /// condition code, and operand 3 is the flag operand produced by a CMP
59      /// instruction.
60      BR_CC,
61
62      /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
63      /// is condition code and operand 4 is flag operand.
64      SELECT_CC,
65
66      /// DADD - Decimal addition with carry
67      /// TODO Nothing generates a node of this type yet.
68      DADD,
69    };
70  }
71
72  class MSP430Subtarget;
73  class MSP430TargetLowering : public TargetLowering {
74  public:
75    explicit MSP430TargetLowering(const TargetMachine &TM,
76                                  const MSP430Subtarget &STI);
77
78    MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
79      return MVT::i8;
80    }
81
82    /// LowerOperation - Provide custom lowering hooks for some operations.
83    SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
84
85    /// getTargetNodeName - This method returns the name of a target specific
86    /// DAG node.
87    const char *getTargetNodeName(unsigned Opcode) const override;
88
89    SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
90    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
91    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
92    SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
93    SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
94    SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
95    SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
96    SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
97    SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
98    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
99    SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
100    SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
101    SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
102
103    TargetLowering::ConstraintType
104    getConstraintType(StringRef Constraint) const override;
105    std::pair<unsigned, const TargetRegisterClass *>
106    getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
107                                 StringRef Constraint, MVT VT) const override;
108
109    /// isTruncateFree - Return true if it's free to truncate a value of type
110    /// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in
111    /// register R15W to i8 by referencing its sub-register R15B.
112    bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
113    bool isTruncateFree(EVT VT1, EVT VT2) const override;
114
115    /// isZExtFree - Return true if any actual instruction that defines a value
116    /// of type Ty1 implicit zero-extends the value to Ty2 in the result
117    /// register. This does not necessarily include registers defined in unknown
118    /// ways, such as incoming arguments, or copies from unknown virtual
119    /// registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not
120    /// necessarily apply to truncate instructions. e.g. on msp430, all
121    /// instructions that define 8-bit values implicit zero-extend the result
122    /// out to 16 bits.
123    bool isZExtFree(Type *Ty1, Type *Ty2) const override;
124    bool isZExtFree(EVT VT1, EVT VT2) const override;
125    bool isZExtFree(SDValue Val, EVT VT2) const override;
126
127    bool isLegalICmpImmediate(int64_t) const override;
128    bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const override;
129
130    MachineBasicBlock *
131    EmitInstrWithCustomInserter(MachineInstr &MI,
132                                MachineBasicBlock *BB) const override;
133    MachineBasicBlock *EmitShiftInstr(MachineInstr &MI,
134                                      MachineBasicBlock *BB) const;
135
136  private:
137    SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
138                           CallingConv::ID CallConv, bool isVarArg,
139                           bool isTailCall,
140                           const SmallVectorImpl<ISD::OutputArg> &Outs,
141                           const SmallVectorImpl<SDValue> &OutVals,
142                           const SmallVectorImpl<ISD::InputArg> &Ins,
143                           const SDLoc &dl, SelectionDAG &DAG,
144                           SmallVectorImpl<SDValue> &InVals) const;
145
146    SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
147                              bool isVarArg,
148                              const SmallVectorImpl<ISD::InputArg> &Ins,
149                              const SDLoc &dl, SelectionDAG &DAG,
150                              SmallVectorImpl<SDValue> &InVals) const;
151
152    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
153                            CallingConv::ID CallConv, bool isVarArg,
154                            const SmallVectorImpl<ISD::InputArg> &Ins,
155                            const SDLoc &dl, SelectionDAG &DAG,
156                            SmallVectorImpl<SDValue> &InVals) const;
157
158    SDValue
159    LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
160                         const SmallVectorImpl<ISD::InputArg> &Ins,
161                         const SDLoc &dl, SelectionDAG &DAG,
162                         SmallVectorImpl<SDValue> &InVals) const override;
163    SDValue
164      LowerCall(TargetLowering::CallLoweringInfo &CLI,
165                SmallVectorImpl<SDValue> &InVals) const override;
166
167    bool CanLowerReturn(CallingConv::ID CallConv,
168                        MachineFunction &MF,
169                        bool IsVarArg,
170                        const SmallVectorImpl<ISD::OutputArg> &Outs,
171                        LLVMContext &Context) const override;
172
173    SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
174                        const SmallVectorImpl<ISD::OutputArg> &Outs,
175                        const SmallVectorImpl<SDValue> &OutVals,
176                        const SDLoc &dl, SelectionDAG &DAG) const override;
177
178    bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
179                                    SDValue &Base,
180                                    SDValue &Offset,
181                                    ISD::MemIndexedMode &AM,
182                                    SelectionDAG &DAG) const override;
183  };
184} // namespace llvm
185
186#endif
187