/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.h | 28 SELECT_CC,
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H A D | BPFISelLowering.cpp | 103 setOperationAction(ISD::SELECT_CC, VT, Custom); 196 case ISD::SELECT_CC: 528 return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops); 539 case BPFISD::SELECT_CC: 540 return "BPFISD::SELECT_CC";
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.h | 36 // SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 38 SELECT_CC, enumerator in enum:llvm::LanaiISD::__anon2285
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H A D | LanaiISelLowering.cpp | 90 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 190 case ISD::SELECT_CC: 998 return DAG.getNode(LanaiISD::SELECT_CC, DL, VTs, TrueV, FalseV, TargetCC, 1102 case LanaiISD::SELECT_CC: 1103 return "LanaiISD::SELECT_CC"; 1499 case LanaiISD::SELECT_CC:
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 496 SELECT_CC, enumerator in enum:llvm::ISD::NodeType 704 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.h | 62 /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 64 SELECT_CC,
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H A D | MSP430ISelLowering.cpp | 97 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); 98 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); 350 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 1216 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); 1235 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); 1386 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC";
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.h | 61 SELECT_CC enumerator in enum:llvm::AVRISD::NodeType
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H A D | AVRISelLowering.cpp | 102 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); 103 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); 104 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 105 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 267 NODE(SELECT_CC); 648 return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops); 665 return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops); 699 case ISD::SELECT_CC:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.h | 31 SELECT_CC,
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H A D | RISCVISelLowering.cpp | 104 setOperationAction(ISD::SELECT_CC, XLenVT, Expand); 172 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 189 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 642 // lowered RISCVISD::SELECT_CC to take advantage of the integer 658 return DAG.getNode(RISCVISD::SELECT_CC, DL, VTs, Ops); 670 return DAG.getNode(RISCVISD::SELECT_CC, DL, VTs, Ops); 2545 case RISCVISD::SELECT_CC: 2546 return "RISCVISD::SELECT_CC";
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.cpp | 161 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 162 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 280 setTargetDAGCombine(ISD::SELECT_CC); 489 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 994 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); 1051 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, 1059 // this SELECT_CC, so we must lower it. 1073 // Lower this unsupported SELECT_CC into a combination of two supported 1074 // SELECT_CC operations. 1075 SDValue Cond = DAG.getNode(ISD::SELECT_CC, D [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeFloatTypes.cpp | 127 case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N); break; 691 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), 792 case ISD::SELECT_CC: Res = SoftenFloatOp_SELECT_CC(N); break; 1119 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 1670 case ISD::SELECT_CC: Res = ExpandFloatOp_SELECT_CC(N); break; 1692 /// is shared among BR_CC, SELECT_CC, and SETCC handlers. 1975 case ISD::SELECT_CC: R = PromoteFloatOp_SELECT_CC(N, OpNo); break; 2036 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0), 2145 case ISD::SELECT_CC: R = PromoteFloatRes_SELECT_CC(N); break; 2355 // Construct a new SELECT_CC nod [all...] |
H A D | LegalizeTypesGeneric.cpp | 549 Lo = DAG.getNode(ISD::SELECT_CC, dl, LL.getValueType(), N->getOperand(0), 551 Hi = DAG.getNode(ISD::SELECT_CC, dl, LH.getValueType(), N->getOperand(0),
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H A D | SelectionDAGDumper.cpp | 279 case ISD::SELECT_CC: return "select_cc";
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H A D | LegalizeDAG.cpp | 1033 case ISD::SELECT_CC: 1038 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 1050 if (Node->getOpcode() == ISD::SELECT_CC) 3641 // illegal; expand it into a SELECT_CC. 3653 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 3661 case ISD::SELECT_CC: { 3677 "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be " 3685 // SELECT_CC is legal, so the condition code must not be. 3713 assert(Legalized && "Can't legalize SELECT_CC with legal condition!"); 3721 // condition code, create a new SELECT_CC nod [all...] |
H A D | LegalizeVectorTypes.cpp | 62 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break; 491 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(), 828 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 2698 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break; 4049 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCISelLowering.cpp | 116 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 171 assert(LHS.getValueType() == MVT::i32 && "Only know how to SELECT_CC i32"); 753 case ISD::SELECT_CC:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 378 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 379 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 646 setOperationAction(ISD::SELECT_CC, VT, Promote); 647 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32); 697 setOperationAction(ISD::SELECT_CC, MVT::v4i32, Expand); 1197 setTargetDAGCombine(ISD::SELECT_CC); 10485 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 12383 N->getOpcode() == ISD::SELECT_CC) { 12425 N->getOperand(0).getOpcode() != ISD::SELECT_CC && 12432 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) [all...] |
H A D | PPCISelDAGToDAG.cpp | 3591 /// the inputs. This can also be used for SELECT_CC if either the true or false 3596 Compare.getOpcode() == ISD::SELECT_CC) && 3607 // The condition code is operand 2 for SETCC and operand 4 for SELECT_CC. 3608 int CCOpNum = Compare.getOpcode() == ISD::SELECT_CC ? 4 : 2; 4237 assert(N->getOpcode() == ISD::SELECT_CC && "Expecting a SELECT_CC here."); 4261 (FalseRes.getOpcode() != ISD::SELECT_CC || CC != ISD::SETEQ))) 4264 bool InnerIsSel = FalseRes.getOpcode() == ISD::SELECT_CC; 4267 SetOrSelCC.getOpcode() != ISD::SELECT_CC) 4270 // Without this setb optimization, the outer SELECT_CC wil [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 167 for (auto Op : {ISD::VSELECT, ISD::SELECT_CC, ISD::SELECT}) { 234 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC}) 1512 return DAG.getNode(ISD::SELECT_CC, DL, MVT::i64, LHS[I], RHS[I],
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1414 // bits (as does the pseudo SELECT_CC expansion). I don't think it 1523 // Sparc has no select or setcc: expand to SELECT_CC. 1543 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 1544 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 1545 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 1546 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); 1563 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 3029 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this, 3102 default: llvm_unreachable("Unknown SELECT_CC!"); 3123 // To "insert" a SELECT_CC instructio [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 130 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote); 249 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 253 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 258 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 296 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 233 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 234 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 235 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom); 236 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 237 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 279 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); 435 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote); 474 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand); 501 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand); 728 setOperationAction(ISD::SELECT_CC, MV [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 93 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 1528 assert((MI.getOpcode() == XCore::SELECT_CC) && 1531 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
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