/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblySelectionDAGInfo.h | 27 SDValue Op3, unsigned Align, bool isVolatile, 33 SDValue Op3, unsigned Align, bool isVolatile, 38 SDValue Op3, unsigned Align, bool IsVolatile,
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H A D | WebAssemblySelectionDAGInfo.cpp | 38 SDValue Op3, unsigned Align, bool IsVolatile, 40 return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3, Align, 36 EmitTargetCodeForMemmove( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool IsVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreSelectionDAGInfo.h | 26 SDValue Op3, unsigned Align, bool isVolatile,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 259 unsigned &Op3) { 269 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2); 538 unsigned Op1, Op2, Op3; local 539 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 543 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 551 unsigned Op1, Op2, Op3; local 552 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 556 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 564 unsigned Op1, Op2, Op3; local 565 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 258 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, unsigned &Op3) argument 577 unsigned Op1, Op2, Op3; local 590 unsigned Op1, Op2, Op3; local 604 unsigned Op1, Op2, Op3; local 619 unsigned Op1, Op2, Op3; local 633 unsigned Op1, Op2, Op3; local 647 unsigned Op1, Op2, Op3, Op4, Op5, Op6; local 681 unsigned Op1, Op2, Op3, Op4, Op5; local 701 unsigned Op1, Op2, Op3; local 720 unsigned Op1, Op2, Op3; local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAGTargetInfo.h | 53 SDValue Op2, SDValue Op3, 69 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, 82 SDValue Op2, SDValue Op3, 94 SDValue Op1, SDValue Op2, SDValue Op3, 51 EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 67 EmitTargetCodeForMemmove( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 80 EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument 93 EmitTargetCodeForMemcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
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H A D | SelectionDAG.h | 1218 SDValue Op3); 1220 SDValue Op3, SDValue Op4); 1222 SDValue Op3, SDValue Op4, SDValue Op5); 1247 SDValue Op1, SDValue Op2, SDValue Op3); 1284 SDValue Op1, SDValue Op2, SDValue Op3); 1290 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3); 1297 SDValue Op3);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 57 SDValue Op3, unsigned Align, bool isVolatile,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 110 const MachineOperand &Op3 = MI->getOperand(Operand + 3); local 111 if (Op3.isGlobal()) 112 AM.GV = Op3.getGlobal(); 114 AM.Disp = Op3.getImm();
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H A D | X86FastISel.cpp | 181 unsigned Op2, bool Op2IsKill, unsigned Op3, 3980 unsigned Op3, bool Op3IsKill) { 3987 Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3); 3994 .addReg(Op3, getKillRegState(Op3IsKill)); 4000 .addReg(Op3, getKillRegState(Op3IsKill)); 3975 fastEmitInst_rrrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill, unsigned Op3, bool Op3IsKill) argument
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H A D | X86ISelDAGToDAG.cpp | 5278 SDValue Op0, Op1, Op2, Op3, Op4; local 5286 if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4)) 5294 OutOps.push_back(Op3);
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H A D | X86InstrInfo.cpp | 1342 unsigned Op1 = 1, Op2 = 2, Op3 = 3; local 1345 Op3++; 1350 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3) 1352 if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/AsmParser/ |
H A D | BPFAsmParser.cpp | 269 BPFOperand &Op3 = (BPFOperand &)*Operands[3]; local 270 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg() 276 && Op0.getReg() != Op3.getReg())
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64InstPrinter.cpp | 78 const MCOperand &Op3 = MI->getOperand(3); local 82 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { 85 switch (Op3.getImm()) { 118 if (Op2.isImm() && Op3.isImm()) { 122 int64_t imms = Op3.getImm(); 152 if (Op2.getImm() > Op3.getImm()) { 155 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; 163 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 4509 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); local 4510 if (Op2.isScalarReg() && Op3.isImm()) { 4511 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm()); 4531 NewOp4, Op3.getStartLoc(), Op3.getEndLoc(), getContext())); 4532 Operands[3] = AArch64Operand::CreateImm(NewOp3, Op3.getStartLoc(), 4533 Op3.getEndLoc(), getContext()); 4595 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); local 4598 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { 4599 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3 4659 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); local 4718 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/ |
H A D | PatternMatch.h | 1227 T2 Op3; member in struct:llvm::PatternMatch::ThreeOps_match 1229 ThreeOps_match(const T0 &Op1, const T1 &Op2, const T2 &Op3) argument 1230 : Op1(Op1), Op2(Op2), Op3(Op3) {} 1236 Op3.match(I->getOperand(2)); 1793 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) { argument 1794 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3)); 1800 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3, argument 1802 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2, Op3),
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.cpp | 1233 const MachineOperand &Op3 = MI.getOperand(3); local 1237 Register Rt = Op3.getReg(); 1241 unsigned K3 = getKillRegState(Op3.isKill()); 1257 const MachineOperand &Op3 = MI.getOperand(3); local 1266 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill 1276 if (Op0.getReg() != Op3.getReg()) { 1280 .add(Op3); 1291 MachineOperand &Op3 = MI.getOperand(3); local 1300 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill 1313 if (Op0.getReg() != Op3 [all...] |
H A D | HexagonSplitDouble.cpp | 908 MachineOperand &Op3 = MI->getOperand(3); local 909 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm()); 910 int64_t Sh64 = Op3.getImm(); 929 // Op0 = S2_asl_i_p_or Op1, Op2, Op3 930 // means: Op0 = or (Op1, asl(Op2, Op3))
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsTargetStreamer.h | 134 MCOperand Op3, SMLoc IDLoc, const MCSubtargetInfo *STI);
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H A D | MipsFastISel.cpp | 238 uint64_t imm2, unsigned Op3, bool Op3IsKill) { 236 fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t imm1, uint64_t imm2, unsigned Op3, bool Op3IsKill) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | ConstantFolding.cpp | 2288 if (const auto *Op3 = dyn_cast<ConstantFP>(Operands[2])) { 2294 V.fusedMultiplyAdd(Op2->getValueAPF(), Op3->getValueAPF(), 2305 if (const auto *Op3 = dyn_cast<ConstantInt>(Operands[2])) { 2318 unsigned Scale = Op3->getValue().getZExtValue();
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsTargetStreamer.cpp | 224 unsigned Reg2, MCOperand Op3, SMLoc IDLoc, 231 TmpInst.addOperand(Op3); 223 emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, MCOperand Op3, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAG.cpp | 7671 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) { 7672 SDValue Ops[] = { Op1, Op2, Op3 }; 7678 SDValue Op3, SDValue Op4) { 7679 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 7685 SDValue Op3, SDValue Op4, SDValue Op5) { 7686 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 7779 SDValue Op2, SDValue Op3) { 7781 SDValue Ops[] = { Op1, Op2, Op3 }; 7986 SDValue Op3) { 7988 SDValue Ops[] = { Op1, Op2, Op3 }; [all...] |
H A D | SelectionDAGBuilder.cpp | 5848 SDValue Op3 = getValue(I.getArgOperand(2)); local 5858 SDValue MC = DAG.getMemcpy(Root, sdl, Op1, Op2, Op3, Align, isVol, 5869 SDValue Op3 = getValue(I.getArgOperand(2)); local 5875 SDValue MS = DAG.getMemset(Root, sdl, Op1, Op2, Op3, Align, isVol, 5884 SDValue Op3 = getValue(I.getArgOperand(2)); local 5894 SDValue MM = DAG.getMemmove(Root, sdl, Op1, Op2, Op3, Align, isVol, 6437 SDValue Op3 = getValue(I.getArgOperand(2)); local 6439 Op1.getValueType(), Op1, Op2, Op3)); 6446 SDValue Op3 = getValue(I.getArgOperand(2)); local 6448 Op1, Op2, Op3, DA [all...] |
H A D | LegalizeIntegerTypes.cpp | 275 // target's atomic operations. Op3 is merely stored and so can be left alone. 277 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); local 292 N->getBasePtr(), Op2, Op3, N->getMemOperand()); 1731 SDValue Op3 = ZExtPromotedInteger(N->getOperand(3)); local 1734 Op2, Op3, Op4),
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/IR/ |
H A D | Verifier.cpp | 4713 auto *Op3 = cast<ConstantInt>(Call.getArgOperand(2)); local 4714 Assert(Op3->getType()->getBitWidth() <= 32, 4720 Op3->getZExtValue() < Op1->getType()->getScalarSizeInBits(), 4724 Assert(Op3->getZExtValue() <= Op1->getType()->getScalarSizeInBits(),
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