/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | RegisterCoalescer.h | 55 const TargetRegisterClass *NewRC = nullptr; member in class:llvm::CoalescerPair 79 bool isPhys() const { return !NewRC; } 85 /// Return true if DstReg is virtual and NewRC is a smaller 107 const TargetRegisterClass *getNewRC() const { return NewRC; }
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H A D | MachineRegisterInfo.cpp | 74 const TargetRegisterClass *NewRC = local 76 if (!NewRC || NewRC == OldRC) 77 return NewRC; 78 if (NewRC->getNumRegs() < MinNumRegs) 80 MRI.setRegClass(Reg, NewRC); 81 return NewRC; 125 const TargetRegisterClass *NewRC = local 129 if (NewRC == OldRC) 134 // Apply the effect of the given operand to NewRC [all...] |
H A D | CriticalAntiDepBreaker.cpp | 192 const TargetRegisterClass *NewRC = nullptr; local 195 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); 199 if (!Classes[Reg] && NewRC) 200 Classes[Reg] = NewRC; 201 else if (!NewRC || Classes[Reg] != NewRC) 320 const TargetRegisterClass *NewRC = nullptr; local 322 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); 326 if (!Classes[Reg] && NewRC) 327 Classes[Reg] = NewRC; [all...] |
H A D | RegisterCoalescer.cpp | 429 NewRC = nullptr; 474 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, 476 if (!NewRC) 481 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); 485 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub); 488 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); 492 if (!NewRC) 503 CrossClass = NewRC != DstRC || NewRC != SrcRC; 1319 const TargetRegisterClass *NewRC local [all...] |
H A D | TailDuplicator.cpp | 440 auto *NewRC = MI->getRegClassConstraint(i, TII, TRI); local 441 if (NewRC == nullptr) 442 NewRC = OrigRC; 443 Register NewReg = MRI->createVirtualRegister(NewRC);
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H A D | PeepholeOptimizer.cpp | 761 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); local 762 // NewRC is only correct if no subregisters are involved. findNextSource() 765 Register NewVR = MRI.createVirtualRegister(NewRC);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRRegisterInfo.h | 63 const TargetRegisterClass *NewRC,
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H A D | AVRRegisterInfo.cpp | 281 const TargetRegisterClass *NewRC, 283 if(this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) { 287 return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, NewRC, LIS); 276 shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonRegisterInfo.h | 65 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
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H A D | HexagonVLIWPacketizer.h | 136 bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
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H A D | HexagonRegisterInfo.cpp | 243 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const { 250 if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID()) 240 shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const argument
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H A D | HexagonFrameLowering.cpp | 2089 // class HaveRC and a new class NewRC. Return nullptr if a common class 2094 const TargetRegisterClass *NewRC) -> const TargetRegisterClass * { 2095 if (HaveRC == nullptr || HaveRC == NewRC) 2096 return NewRC; 2098 if (HaveRC->hasSubClassEq(NewRC)) 2100 if (NewRC->hasSubClassEq(HaveRC)) 2101 return NewRC;
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H A D | HexagonBitSimplify.cpp | 2618 BitTracker::RegisterCell NewRC(W); 2620 NewRC[I] = BitTracker::BitValue(C & 1); 2623 BT.put(BitTracker::RegisterRef(NewR), NewRC); 2686 BitTracker::RegisterCell NewRC(W); 2687 NewRC[0] = BitTracker::BitValue::self(); 2688 NewRC.fill(1, W, BitTracker::BitValue::Zero); 2689 BT.put(BitTracker::RegisterRef(NewR), NewRC);
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H A D | HexagonVLIWPacketizer.cpp | 354 const TargetRegisterClass *NewRC) { 357 if (NewRC == &Hexagon::PredRegsRegClass) { 353 isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC) argument
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H A D | HexagonConstPropagation.cpp | 2896 const TargetRegisterClass *NewRC; local 2903 NewRC = &Hexagon::IntRegsRegClass; 2905 NewRC = &Hexagon::DoubleRegsRegClass; 2906 Register NewR = MRI->createVirtualRegister(NewRC);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZRegisterInfo.h | 86 /// SrcRC and DstRC will be morphed into NewRC if this returns true. 92 const TargetRegisterClass *NewRC,
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H A D | SystemZRegisterInfo.cpp | 345 const TargetRegisterClass *NewRC, 350 if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) && 396 if (NewRC->contains(*SI)) { 405 if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128)) 340 shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | CGSCCPassManager.cpp | 565 for (RefSCC *NewRC : llvm::reverse(make_range(std::next(NewRefSCCs.begin()), 567 assert(NewRC != RC && "Should not encounter the current RefSCC further " 569 UR.RCWorklist.insert(NewRC); 571 << *NewRC << "\n");
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H A D | LazyCallGraph.cpp | 1725 RefSCC *NewRC = createRefSCC(*this); 1726 buildSCCs(*NewRC, Nodes); 1731 RefSCCIndices.insert({NewRC, PostOrderRefSCCs.size()}).second; 1734 PostOrderRefSCCs.push_back(NewRC); 1736 NewRC->verify();
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.h | 205 /// SrcRC and DstRC will be morphed into NewRC if this returns true 211 const TargetRegisterClass *NewRC,
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H A D | ARMBaseRegisterInfo.cpp | 841 const TargetRegisterClass *NewRC, 851 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 && 856 MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC); 836 shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIRegisterInfo.h | 241 const TargetRegisterClass *NewRC,
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H A D | SIRegisterInfo.cpp | 1706 const TargetRegisterClass *NewRC, 1710 unsigned NewSize = getRegSizeInBits(*NewRC); 1701 shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetRegisterInfo.h | 945 /// SrcRC and DstRC will be morphed into NewRC if this returns true. 951 const TargetRegisterClass *NewRC,
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/freebsd-11-stable/contrib/llvm-project/clang/lib/Sema/ |
H A D | SemaTemplate.cpp | 7662 const Expr *NewRC = New->getRequiresClause(); local 7666 Diag(NewRC ? NewRC->getBeginLoc() : New->getTemplateLoc(), 7672 if (!NewRC != !OldRC) { 7678 if (NewRC) { 7681 NewRC->Profile(NewRCID, Context, /*Canonical=*/true);
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