1327952Sdim//===- HexagonPacketizer.h - VLIW packetizer --------------------*- C++ -*-===// 2327952Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6327952Sdim// 7327952Sdim//===----------------------------------------------------------------------===// 8292915Sdim 9327952Sdim#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H 10327952Sdim#define LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H 11327952Sdim 12292915Sdim#include "llvm/CodeGen/DFAPacketizer.h" 13327952Sdim#include "llvm/CodeGen/MachineBasicBlock.h" 14292915Sdim#include "llvm/CodeGen/ScheduleDAG.h" 15327952Sdim#include <vector> 16292915Sdim 17292915Sdimnamespace llvm { 18327952Sdim 19321369Sdimclass HexagonInstrInfo; 20321369Sdimclass HexagonRegisterInfo; 21327952Sdimclass MachineBranchProbabilityInfo; 22327952Sdimclass MachineFunction; 23327952Sdimclass MachineInstr; 24327952Sdimclass MachineLoopInfo; 25327952Sdimclass TargetRegisterClass; 26321369Sdim 27292915Sdimclass HexagonPacketizerList : public VLIWPacketizerList { 28292915Sdim // Vector of instructions assigned to the packet that has just been created. 29327952Sdim std::vector<MachineInstr *> OldPacketMIs; 30292915Sdim 31292915Sdim // Has the instruction been promoted to a dot-new instruction. 32292915Sdim bool PromotedToDotNew; 33292915Sdim 34292915Sdim // Has the instruction been glued to allocframe. 35292915Sdim bool GlueAllocframeStore; 36292915Sdim 37292915Sdim // Has the feeder instruction been glued to new value jump. 38292915Sdim bool GlueToNewValueJump; 39292915Sdim 40327952Sdim // This holds the offset value, when pruning the dependences. 41327952Sdim int64_t ChangedOffset; 42327952Sdim 43292915Sdim // Check if there is a dependence between some instruction already in this 44292915Sdim // packet and this instruction. 45292915Sdim bool Dependence; 46292915Sdim 47292915Sdim // Only check for dependence if there are resources available to 48292915Sdim // schedule this instruction. 49292915Sdim bool FoundSequentialDependence; 50292915Sdim 51327952Sdim bool MemShufDisabled = false; 52327952Sdim 53292915Sdim // Track MIs with ignored dependence. 54292915Sdim std::vector<MachineInstr*> IgnoreDepMIs; 55292915Sdim 56321369Sdim // Set to true if the packet contains an instruction that stalls with an 57321369Sdim // instruction from the previous packet. 58321369Sdim bool PacketStalls = false; 59321369Sdim 60292915Sdimprotected: 61341825Sdim /// A handle to the branch probability pass. 62292915Sdim const MachineBranchProbabilityInfo *MBPI; 63292915Sdim const MachineLoopInfo *MLI; 64292915Sdim 65292915Sdimprivate: 66292915Sdim const HexagonInstrInfo *HII; 67292915Sdim const HexagonRegisterInfo *HRI; 68344779Sdim const bool Minimal; 69292915Sdim 70292915Sdimpublic: 71292915Sdim HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, 72360784Sdim AAResults *AA, const MachineBranchProbabilityInfo *MBPI, 73344779Sdim bool Minimal); 74292915Sdim 75292915Sdim // initPacketizerState - initialize some internal flags. 76292915Sdim void initPacketizerState() override; 77292915Sdim 78292915Sdim // ignorePseudoInstruction - Ignore bundling of pseudo instructions. 79309124Sdim bool ignorePseudoInstruction(const MachineInstr &MI, 80292915Sdim const MachineBasicBlock *MBB) override; 81292915Sdim 82292915Sdim // isSoloInstruction - return true if instruction MI can not be packetized 83292915Sdim // with any other instruction, which means that MI itself is a packet. 84309124Sdim bool isSoloInstruction(const MachineInstr &MI) override; 85292915Sdim 86292915Sdim // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ 87292915Sdim // together. 88292915Sdim bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override; 89292915Sdim 90292915Sdim // isLegalToPruneDependencies - Is it legal to prune dependece between SUI 91292915Sdim // and SUJ. 92292915Sdim bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override; 93292915Sdim 94327952Sdim bool foundLSInPacket(); 95309124Sdim MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override; 96309124Sdim void endPacket(MachineBasicBlock *MBB, 97309124Sdim MachineBasicBlock::iterator MI) override; 98309124Sdim bool shouldAddToPacket(const MachineInstr &MI) override; 99292915Sdim 100292915Sdim void unpacketizeSoloInstrs(MachineFunction &MF); 101292915Sdim 102292915Sdimprotected: 103327952Sdim bool getmemShufDisabled() { 104327952Sdim return MemShufDisabled; 105327952Sdim }; 106327952Sdim void setmemShufDisabled(bool val) { 107327952Sdim MemShufDisabled = val; 108327952Sdim }; 109314564Sdim bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType, 110292915Sdim unsigned DepReg); 111314564Sdim bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType, 112292915Sdim MachineBasicBlock::iterator &MII, 113314564Sdim const TargetRegisterClass *RC); 114314564Sdim bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU, 115292915Sdim unsigned DepReg, MachineBasicBlock::iterator &MII, 116314564Sdim const TargetRegisterClass *RC); 117292915Sdim void cleanUpDotCur(); 118292915Sdim 119314564Sdim bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType, 120292915Sdim MachineBasicBlock::iterator &MII, 121314564Sdim const TargetRegisterClass *RC); 122314564Sdim bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU, 123292915Sdim unsigned DepReg, MachineBasicBlock::iterator &MII, 124314564Sdim const TargetRegisterClass *RC); 125314564Sdim bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU, 126292915Sdim unsigned DepReg, MachineBasicBlock::iterator &MII); 127314564Sdim bool canPromoteToNewValueStore(const MachineInstr &MI, 128314564Sdim const MachineInstr &PacketMI, unsigned DepReg); 129314564Sdim bool demoteToDotOld(MachineInstr &MI); 130314564Sdim bool useCallersSP(MachineInstr &MI); 131314564Sdim void useCalleesSP(MachineInstr &MI); 132327952Sdim bool updateOffset(SUnit *SUI, SUnit *SUJ); 133327952Sdim void undoChangedOffset(MachineInstr &MI); 134309124Sdim bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2); 135314564Sdim bool restrictingDepExistInPacket(MachineInstr&, unsigned); 136314564Sdim bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC); 137314564Sdim bool isCurifiable(MachineInstr &MI); 138314564Sdim bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ); 139327952Sdim 140327952Sdim bool isPromotedToDotNew() const { 141292915Sdim return PromotedToDotNew; 142292915Sdim } 143327952Sdim 144292915Sdim bool tryAllocateResourcesForConstExt(bool Reserve); 145292915Sdim bool canReserveResourcesForConstExt(); 146292915Sdim void reserveResourcesForConstExt(); 147314564Sdim bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J); 148314564Sdim bool hasControlDependence(const MachineInstr &I, const MachineInstr &J); 149321369Sdim bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J); 150344779Sdim bool hasDualStoreDependence(const MachineInstr &I, const MachineInstr &J); 151314564Sdim bool producesStall(const MachineInstr &MI); 152292915Sdim}; 153292915Sdim 154327952Sdim} // end namespace llvm 155327952Sdim 156327952Sdim#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H 157