1234285Sdim//==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==// 2234285Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6234285Sdim// 7234285Sdim//===----------------------------------------------------------------------===// 8234285Sdim// 9234285Sdim// This file contains the Hexagon implementation of the TargetRegisterInfo 10234285Sdim// class. 11234285Sdim// 12234285Sdim//===----------------------------------------------------------------------===// 13234285Sdim 14280031Sdim#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H 15280031Sdim#define LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H 16234285Sdim 17327952Sdim#include "llvm/CodeGen/TargetRegisterInfo.h" 18234285Sdim 19234285Sdim#define GET_REGINFO_HEADER 20234285Sdim#include "HexagonGenRegisterInfo.inc" 21234285Sdim 22234285Sdimnamespace llvm { 23314564Sdim 24314564Sdimnamespace Hexagon { 25314564Sdim // Generic (pseudo) subreg indices for use with getHexagonSubRegIndex. 26314564Sdim enum { ps_sub_lo = 0, ps_sub_hi = 1 }; 27314564Sdim} 28314564Sdim 29288943Sdimclass HexagonRegisterInfo : public HexagonGenRegisterInfo { 30288943Sdimpublic: 31327952Sdim HexagonRegisterInfo(unsigned HwMode); 32234285Sdim 33234285Sdim /// Code Generation virtual methods... 34288943Sdim const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) 35288943Sdim const override; 36321369Sdim const uint32_t *getCallPreservedMask(const MachineFunction &MF, 37321369Sdim CallingConv::ID) const override; 38234285Sdim 39276479Sdim BitVector getReservedRegs(const MachineFunction &MF) const override; 40234285Sdim 41288943Sdim void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, 42288943Sdim unsigned FIOperandNum, RegScavenger *RS = nullptr) const override; 43234285Sdim 44288943Sdim /// Returns true since we may need scavenging for a temporary register 45288943Sdim /// when generating hardware loop instructions. 46276479Sdim bool requiresRegisterScavenging(const MachineFunction &MF) const override { 47234285Sdim return true; 48234285Sdim } 49234285Sdim 50288943Sdim /// Returns true. Spill code for predicate registers might need an extra 51288943Sdim /// register. 52288943Sdim bool requiresFrameIndexScavenging(const MachineFunction &MF) const override { 53288943Sdim return true; 54288943Sdim } 55288943Sdim 56288943Sdim /// Returns true if the frame pointer is valid. 57288943Sdim bool useFPForScavengingIndex(const MachineFunction &MF) const override; 58288943Sdim 59276479Sdim bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override { 60239462Sdim return true; 61239462Sdim } 62239462Sdim 63341825Sdim bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, 64341825Sdim unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, 65341825Sdim const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override; 66341825Sdim 67234285Sdim // Debug information queries. 68234285Sdim unsigned getRARegister() const; 69353358Sdim Register getFrameRegister(const MachineFunction &MF) const override; 70234285Sdim unsigned getFrameRegister() const; 71234285Sdim unsigned getStackRegister() const; 72288943Sdim 73327952Sdim unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC, 74314564Sdim unsigned GenIdx) const; 75314564Sdim 76309124Sdim const MCPhysReg *getCallerSavedRegs(const MachineFunction *MF, 77309124Sdim const TargetRegisterClass *RC) const; 78288943Sdim 79288943Sdim unsigned getFirstCallerSavedNonParamReg() const; 80288943Sdim 81341825Sdim const TargetRegisterClass * 82341825Sdim getPointerRegClass(const MachineFunction &MF, 83341825Sdim unsigned Kind = 0) const override; 84341825Sdim 85288943Sdim bool isEHReturnCalleeSaveReg(unsigned Reg) const; 86234285Sdim}; 87234285Sdim 88234285Sdim} // end namespace llvm 89234285Sdim 90234285Sdim#endif 91