Searched refs:CCInfo (Results 1 - 25 of 37) sorted by relevance

12

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp385 static void allocateHSAUserSGPRs(CCState &CCInfo, argument
394 CCInfo.AllocateReg(PrivateSegmentBufferReg);
400 CCInfo.AllocateReg(DispatchPtrReg);
406 CCInfo.AllocateReg(QueuePtrReg);
417 CCInfo.AllocateReg(InputPtrReg);
423 CCInfo.AllocateReg(DispatchIDReg);
429 CCInfo.AllocateReg(FlatScratchInitReg);
449 CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
451 allocateHSAUserSGPRs(CCInfo, B, MF, *TRI, *Info);
483 TLI.allocateSpecialEntryInputVGPRs(CCInfo, M
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H A DSIISelLowering.h309 CCState &CCInfo,
410 void allocateHSAUserSGPRs(CCState &CCInfo,
415 void allocateSystemSGPRs(CCState &CCInfo,
421 void allocateSpecialEntryInputVGPRs(CCState &CCInfo,
426 CCState &CCInfo,
431 void allocateSpecialInputVGPRs(CCState &CCInfo,
H A DSIISelLowering.cpp108 static unsigned findFirstFreeSGPR(CCState &CCInfo) { argument
111 if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) {
1623 void SITargetLowering::allocateSpecialEntryInputVGPRs(CCState &CCInfo, argument
1634 CCInfo.AllocateReg(Reg);
1642 CCInfo.AllocateReg(Reg);
1650 CCInfo.AllocateReg(Reg);
1659 static ArgDescriptor allocateVGPR32Input(CCState &CCInfo, unsigned Mask = ~0u, argument
1666 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs);
1669 int64_t Offset = CCInfo.AllocateStack(4, 4);
1675 Reg = CCInfo
1684 allocateSGPR32InputImpl(CCState &CCInfo, const TargetRegisterClass *RC, unsigned NumArgRegs) argument
1701 allocateSGPR32Input(CCState &CCInfo) argument
1705 allocateSGPR64Input(CCState &CCInfo) argument
1709 allocateSpecialInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const argument
1730 allocateSpecialInputSGPRs( CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const argument
1767 allocateHSAUserSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const argument
1822 allocateSystemSGPRs(CCState &CCInfo, MachineFunction &MF, SIMachineFunctionInfo &Info, CallingConv::ID CallConv, bool IsShader) const argument
2436 passSpecialInputs( CallLoweringInfo &CLI, CCState &CCInfo, const SIMachineFunctionInfo &Info, SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, SmallVectorImpl<SDValue> &MemOpChains, SDValue Chain) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16ISelLowering.h35 const CCState &CCInfo, unsigned NextStackOffset,
H A DMipsCallLowering.cpp439 MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
441 CCInfo.AnalyzeReturn(Outs, TLI.CCAssignFnForReturn());
485 MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
491 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(F.getCallingConv()),
493 CCInfo.AnalyzeFormalArguments(Ins, TLI.CCAssignFnForCall());
502 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
507 VaArgOffset = alignTo(CCInfo.getNextStackOffset(), RegSize);
510 (int)ABI.GetCalleeAllocdArgSizeInBytes(CCInfo.getCallingConv()) -
611 MipsCCState CCInfo(F.getCallingConv(), IsCalleeVarArg, MF, ArgLocs,
614 CCInfo
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H A DMipsSEISelLowering.h64 const CCState &CCInfo, unsigned NextStackOffset,
H A DMipsISelLowering.cpp3164 MipsCCState CCInfo(
3204 CCInfo.AllocateStack(ReservedArgArea, 1);
3206 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(),
3210 unsigned NextStackOffset = CCInfo.getNextStackOffset();
3217 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
3250 CCInfo.rewindByValRegsInfo();
3263 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3264 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3268 assert(ByValIdx < CCInfo.getInRegsParamsCount());
3274 CCInfo
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H A DMipsFastISel.cpp1144 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1145 CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1147 NumBytes = CCInfo.getNextStackOffset();
1285 MipsCCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1287 CCInfo.AnalyzeCallResult(CLI.Ins, RetCC_Mips, CLI.RetTy,
1705 MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1708 CCInfo.AnalyzeReturn(Outs, RetCC);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp239 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
242 CCInfo.AnalyzeCallOperands(Outs, CC_ARC);
248 RetCCInfo.AllocateStack(CCInfo.getNextStackOffset(), 4);
457 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
460 CCInfo.AnalyzeFormalArguments(Ins, CC_ARC);
465 AFI->setReturnStackOffset(CCInfo.getNextStackOffset());
524 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs);
533 CCInfo.getNextStackOffset(), true);
596 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
597 if (!CCInfo
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h158 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
161 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
205 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
H A DRISCVISelLowering.cpp1665 MachineFunction &MF, CCState &CCInfo,
1682 ArgFlags, CCInfo, /*IsRet=*/true, IsRet, ArgTy)) {
1691 MachineFunction &MF, CCState &CCInfo,
1703 ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy)) {
1948 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1951 CCInfo.AnalyzeFormalArguments(Ins, CC_RISCV_FastCC);
1953 analyzeInputArgs(MF, CCInfo, Ins, /*IsRet=*/false);
1991 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
2005 VaArgOffset = CCInfo.getNextStackOffset();
2058 CCState &CCInfo, CallLoweringInf
1664 analyzeInputArgs( MachineFunction &MF, CCState &CCInfo, const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet) const argument
1690 analyzeOutputArgs( MachineFunction &MF, CCState &CCInfo, const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsRet, CallLoweringInfo *CLI) const argument
2057 isEligibleForTailCallOptimization( CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF, const SmallVector<CCValAssign, 16> &ArgLocs) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp177 CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
178 return handleAssignments(CCInfo, ArgLocs, MIRBuilder, Args, Handler);
181 bool CallLowering::handleAssignments(CCState &CCInfo, argument
194 Args[i].Flags[0], CCInfo)) {
222 Args[i].Flags[0], CCInfo))
249 Args[i], Args[i].Flags[Part], CCInfo)) {
282 Args[i], Args[i].Flags[PartIdx], CCInfo))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp938 CCState &CCInfo, bool IsCall, bool IsVarArg) {
948 CCInfo.AnalyzeCallOperands(*Outs, ArgCC_AVR_Vararg);
950 CCInfo.AnalyzeFormalArguments(*Ins, ArgCC_AVR_Vararg);
982 unsigned Reg = CCInfo.AllocateReg(
984 CCInfo.addLoc(
996 unsigned Offset = CCInfo.AllocateStack(
997 TD->getTypeAllocSize(EVT(LocVT).getTypeForEVT(CCInfo.getContext())),
999 EVT(LocVT).getTypeForEVT(CCInfo.getContext())));
1000 CCInfo.addLoc(CCValAssign::getMem(ValNo++, LocVT, Offset, LocVT,
1014 CCState &CCInfo, boo
932 analyzeStandardArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl<ISD::OutputArg> *Outs, const SmallVectorImpl<ISD::InputArg> *Ins, CallingConv::ID CallConv, SmallVectorImpl<CCValAssign> &ArgLocs, CCState &CCInfo, bool IsCall, bool IsVarArg) argument
1008 analyzeBuiltinArguments(TargetLowering::CallLoweringInfo &CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl<ISD::OutputArg> *Outs, const SmallVectorImpl<ISD::InputArg> *Ins, CallingConv::ID CallConv, SmallVectorImpl<CCValAssign> &ArgLocs, CCState &CCInfo, bool IsCall, bool IsVarArg) argument
1026 analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl<ISD::OutputArg> *Outs, const SmallVectorImpl<ISD::InputArg> *Ins, CallingConv::ID CallConv, SmallVectorImpl<CCValAssign> &ArgLocs, CCState &CCInfo, bool IsCall, bool IsVarArg) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp223 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
224 CCInfo.AnalyzeFormalArguments(Ins, getHasAlu32() ? CC_BPF32 : CC_BPF64);
301 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
303 CCInfo.AnalyzeCallOperands(Outs, getHasAlu32() ? CC_BPF32 : CC_BPF64);
305 unsigned NumBytes = CCInfo.getNextStackOffset();
419 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
427 CCInfo.AnalyzeReturn(Outs, getHasAlu32() ? RetCC_BPF32 : RetCC_BPF64);
462 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
471 CCInfo.AnalyzeCallResult(Ins, getHasAlu32() ? RetCC_BPF32 : RetCC_BPF64);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp448 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
451 CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32_Fast);
453 CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32);
526 int FI = MFI.CreateFixedObject(4, CCInfo.getNextStackOffset(), true);
543 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
547 CCInfo.AnalyzeReturn(Outs, RetCC_Lanai32);
604 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
616 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_VarArg);
619 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_Fast);
621 CCInfo
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1116 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1121 CCInfo.AllocateStack(4, 4);
1123 CCInfo.AnalyzeCallOperands(Outs, CC_XCore);
1129 RetCCInfo.AllocateStack(CCInfo.getNextStackOffset(), 4);
1271 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1274 CCInfo.AnalyzeFormalArguments(Ins, CC_XCore);
1281 XFI->setReturnStackOffset(CCInfo.getNextStackOffset() + LRSaveSize);
1350 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs);
1376 MFI.CreateFixedObject(4, LRSaveSize + CCInfo.getNextStackOffset(),
1428 CCState CCInfo(CallCon
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp629 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
631 AnalyzeArguments(CCInfo, ArgLocs, Ins);
635 unsigned Offset = CCInfo.getNextStackOffset();
730 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
731 return CCInfo.CheckReturn(Outs, RetCC_MSP430);
751 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
755 AnalyzeReturnValues(CCInfo, RVLocs, Outs);
812 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
814 AnalyzeArguments(CCInfo, ArgLocs, Outs);
817 unsigned NumBytes = CCInfo
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1383 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, *Context);
1387 CCInfo.AllocateStack(LinkageSize, 8);
1389 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS);
1408 NumBytes = CCInfo.getNextStackOffset();
1503 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1504 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1585 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context);
1586 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1707 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, *Context);
1708 CCInfo
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp182 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
185 return CCInfo.CheckReturn(Outs, RetCC_Hexagon_HVX);
186 return CCInfo.CheckReturn(Outs, RetCC_Hexagon);
202 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
207 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon_HVX);
209 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
326 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
330 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon_HVX);
332 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
398 HexagonCCState CCInfo(CallCon
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp219 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
223 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
302 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
306 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
393 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
395 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
539 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs);
541 unsigned ArgOffset = CCInfo.getNextStackOffset();
586 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
588 CCInfo
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallLowering.cpp391 CCState CCInfo(F.getCallingConv(), /*IsVarArg=*/true, MF, ArgLocs,
400 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, AssignFn);
404 if (!CCInfo.isAllocated(AArch64::X8)) {
H A DAArch64ISelLowering.cpp3341 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3371 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
3514 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
3518 unsigned StackOffset = CCInfo.getNextStackOffset();
3530 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes,
3534 if (!CCInfo.isAllocated(AArch64::X8)) {
3561 unsigned StackArgSize = CCInfo.getNextStackOffset();
3587 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo, argument
3603 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
3641 unsigned FirstVariadicFPR = CCInfo
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1896 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, ArgLocs, *Context);
1897 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
1943 NumBytes = CCInfo.getNextStackOffset();
2046 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2047 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2114 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext());
2115 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2218 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
2219 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2326 CCState CCInfo(C
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H A DARMISelLowering.h772 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
777 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Bitcode/Reader/
H A DBitcodeReader.cpp4475 unsigned CCInfo = Record[OpNum++]; local
4481 if ((CCInfo >> 13) & 1) {
4539 static_cast<CallingConv::ID>(CallingConv::MaxID & CCInfo));
4558 unsigned CCInfo = Record[OpNum++]; local
4568 if ((CCInfo >> bitc::CALL_EXPLICIT_TYPE) & 1) {
4626 static_cast<CallingConv::ID>((0x7ff & CCInfo) >> bitc::CALL_CCONV));
4997 unsigned CCInfo = Record[OpNum++]; local
5000 if ((CCInfo >> bitc::CALL_FMF) & 1) {
5008 if ((CCInfo >> bitc::CALL_EXPLICIT_TYPE) & 1) {
5069 static_cast<CallingConv::ID>((0x7ff & CCInfo) >> bit
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