Searched refs:BR_CC (Results 1 - 25 of 31) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.h29 BR_CC,
H A DBPFISelLowering.cpp71 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
108 setOperationAction(ISD::BR_CC, MVT::i32,
192 case ISD::BR_CC:
509 return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS,
541 case BPFISD::BR_CC:
542 return "BPFISD::BR_CC";
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.h49 // BR_CC - Used to glue together a conditional branch and comparison
50 BR_CC, enumerator in enum:llvm::LanaiISD::__anon2285
H A DLanaiISelLowering.cpp85 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
180 case ISD::BR_CC:
879 return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest,
1110 case LanaiISD::BR_CC:
1111 return "LanaiISD::BR_CC";
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h704 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
708 BR_CC, enumerator in enum:llvm::ISD::NodeType
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h60 BR_CC,
H A DMSP430ISelLowering.cpp90 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
91 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
349 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
1140 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
1383 case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp117 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
205 assert(LHS.getValueType() == MVT::i32 && "Only know how to BR_CC i32");
755 case ISD::BR_CC:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp96 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
97 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
98 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
99 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
697 case ISD::BR_CC:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp1037 case ISD::BR_CC: {
1042 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 :
3577 // Expand brcond's setcc into its constituent parts and create a BR_CC
3582 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3596 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3736 case ISD::BR_CC: {
3748 assert(Legalized && "Can't legalize BR_CC with legal condition!");
3750 assert(!NeedInvert && "Don't know how to invert BR_CC!");
3752 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3755 Tmp1 = DAG.getNode(ISD::BR_CC, d
[all...]
H A DSelectionDAGDumper.cpp359 case ISD::BR_CC: return "br_cc";
H A DLegalizeFloatTypes.cpp776 case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break;
1658 case ISD::BR_CC: Res = ExpandFloatOp_BR_CC(N); break;
1692 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
H A DLegalizeIntegerTypes.cpp1266 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
1359 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
3772 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
3814 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1534 // Sparc doesn't have BRCOND either, it has BR_CC.
1538 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1539 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1540 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1541 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
1562 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
3027 case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1455 // Expand BR_CC and SELECT_CC for all integer and fp types.
1457 setOperationAction(ISD::BR_CC, VT, Expand);
1461 setOperationAction(ISD::BR_CC, VT, Expand);
1464 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
1488 ISD::BR_CC, ISD::SELECT_CC, ISD::ConstantPool,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp102 setOperationAction(ISD::BR_CC, XLenVT, Expand);
174 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
191 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp223 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
224 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
225 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
226 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
227 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
277 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
437 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
472 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
499 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
726 setOperationAction(ISD::BR_CC, MV
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp401 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
402 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
403 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
404 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
H A DMipsSEISelLowering.cpp129 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp150 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
151 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
H A DSIISelLowering.cpp238 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
239 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
240 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
241 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
242 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
477 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
515 setOperationAction(ISD::BR_CC, MVT::f16, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp234 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp92 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp754 setTargetDAGCombine(ISD::BR_CC);
1316 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1318 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1319 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1320 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
9301 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
14305 assert(N->getOpcode() == ISD::BR_CC && "Expected BRCOND or BR_CC!");
14632 case ISD::BR_CC: return PerformHWLoopCombine(N, DCI, Subtarget);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp146 // Lower SELECT_CC and BR_CC into separate comparisons and branches.
148 setOperationAction(ISD::BR_CC, VT, Custom);
156 // Expand BRCOND into a BR_CC (see above).
5097 case ISD::BR_CC:

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