/freebsd-10.2-release/contrib/llvm/lib/Target/X86/InstPrinter/ |
H A D | X86InstComments.cpp | 38 DestName = getRegName(MI->getOperand(0).getReg()); 39 Src1Name = getRegName(MI->getOperand(1).getReg()); 40 Src2Name = getRegName(MI->getOperand(2).getReg()); 46 Src2Name = getRegName(MI->getOperand(2).getReg()); 47 Src1Name = getRegName(MI->getOperand(1).getReg()); 48 DestName = getRegName(MI->getOperand(0).getReg()); 54 Src2Name = getRegName(MI->getOperand(2).getReg()); 55 Src1Name = getRegName(MI->getOperand(1).getReg()); 56 DestName = getRegName(MI->getOperand(0).getReg()); 62 Src1Name = getRegName(MI->getOperand(2).getReg()); [all...] |
H A D | X86ATTInstPrinter.cpp | 155 printRegName(O, Op.getReg()); 183 if (SegReg.getReg()) { 190 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) 197 if (IndexReg.getReg() || BaseReg.getReg()) { 199 if (BaseReg.getReg()) 202 if (IndexReg.getReg()) {
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/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMFeatures.h | 73 return Instr->getOperand(2).getReg() != ARM::PC; 78 return Instr->getOperand(0).getReg() != ARM::PC; 80 return Instr->getOperand(BLXOperandIndex).getReg() != ARM::PC; 82 return Instr->getOperand(0).getReg() != ARM::PC && 83 Instr->getOperand(2).getReg() != ARM::PC; 86 return Instr->getOperand(0).getReg() != ARM::PC && 87 Instr->getOperand(1).getReg() != ARM::PC;
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H A D | A15SDOptimizer.cpp | 143 unsigned Reg = MO.getReg(); 173 SReg = MI->getOperand(1).getReg(); 202 unsigned Reg = MO.getReg(); 225 unsigned DefReg = MODef.getReg(); 255 return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg()); 259 unsigned DPRReg = MI->getOperand(1).getReg(); 260 unsigned SPRReg = MI->getOperand(2).getReg(); 263 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg()); 264 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg()); 281 unsigned FullReg = SPRMI->getOperand(1).getReg(); [all...] |
H A D | MLxExpansionPass.cpp | 89 unsigned Reg = MI->getOperand(1).getReg(); 99 Reg = DefMI->getOperand(1).getReg(); 105 Reg = DefMI->getOperand(2).getReg(); 117 unsigned Reg = MI->getOperand(0).getReg(); 128 Reg = UseMI->getOperand(0).getReg(); 143 unsigned Reg = MI->getOperand(1).getReg(); 157 unsigned SrcReg = DefMI->getOperand(i).getReg(); 165 Reg = DefMI->getOperand(1).getReg(); 171 Reg = DefMI->getOperand(2).getReg(); 274 unsigned DstReg = MI->getOperand(0).getReg(); [all...] |
H A D | ARMAsmPrinter.cpp | 63 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1) { 69 unsigned Reg = MLoc.getReg(); 175 unsigned Reg = MO.getReg(); 263 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg()) 279 unsigned Reg = MI->getOperand(OpNum).getReg(); 306 unsigned RegBegin = MO.getReg(); 326 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg()); 369 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ? 382 unsigned Reg = MO.getReg(); 391 unsigned Reg = MI->getOperand(OpNum).getReg(); [all...] |
/freebsd-10.2-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonSplitTFRCondSets.cpp | 97 int DestReg = MI->getOperand(0).getReg(); 98 int SrcReg1 = MI->getOperand(2).getReg(); 99 int SrcReg2 = MI->getOperand(3).getReg(); 115 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); 119 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); 127 int DestReg = MI->getOperand(0).getReg(); 128 int SrcReg1 = MI->getOperand(2).getReg(); 135 addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); 140 addReg(MI->getOperand(1).getReg()). 145 addReg(MI->getOperand(1).getReg()) [all...] |
H A D | HexagonPeephole.cpp | 141 unsigned DstReg = Dst.getReg(); 142 unsigned SrcReg = Src.getReg(); 163 unsigned DstReg = Dst.getReg(); 164 unsigned SrcReg = Src2.getReg(); 180 unsigned DstReg = Dst.getReg(); 181 unsigned SrcReg = Src1.getReg(); 192 unsigned DstReg = Dst.getReg(); 193 unsigned SrcReg = Src.getReg(); 215 unsigned DstReg = Dst.getReg(); 216 unsigned SrcReg = Src.getReg(); [all...] |
H A D | HexagonSplitConst32AndConst64.cpp | 83 int DestReg = MI->getOperand(0).getReg(); 96 int DestReg = MI->getOperand(0).getReg(); 109 int DestReg = MI->getOperand(0).getReg(); 122 int DestReg = MI->getOperand(0).getReg(); 133 int DestReg = MI->getOperand(0).getReg();
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H A D | HexagonHardwareLoops.cpp | 255 unsigned getReg() const { function in class:__anon2502::CountValue 354 unsigned PhiOpReg = Phi->getOperand(i).getReg(); 362 unsigned IndReg = DI->getOperand(1).getReg(); 364 unsigned UpdReg = DI->getOperand(0).getReg(); 380 unsigned PredR = Cond[CSz-1].getReg(); 475 IVReg = IV_Phi->getOperand(i).getReg(); // Want IV reg after bump. 500 unsigned PredReg = Cond[Cond.size()-1].getReg(); 528 if (Op2.isImm() || Op1.getReg() == IVReg) 565 if (!defWithImmediate(InitialValue->getReg())) 592 unsigned R = InitialValue->getReg(); [all...] |
H A D | HexagonCopyToCombine.cpp | 122 unsigned DestReg = MI->getOperand(0).getReg(); 123 unsigned SrcReg = MI->getOperand(1).getReg(); 132 unsigned DestReg = MI->getOperand(0).getReg(); 150 unsigned DestReg = MI->getOperand(0).getReg(); 214 if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill()) 241 unsigned I2UseReg = IsImmUseReg ? 0 : I2->getOperand(1).getReg(); 306 unsigned I1UseReg = IsImmUseReg ? 0 : I1->getOperand(1).getReg(); 371 if (!Op.isReg() || !Op.isUse() || !Op.getReg()) 375 unsigned Reg = Op.getReg(); 401 if (!Op.isReg() || !Op.isDef() || !Op.getReg()) [all...] |
H A D | HexagonVLIWPacketizer.cpp | 356 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) { 485 DefRegsSet[MI->getOperand(opNum).getReg()] = 1; 491 if (DefRegsSet[MI->getOperand(opNum).getReg()]) { 548 GetStoreValueOperand(MI).getReg() != DepReg) 582 GetPostIncrementOperand(MI, QII).getReg() == DepReg) { 588 GetPostIncrementOperand(PacketMI, QII).getReg() == DepReg) { 612 predRegNumSrc = PacketMI->getOperand(opNum).getReg(); 624 predRegNumDst = MI->getOperand(opNum).getReg(); 678 TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(), 692 GetStoreValueOperand(MI).getReg() [all...] |
/freebsd-10.2-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZAsmPrinter.cpp | 34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) 38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) 39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) 48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) 52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) 53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) 61 .addReg(MI->getOperand(0).getReg()) 62 .addReg(MI->getOperand(1).getReg()) 63 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) 86 .addReg(MI->getOperand(0).getReg()); [all...] |
/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 121 printRegName(O, Dst.getReg()); 123 printRegName(O, MO1.getReg()); 126 printRegName(O, MO2.getReg()); 143 printRegName(O, Dst.getReg()); 145 printRegName(O, MO1.getReg()); 163 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { 177 if (MI->getOperand(2).getReg() == ARM::SP && 182 printRegName(O, MI->getOperand(1).getReg()); 192 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { 206 if (MI->getOperand(2).getReg() [all...] |
/freebsd-10.2-release/contrib/llvm/lib/Target/MSP430/InstPrinter/ |
H A D | MSP430InstPrinter.cpp | 50 O << getRegisterName(Op.getReg()); 73 if (!Base.getReg()) 84 if (Base.getReg()) 85 O << '(' << getRegisterName(Base.getReg()) << ')';
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/freebsd-10.2-release/contrib/llvm/lib/Target/R600/ |
H A D | R600ExpandSpecialInstrs.cpp | 77 DstOp.getReg(), AMDGPU::OQAP); 85 MI.getOperand(LDSPredSelIdx).getReg()); 97 MI.getOperand(0).getReg(), // dst 98 MI.getOperand(1).getReg(), // src0 119 DstReg = MI.getOperand(Chan).getReg(); 124 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); 150 DstReg = MI.getOperand(Chan-2).getReg(); 153 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); 173 unsigned DstReg = MI.getOperand(0).getReg(); 192 unsigned DstReg = MI.getOperand(0).getReg(); [all...] |
H A D | SIFixSGPRCopies.cpp | 120 !TargetRegisterInfo::isVirtualRegister(MI.getOperand(i).getReg())) 123 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) 149 I->getOperand(0).getReg(), 172 return inferRegClassFromDef(TRI, MRI, Def->getOperand(1).getReg(), 180 unsigned DstReg = Copy.getOperand(0).getReg(); 181 unsigned SrcReg = Copy.getOperand(1).getReg(); 221 unsigned Reg = MI.getOperand(i).getReg(); 226 unsigned Reg = MI.getOperand(0).getReg(); 239 unsigned Reg = MI.getOperand(i).getReg();
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H A D | SILowerControlFlow.cpp | 197 unsigned Reg = MI.getOperand(0).getReg(); 198 unsigned Vcc = MI.getOperand(1).getReg(); 215 unsigned Dst = MI.getOperand(0).getReg(); 216 unsigned Src = MI.getOperand(1).getReg(); 235 unsigned Dst = MI.getOperand(0).getReg(); 236 unsigned Src = MI.getOperand(1).getReg(); 249 unsigned Dst = MI.getOperand(0).getReg(); 250 unsigned Vcc = MI.getOperand(1).getReg(); 251 unsigned Src = MI.getOperand(2).getReg(); 264 unsigned Dst = MI.getOperand(0).getReg(); [all...] |
/freebsd-10.2-release/contrib/llvm/lib/CodeGen/ |
H A D | OptimizePHIs.cpp | 87 unsigned DstReg = MI->getOperand(0).getReg(); 99 unsigned SrcReg = MI->getOperand(i).getReg(); 108 TargetRegisterInfo::isVirtualRegister(SrcMI->getOperand(1).getReg())) 109 SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg()); 130 unsigned DstReg = MI->getOperand(0).getReg(); 167 unsigned OldReg = MI->getOperand(0).getReg();
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H A D | LiveRegUnits.cpp | 54 unsigned Reg = O->getReg(); 66 unsigned Reg = O->getReg(); 82 unsigned Reg = O->getReg();
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H A D | ExpandPostRAPseudos.cpp | 74 CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true)); 85 unsigned DstReg = MI->getOperand(0).getReg(); 86 unsigned InsReg = MI->getOperand(2).getReg(); 147 if (SrcMO.getReg() == DstMO.getReg()) { 165 DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
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/freebsd-10.2-release/contrib/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 56 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7; 70 unsigned SrcReg = MI.getOperand(OpNum).getReg(); 82 assert(X86::K0 != MI.getOperand(OpNum).getReg() && 224 if ((BaseReg.getReg() != 0 && 225 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || 226 (IndexReg.getReg() != 0 && 227 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) 239 if ((BaseReg.getReg() != 0 && 240 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || 241 (IndexReg.getReg() ! [all...] |
/freebsd-10.2-release/contrib/llvm/lib/Target/Sparc/ |
H A D | DelaySlotFiller.cpp | 261 unsigned Reg = MO.getReg(); 294 RegUses.insert(Reg.getReg()); 301 RegUses.insert(RegOrImm.getReg()); 316 unsigned Reg = MO.getReg(); 372 unsigned reg = AddMI->getOperand(0).getReg(); 400 unsigned reg = OrMI->getOperand(0).getReg(); 406 && OrMI->getOperand(1).getReg() != SP::G0 407 && OrMI->getOperand(2).getReg() != SP::G0) 411 && OrMI->getOperand(1).getReg() != SP::G0 438 unsigned reg = SetHiMI->getOperand(0).getReg(); [all...] |
/freebsd-10.2-release/contrib/llvm/lib/Target/X86/ |
H A D | X86CodeEmitter.cpp | 182 unsigned Reg = MO.getReg(); 484 unsigned BaseReg = Base.getReg(); 489 assert(IndexReg.getReg() == 0 && Is64BitMode && 510 IndexReg.getReg() == 0 && 548 assert(IndexReg.getReg() != X86::ESP && 549 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 582 if (IndexReg.getReg()) 583 IndexRegNo = getX86RegNum(IndexReg.getReg()); 590 if (IndexReg.getReg()) 591 IndexRegNo = getX86RegNum(IndexReg.getReg()); [all...] |
/freebsd-10.2-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64AsmPrinter.cpp | 39 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) { 41 O << RegType << TRI->getEncodingValue(MO.getReg()); 62 if (MO.getReg() == AArch64::XSP || MO.getReg() == AArch64::WSP) { 67 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) { 229 O << AArch64InstPrinter::getRegisterName(MO.getReg()); 258 O << '[' << AArch64InstPrinter::getRegisterName(MO.getReg()) << ']';
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