X86/MCTargetDesc/X86MCCodeEmitter.cpp

56     return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
70     unsigned SrcReg = MI.getOperand(OpNum).getReg();
82     assert(X86::K0 != MI.getOperand(OpNum).getReg() &&
224   if ((BaseReg.getReg() != 0 &&
225        X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
226       (IndexReg.getReg() != 0 &&
227        X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
239   if ((BaseReg.getReg() != 0 &&
240        X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
241       (IndexReg.getReg() != 0 &&
242        X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
254   if ((BaseReg.getReg() != 0 &&
255        X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
256       (IndexReg.getReg() != 0 &&
257        X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
374   unsigned BaseReg = Base.getReg();
380     assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
411       IndexReg.getReg() == 0 &&
461   assert(IndexReg.getReg() != X86::ESP &&
462          IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
505     if (IndexReg.getReg())
512     if (IndexReg.getReg())
705                                                  X86::AddrBaseReg).getReg()))
708                                                  X86::AddrIndexReg).getReg()))
711                                           X86::AddrIndexReg).getReg()))
721       if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
728       if (X86II::isX86_64ExtendedReg(MO.getReg()))
730       if (HasEVEX && X86II::is32ExtendedReg(MO.getReg()))
745     if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
747     if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
756       if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
762                MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
765                MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
768                                           X86::AddrIndexReg).getReg()))
788       if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
797                MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
800                MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
813     if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
815     if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
824       if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
832     if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
834     if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
845     if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
847     if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
856       if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
861     if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
863     if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
874       if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
881     if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
883     if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
968     unsigned Reg = MO.getReg();
980         X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
985       if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
991         X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
998         if (X86II::isX86_64ExtendedReg(MO.getReg()))
1013         X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
1019         if (X86II::isX86_64ExtendedReg(MO.getReg()))
1028         X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
1033       if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
1051       switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
1420       if (X86II::isX86_64ExtendedReg(MO.getReg()))