1234353Sdim//===-- X86CodeEmitter.cpp - Convert X86 code to machine code -------------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file contains the pass that transforms the X86 machine instructions into 11193323Sed// relocatable machine code. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15193323Sed#define DEBUG_TYPE "x86-emitter" 16249423Sdim#include "X86.h" 17193323Sed#include "X86InstrInfo.h" 18193323Sed#include "X86JITInfo.h" 19249423Sdim#include "X86Relocations.h" 20193323Sed#include "X86Subtarget.h" 21193323Sed#include "X86TargetMachine.h" 22249423Sdim#include "llvm/ADT/Statistic.h" 23193323Sed#include "llvm/CodeGen/JITCodeEmitter.h" 24193323Sed#include "llvm/CodeGen/MachineFunctionPass.h" 25193323Sed#include "llvm/CodeGen/MachineInstr.h" 26193323Sed#include "llvm/CodeGen/MachineModuleInfo.h" 27193323Sed#include "llvm/CodeGen/Passes.h" 28249423Sdim#include "llvm/IR/LLVMContext.h" 29198090Srdivacky#include "llvm/MC/MCCodeEmitter.h" 30198090Srdivacky#include "llvm/MC/MCExpr.h" 31198090Srdivacky#include "llvm/MC/MCInst.h" 32249423Sdim#include "llvm/PassManager.h" 33193323Sed#include "llvm/Support/Debug.h" 34198090Srdivacky#include "llvm/Support/ErrorHandling.h" 35198090Srdivacky#include "llvm/Support/raw_ostream.h" 36193323Sed#include "llvm/Target/TargetOptions.h" 37193323Sedusing namespace llvm; 38193323Sed 39193323SedSTATISTIC(NumEmitted, "Number of machine instructions emitted"); 40193323Sed 41193323Sednamespace { 42198090Srdivacky template<class CodeEmitter> 43198892Srdivacky class Emitter : public MachineFunctionPass { 44193323Sed const X86InstrInfo *II; 45243830Sdim const DataLayout *TD; 46193323Sed X86TargetMachine &TM; 47193323Sed CodeEmitter &MCE; 48205218Srdivacky MachineModuleInfo *MMI; 49193323Sed intptr_t PICBaseOffset; 50193323Sed bool Is64BitMode; 51193323Sed bool IsPIC; 52193323Sed public: 53193323Sed static char ID; 54193323Sed explicit Emitter(X86TargetMachine &tm, CodeEmitter &mce) 55239462Sdim : MachineFunctionPass(ID), II(0), TD(0), TM(tm), 56263508Sdim MCE(mce), PICBaseOffset(0), Is64BitMode(false), 57263508Sdim IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} 58193323Sed 59193323Sed bool runOnMachineFunction(MachineFunction &MF); 60193323Sed 61193323Sed virtual const char *getPassName() const { 62193323Sed return "X86 Machine Code Emitter"; 63193323Sed } 64193323Sed 65239462Sdim void emitOpcodePrefix(uint64_t TSFlags, int MemOperand, 66239462Sdim const MachineInstr &MI, 67239462Sdim const MCInstrDesc *Desc) const; 68239462Sdim 69239462Sdim void emitVEXOpcodePrefix(uint64_t TSFlags, int MemOperand, 70239462Sdim const MachineInstr &MI, 71239462Sdim const MCInstrDesc *Desc) const; 72239462Sdim 73239462Sdim void emitSegmentOverridePrefix(uint64_t TSFlags, 74239462Sdim int MemOperand, 75239462Sdim const MachineInstr &MI) const; 76239462Sdim 77224145Sdim void emitInstruction(MachineInstr &MI, const MCInstrDesc *Desc); 78239462Sdim 79193323Sed void getAnalysisUsage(AnalysisUsage &AU) const { 80198090Srdivacky AU.setPreservesAll(); 81193323Sed AU.addRequired<MachineModuleInfo>(); 82193323Sed MachineFunctionPass::getAnalysisUsage(AU); 83193323Sed } 84193323Sed 85193323Sed private: 86193323Sed void emitPCRelativeBlockAddress(MachineBasicBlock *MBB); 87207618Srdivacky void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 88193323Sed intptr_t Disp = 0, intptr_t PCAdj = 0, 89199481Srdivacky bool Indirect = false); 90193323Sed void emitExternalSymbolAddress(const char *ES, unsigned Reloc); 91193323Sed void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0, 92193323Sed intptr_t PCAdj = 0); 93193323Sed void emitJumpTableAddress(unsigned JTI, unsigned Reloc, 94193323Sed intptr_t PCAdj = 0); 95193323Sed 96193323Sed void emitDisplacementField(const MachineOperand *RelocOp, int DispVal, 97198090Srdivacky intptr_t Adj = 0, bool IsPCRel = true); 98193323Sed 99193323Sed void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField); 100193323Sed void emitRegModRMByte(unsigned RegOpcodeField); 101193323Sed void emitSIBByte(unsigned SS, unsigned Index, unsigned Base); 102193323Sed void emitConstant(uint64_t Val, unsigned Size); 103193323Sed 104193323Sed void emitMemModRMByte(const MachineInstr &MI, 105193323Sed unsigned Op, unsigned RegOpcodeField, 106193323Sed intptr_t PCAdj = 0); 107243830Sdim 108243830Sdim unsigned getX86RegNum(unsigned RegNo) const { 109243830Sdim const TargetRegisterInfo *TRI = TM.getRegisterInfo(); 110243830Sdim return TRI->getEncodingValue(RegNo) & 0x7; 111243830Sdim } 112243830Sdim 113243830Sdim unsigned char getVEXRegisterEncoding(const MachineInstr &MI, 114243830Sdim unsigned OpNum) const; 115193323Sed }; 116193323Sed 117193323Sedtemplate<class CodeEmitter> 118193323Sed char Emitter<CodeEmitter>::ID = 0; 119198090Srdivacky} // end anonymous namespace. 120193323Sed 121193323Sed/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code 122249423Sdim/// to the specified JITCodeEmitter object. 123198090SrdivackyFunctionPass *llvm::createX86JITCodeEmitterPass(X86TargetMachine &TM, 124198090Srdivacky JITCodeEmitter &JCE) { 125193323Sed return new Emitter<JITCodeEmitter>(TM, JCE); 126193323Sed} 127193323Sed 128193323Sedtemplate<class CodeEmitter> 129193323Sedbool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) { 130205218Srdivacky MMI = &getAnalysis<MachineModuleInfo>(); 131205218Srdivacky MCE.setModuleInfo(MMI); 132239462Sdim 133193323Sed II = TM.getInstrInfo(); 134243830Sdim TD = TM.getDataLayout(); 135193323Sed Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit(); 136193323Sed IsPIC = TM.getRelocationModel() == Reloc::PIC_; 137239462Sdim 138193323Sed do { 139243830Sdim DEBUG(dbgs() << "JITTing function '" << MF.getName() << "'\n"); 140193323Sed MCE.startFunction(MF); 141239462Sdim for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 142193323Sed MBB != E; ++MBB) { 143193323Sed MCE.StartMachineBasicBlock(MBB); 144218893Sdim for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); 145193323Sed I != E; ++I) { 146224145Sdim const MCInstrDesc &Desc = I->getDesc(); 147193323Sed emitInstruction(*I, &Desc); 148193323Sed // MOVPC32r is basically a call plus a pop instruction. 149193323Sed if (Desc.getOpcode() == X86::MOVPC32r) 150193323Sed emitInstruction(*I, &II->get(X86::POP32r)); 151210299Sed ++NumEmitted; // Keep track of the # of mi's emitted 152193323Sed } 153193323Sed } 154193323Sed } while (MCE.finishFunction(MF)); 155193323Sed 156193323Sed return false; 157193323Sed} 158193323Sed 159212904Sdim/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64 160212904Sdim/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand 161212904Sdim/// size, and 3) use of X86-64 extended registers. 162212904Sdimstatic unsigned determineREX(const MachineInstr &MI) { 163212904Sdim unsigned REX = 0; 164224145Sdim const MCInstrDesc &Desc = MI.getDesc(); 165239462Sdim 166212904Sdim // Pseudo instructions do not need REX prefix byte. 167212904Sdim if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo) 168212904Sdim return 0; 169212904Sdim if (Desc.TSFlags & X86II::REX_W) 170212904Sdim REX |= 1 << 3; 171239462Sdim 172212904Sdim unsigned NumOps = Desc.getNumOperands(); 173212904Sdim if (NumOps) { 174212904Sdim bool isTwoAddr = NumOps > 1 && 175239462Sdim Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1; 176239462Sdim 177212904Sdim // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 178212904Sdim unsigned i = isTwoAddr ? 1 : 0; 179212904Sdim for (unsigned e = NumOps; i != e; ++i) { 180212904Sdim const MachineOperand& MO = MI.getOperand(i); 181212904Sdim if (MO.isReg()) { 182212904Sdim unsigned Reg = MO.getReg(); 183226633Sdim if (X86II::isX86_64NonExtLowByteReg(Reg)) 184212904Sdim REX |= 0x40; 185212904Sdim } 186212904Sdim } 187239462Sdim 188212904Sdim switch (Desc.TSFlags & X86II::FormMask) { 189212904Sdim case X86II::MRMInitReg: 190212904Sdim if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0))) 191212904Sdim REX |= (1 << 0) | (1 << 2); 192212904Sdim break; 193212904Sdim case X86II::MRMSrcReg: { 194212904Sdim if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0))) 195212904Sdim REX |= 1 << 2; 196212904Sdim i = isTwoAddr ? 2 : 1; 197212904Sdim for (unsigned e = NumOps; i != e; ++i) { 198212904Sdim const MachineOperand& MO = MI.getOperand(i); 199212904Sdim if (X86InstrInfo::isX86_64ExtendedReg(MO)) 200212904Sdim REX |= 1 << 0; 201212904Sdim } 202212904Sdim break; 203212904Sdim } 204212904Sdim case X86II::MRMSrcMem: { 205212904Sdim if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0))) 206212904Sdim REX |= 1 << 2; 207212904Sdim unsigned Bit = 0; 208212904Sdim i = isTwoAddr ? 2 : 1; 209212904Sdim for (; i != NumOps; ++i) { 210212904Sdim const MachineOperand& MO = MI.getOperand(i); 211212904Sdim if (MO.isReg()) { 212212904Sdim if (X86InstrInfo::isX86_64ExtendedReg(MO)) 213212904Sdim REX |= 1 << Bit; 214212904Sdim Bit++; 215212904Sdim } 216212904Sdim } 217212904Sdim break; 218212904Sdim } 219212904Sdim case X86II::MRM0m: case X86II::MRM1m: 220212904Sdim case X86II::MRM2m: case X86II::MRM3m: 221212904Sdim case X86II::MRM4m: case X86II::MRM5m: 222212904Sdim case X86II::MRM6m: case X86II::MRM7m: 223212904Sdim case X86II::MRMDestMem: { 224212904Sdim unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands); 225212904Sdim i = isTwoAddr ? 1 : 0; 226212904Sdim if (NumOps > e && X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e))) 227212904Sdim REX |= 1 << 2; 228212904Sdim unsigned Bit = 0; 229212904Sdim for (; i != e; ++i) { 230212904Sdim const MachineOperand& MO = MI.getOperand(i); 231212904Sdim if (MO.isReg()) { 232212904Sdim if (X86InstrInfo::isX86_64ExtendedReg(MO)) 233212904Sdim REX |= 1 << Bit; 234212904Sdim Bit++; 235212904Sdim } 236212904Sdim } 237212904Sdim break; 238212904Sdim } 239212904Sdim default: { 240212904Sdim if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0))) 241212904Sdim REX |= 1 << 0; 242212904Sdim i = isTwoAddr ? 2 : 1; 243212904Sdim for (unsigned e = NumOps; i != e; ++i) { 244212904Sdim const MachineOperand& MO = MI.getOperand(i); 245212904Sdim if (X86InstrInfo::isX86_64ExtendedReg(MO)) 246212904Sdim REX |= 1 << 2; 247212904Sdim } 248212904Sdim break; 249212904Sdim } 250212904Sdim } 251212904Sdim } 252212904Sdim return REX; 253212904Sdim} 254212904Sdim 255212904Sdim 256193323Sed/// emitPCRelativeBlockAddress - This method keeps track of the information 257193323Sed/// necessary to resolve the address of this block later and emits a dummy 258193323Sed/// value. 259193323Sed/// 260193323Sedtemplate<class CodeEmitter> 261193323Sedvoid Emitter<CodeEmitter>::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) { 262193323Sed // Remember where this reference was and where it is to so we can 263193323Sed // deal with it later. 264193323Sed MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), 265193323Sed X86::reloc_pcrel_word, MBB)); 266193323Sed MCE.emitWordLE(0); 267193323Sed} 268193323Sed 269193323Sed/// emitGlobalAddress - Emit the specified address to the code stream assuming 270193323Sed/// this is part of a "take the address of a global" instruction. 271193323Sed/// 272193323Sedtemplate<class CodeEmitter> 273207618Srdivackyvoid Emitter<CodeEmitter>::emitGlobalAddress(const GlobalValue *GV, 274207618Srdivacky unsigned Reloc, 275193323Sed intptr_t Disp /* = 0 */, 276193323Sed intptr_t PCAdj /* = 0 */, 277193323Sed bool Indirect /* = false */) { 278198090Srdivacky intptr_t RelocCST = Disp; 279193323Sed if (Reloc == X86::reloc_picrel_word) 280193323Sed RelocCST = PICBaseOffset; 281193323Sed else if (Reloc == X86::reloc_pcrel_word) 282193323Sed RelocCST = PCAdj; 283193323Sed MachineRelocation MR = Indirect 284193323Sed ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc, 285207618Srdivacky const_cast<GlobalValue *>(GV), 286207618Srdivacky RelocCST, false) 287193323Sed : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, 288207618Srdivacky const_cast<GlobalValue *>(GV), RelocCST, false); 289193323Sed MCE.addRelocation(MR); 290193323Sed // The relocated value will be added to the displacement 291193323Sed if (Reloc == X86::reloc_absolute_dword) 292193323Sed MCE.emitDWordLE(Disp); 293193323Sed else 294193323Sed MCE.emitWordLE((int32_t)Disp); 295193323Sed} 296193323Sed 297193323Sed/// emitExternalSymbolAddress - Arrange for the address of an external symbol to 298193323Sed/// be emitted to the current location in the function, and allow it to be PC 299193323Sed/// relative. 300193323Sedtemplate<class CodeEmitter> 301193323Sedvoid Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES, 302193323Sed unsigned Reloc) { 303193323Sed intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0; 304203954Srdivacky 305203954Srdivacky // X86 never needs stubs because instruction selection will always pick 306203954Srdivacky // an instruction sequence that is large enough to hold any address 307203954Srdivacky // to a symbol. 308203954Srdivacky // (see X86ISelLowering.cpp, near 2039: X86TargetLowering::LowerCall) 309203954Srdivacky bool NeedStub = false; 310193323Sed MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 311203954Srdivacky Reloc, ES, RelocCST, 312203954Srdivacky 0, NeedStub)); 313193323Sed if (Reloc == X86::reloc_absolute_dword) 314193323Sed MCE.emitDWordLE(0); 315193323Sed else 316193323Sed MCE.emitWordLE(0); 317193323Sed} 318193323Sed 319193323Sed/// emitConstPoolAddress - Arrange for the address of an constant pool 320193323Sed/// to be emitted to the current location in the function, and allow it to be PC 321193323Sed/// relative. 322193323Sedtemplate<class CodeEmitter> 323193323Sedvoid Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc, 324193323Sed intptr_t Disp /* = 0 */, 325193323Sed intptr_t PCAdj /* = 0 */) { 326193323Sed intptr_t RelocCST = 0; 327193323Sed if (Reloc == X86::reloc_picrel_word) 328193323Sed RelocCST = PICBaseOffset; 329193323Sed else if (Reloc == X86::reloc_pcrel_word) 330193323Sed RelocCST = PCAdj; 331193323Sed MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 332193323Sed Reloc, CPI, RelocCST)); 333193323Sed // The relocated value will be added to the displacement 334193323Sed if (Reloc == X86::reloc_absolute_dword) 335193323Sed MCE.emitDWordLE(Disp); 336193323Sed else 337193323Sed MCE.emitWordLE((int32_t)Disp); 338193323Sed} 339193323Sed 340193323Sed/// emitJumpTableAddress - Arrange for the address of a jump table to 341193323Sed/// be emitted to the current location in the function, and allow it to be PC 342193323Sed/// relative. 343193323Sedtemplate<class CodeEmitter> 344193323Sedvoid Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTI, unsigned Reloc, 345193323Sed intptr_t PCAdj /* = 0 */) { 346193323Sed intptr_t RelocCST = 0; 347193323Sed if (Reloc == X86::reloc_picrel_word) 348193323Sed RelocCST = PICBaseOffset; 349193323Sed else if (Reloc == X86::reloc_pcrel_word) 350193323Sed RelocCST = PCAdj; 351193323Sed MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 352193323Sed Reloc, JTI, RelocCST)); 353193323Sed // The relocated value will be added to the displacement 354193323Sed if (Reloc == X86::reloc_absolute_dword) 355193323Sed MCE.emitDWordLE(0); 356193323Sed else 357193323Sed MCE.emitWordLE(0); 358193323Sed} 359193323Sed 360193323Sedinline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode, 361193323Sed unsigned RM) { 362193323Sed assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!"); 363193323Sed return RM | (RegOpcode << 3) | (Mod << 6); 364193323Sed} 365193323Sed 366193323Sedtemplate<class CodeEmitter> 367193323Sedvoid Emitter<CodeEmitter>::emitRegModRMByte(unsigned ModRMReg, 368193323Sed unsigned RegOpcodeFld){ 369243830Sdim MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg))); 370193323Sed} 371193323Sed 372193323Sedtemplate<class CodeEmitter> 373193323Sedvoid Emitter<CodeEmitter>::emitRegModRMByte(unsigned RegOpcodeFld) { 374193323Sed MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0)); 375193323Sed} 376193323Sed 377193323Sedtemplate<class CodeEmitter> 378239462Sdimvoid Emitter<CodeEmitter>::emitSIBByte(unsigned SS, 379193323Sed unsigned Index, 380193323Sed unsigned Base) { 381193323Sed // SIB byte is in the same format as the ModRMByte... 382193323Sed MCE.emitByte(ModRMByte(SS, Index, Base)); 383193323Sed} 384193323Sed 385193323Sedtemplate<class CodeEmitter> 386193323Sedvoid Emitter<CodeEmitter>::emitConstant(uint64_t Val, unsigned Size) { 387193323Sed // Output the constant in little endian byte order... 388193323Sed for (unsigned i = 0; i != Size; ++i) { 389193323Sed MCE.emitByte(Val & 255); 390193323Sed Val >>= 8; 391193323Sed } 392193323Sed} 393193323Sed 394239462Sdim/// isDisp8 - Return true if this signed displacement fits in a 8-bit 395239462Sdim/// sign-extended field. 396193323Sedstatic bool isDisp8(int Value) { 397193323Sed return Value == (signed char)Value; 398193323Sed} 399193323Sed 400198090Srdivackystatic bool gvNeedsNonLazyPtr(const MachineOperand &GVOp, 401198090Srdivacky const TargetMachine &TM) { 402198090Srdivacky // For Darwin-64, simulate the linktime GOT by using the same non-lazy-pointer 403193323Sed // mechanism as 32-bit mode. 404239462Sdim if (TM.getSubtarget<X86Subtarget>().is64Bit() && 405198090Srdivacky !TM.getSubtarget<X86Subtarget>().isTargetDarwin()) 406198090Srdivacky return false; 407239462Sdim 408198090Srdivacky // Return true if this is a reference to a stub containing the address of the 409198090Srdivacky // global, not the global itself. 410198090Srdivacky return isGlobalStubReference(GVOp.getTargetFlags()); 411193323Sed} 412193323Sed 413193323Sedtemplate<class CodeEmitter> 414193323Sedvoid Emitter<CodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp, 415198090Srdivacky int DispVal, 416198090Srdivacky intptr_t Adj /* = 0 */, 417198090Srdivacky bool IsPCRel /* = true */) { 418193323Sed // If this is a simple integer displacement that doesn't require a relocation, 419193323Sed // emit it now. 420193323Sed if (!RelocOp) { 421193323Sed emitConstant(DispVal, 4); 422193323Sed return; 423193323Sed } 424198090Srdivacky 425193323Sed // Otherwise, this is something that requires a relocation. Emit it as such 426193323Sed // now. 427198090Srdivacky unsigned RelocType = Is64BitMode ? 428198090Srdivacky (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext) 429198090Srdivacky : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); 430193323Sed if (RelocOp->isGlobal()) { 431193323Sed // In 64-bit static small code model, we could potentially emit absolute. 432198090Srdivacky // But it's probably not beneficial. If the MCE supports using RIP directly 433239462Sdim // do it, otherwise fallback to absolute (this is determined by IsPCRel). 434193323Sed // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative 435193323Sed // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute 436198090Srdivacky bool Indirect = gvNeedsNonLazyPtr(*RelocOp, TM); 437198090Srdivacky emitGlobalAddress(RelocOp->getGlobal(), RelocType, RelocOp->getOffset(), 438199481Srdivacky Adj, Indirect); 439198090Srdivacky } else if (RelocOp->isSymbol()) { 440198090Srdivacky emitExternalSymbolAddress(RelocOp->getSymbolName(), RelocType); 441193323Sed } else if (RelocOp->isCPI()) { 442198090Srdivacky emitConstPoolAddress(RelocOp->getIndex(), RelocType, 443198090Srdivacky RelocOp->getOffset(), Adj); 444193323Sed } else { 445198090Srdivacky assert(RelocOp->isJTI() && "Unexpected machine operand!"); 446198090Srdivacky emitJumpTableAddress(RelocOp->getIndex(), RelocType, Adj); 447193323Sed } 448193323Sed} 449193323Sed 450193323Sedtemplate<class CodeEmitter> 451193323Sedvoid Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI, 452198090Srdivacky unsigned Op,unsigned RegOpcodeField, 453198090Srdivacky intptr_t PCAdj) { 454193323Sed const MachineOperand &Op3 = MI.getOperand(Op+3); 455193323Sed int DispVal = 0; 456193323Sed const MachineOperand *DispForReloc = 0; 457239462Sdim 458193323Sed // Figure out what sort of displacement we have to handle here. 459193323Sed if (Op3.isGlobal()) { 460193323Sed DispForReloc = &Op3; 461198090Srdivacky } else if (Op3.isSymbol()) { 462198090Srdivacky DispForReloc = &Op3; 463193323Sed } else if (Op3.isCPI()) { 464198090Srdivacky if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) { 465193323Sed DispForReloc = &Op3; 466193323Sed } else { 467193323Sed DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex()); 468193323Sed DispVal += Op3.getOffset(); 469193323Sed } 470193323Sed } else if (Op3.isJTI()) { 471198090Srdivacky if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) { 472193323Sed DispForReloc = &Op3; 473193323Sed } else { 474193323Sed DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex()); 475193323Sed } 476193323Sed } else { 477193323Sed DispVal = Op3.getImm(); 478193323Sed } 479193323Sed 480193323Sed const MachineOperand &Base = MI.getOperand(Op); 481193323Sed const MachineOperand &Scale = MI.getOperand(Op+1); 482193323Sed const MachineOperand &IndexReg = MI.getOperand(Op+2); 483193323Sed 484193323Sed unsigned BaseReg = Base.getReg(); 485239462Sdim 486207618Srdivacky // Handle %rip relative addressing. 487207618Srdivacky if (BaseReg == X86::RIP || 488207618Srdivacky (Is64BitMode && DispForReloc)) { // [disp32+RIP] in X86-64 mode 489207618Srdivacky assert(IndexReg.getReg() == 0 && Is64BitMode && 490207618Srdivacky "Invalid rip-relative address"); 491207618Srdivacky MCE.emitByte(ModRMByte(0, RegOpcodeField, 5)); 492207618Srdivacky emitDisplacementField(DispForReloc, DispVal, PCAdj, true); 493207618Srdivacky return; 494207618Srdivacky } 495193323Sed 496198090Srdivacky // Indicate that the displacement will use an pcrel or absolute reference 497198090Srdivacky // by default. MCEs able to resolve addresses on-the-fly use pcrel by default 498198090Srdivacky // while others, unless explicit asked to use RIP, use absolute references. 499198090Srdivacky bool IsPCRel = MCE.earlyResolveAddresses() ? true : false; 500198090Srdivacky 501193323Sed // Is a SIB byte needed? 502239462Sdim // If no BaseReg, issue a RIP relative instruction only if the MCE can 503198090Srdivacky // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table 504198090Srdivacky // 2-7) and absolute references. 505203954Srdivacky unsigned BaseRegNo = -1U; 506203954Srdivacky if (BaseReg != 0 && BaseReg != X86::RIP) 507243830Sdim BaseRegNo = getX86RegNum(BaseReg); 508203954Srdivacky 509203954Srdivacky if (// The SIB byte must be used if there is an index register. 510239462Sdim IndexReg.getReg() == 0 && 511203954Srdivacky // The SIB byte must be used if the base is ESP/RSP/R12, all of which 512203954Srdivacky // encode to an R/M value of 4, which indicates that a SIB byte is 513203954Srdivacky // present. 514203954Srdivacky BaseRegNo != N86::ESP && 515203954Srdivacky // If there is no base register and we're in 64-bit mode, we need a SIB 516203954Srdivacky // byte to emit an addr that is just 'disp32' (the non-RIP relative form). 517203954Srdivacky (!Is64BitMode || BaseReg != 0)) { 518203954Srdivacky if (BaseReg == 0 || // [disp32] in X86-32 mode 519203954Srdivacky BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode 520193323Sed MCE.emitByte(ModRMByte(0, RegOpcodeField, 5)); 521198090Srdivacky emitDisplacementField(DispForReloc, DispVal, PCAdj, true); 522203954Srdivacky return; 523193323Sed } 524239462Sdim 525203954Srdivacky // If the base is not EBP/ESP and there is no displacement, use simple 526203954Srdivacky // indirect register encoding, this handles addresses like [EAX]. The 527203954Srdivacky // encoding for [EBP] with no displacement means [disp32] so we handle it 528203954Srdivacky // by emitting a displacement of 0 below. 529203954Srdivacky if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) { 530203954Srdivacky MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo)); 531203954Srdivacky return; 532193323Sed } 533239462Sdim 534203954Srdivacky // Otherwise, if the displacement fits in a byte, encode as [REG+disp8]. 535203954Srdivacky if (!DispForReloc && isDisp8(DispVal)) { 536203954Srdivacky MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo)); 537203954Srdivacky emitConstant(DispVal, 1); 538203954Srdivacky return; 539203954Srdivacky } 540239462Sdim 541203954Srdivacky // Otherwise, emit the most general non-SIB encoding: [REG+disp32] 542203954Srdivacky MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo)); 543203954Srdivacky emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel); 544203954Srdivacky return; 545203954Srdivacky } 546239462Sdim 547203954Srdivacky // Otherwise we need a SIB byte, so start by outputting the ModR/M byte first. 548203954Srdivacky assert(IndexReg.getReg() != X86::ESP && 549203954Srdivacky IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 550193323Sed 551203954Srdivacky bool ForceDisp32 = false; 552203954Srdivacky bool ForceDisp8 = false; 553203954Srdivacky if (BaseReg == 0) { 554203954Srdivacky // If there is no base register, we emit the special case SIB byte with 555203954Srdivacky // MOD=0, BASE=4, to JUST get the index, scale, and displacement. 556203954Srdivacky MCE.emitByte(ModRMByte(0, RegOpcodeField, 4)); 557203954Srdivacky ForceDisp32 = true; 558203954Srdivacky } else if (DispForReloc) { 559203954Srdivacky // Emit the normal disp32 encoding. 560203954Srdivacky MCE.emitByte(ModRMByte(2, RegOpcodeField, 4)); 561203954Srdivacky ForceDisp32 = true; 562207618Srdivacky } else if (DispVal == 0 && BaseRegNo != N86::EBP) { 563203954Srdivacky // Emit no displacement ModR/M byte 564203954Srdivacky MCE.emitByte(ModRMByte(0, RegOpcodeField, 4)); 565203954Srdivacky } else if (isDisp8(DispVal)) { 566203954Srdivacky // Emit the disp8 encoding... 567203954Srdivacky MCE.emitByte(ModRMByte(1, RegOpcodeField, 4)); 568203954Srdivacky ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 569203954Srdivacky } else { 570203954Srdivacky // Emit the normal disp32 encoding... 571203954Srdivacky MCE.emitByte(ModRMByte(2, RegOpcodeField, 4)); 572203954Srdivacky } 573193323Sed 574203954Srdivacky // Calculate what the SS field value should be... 575226633Sdim static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 }; 576203954Srdivacky unsigned SS = SSTable[Scale.getImm()]; 577193323Sed 578203954Srdivacky if (BaseReg == 0) { 579239462Sdim // Handle the SIB byte for the case where there is no base, see Intel 580203954Srdivacky // Manual 2A, table 2-7. The displacement has already been output. 581203954Srdivacky unsigned IndexRegNo; 582203954Srdivacky if (IndexReg.getReg()) 583243830Sdim IndexRegNo = getX86RegNum(IndexReg.getReg()); 584203954Srdivacky else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5) 585203954Srdivacky IndexRegNo = 4; 586203954Srdivacky emitSIBByte(SS, IndexRegNo, 5); 587203954Srdivacky } else { 588243830Sdim unsigned BaseRegNo = getX86RegNum(BaseReg); 589203954Srdivacky unsigned IndexRegNo; 590203954Srdivacky if (IndexReg.getReg()) 591243830Sdim IndexRegNo = getX86RegNum(IndexReg.getReg()); 592203954Srdivacky else 593203954Srdivacky IndexRegNo = 4; // For example [ESP+1*<noreg>+4] 594203954Srdivacky emitSIBByte(SS, IndexRegNo, BaseRegNo); 595193323Sed } 596203954Srdivacky 597203954Srdivacky // Do we need to output a displacement? 598203954Srdivacky if (ForceDisp8) { 599203954Srdivacky emitConstant(DispVal, 1); 600203954Srdivacky } else if (DispVal != 0 || ForceDisp32) { 601203954Srdivacky emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel); 602203954Srdivacky } 603193323Sed} 604193323Sed 605228379Sdimstatic const MCInstrDesc *UpdateOp(MachineInstr &MI, const X86InstrInfo *II, 606228379Sdim unsigned Opcode) { 607228379Sdim const MCInstrDesc *Desc = &II->get(Opcode); 608228379Sdim MI.setDesc(*Desc); 609228379Sdim return Desc; 610228379Sdim} 611228379Sdim 612239462Sdim/// Is16BitMemOperand - Return true if the specified instruction has 613239462Sdim/// a 16-bit memory operand. Op specifies the operand # of the memoperand. 614239462Sdimstatic bool Is16BitMemOperand(const MachineInstr &MI, unsigned Op) { 615239462Sdim const MachineOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 616239462Sdim const MachineOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 617193323Sed 618239462Sdim if ((BaseReg.getReg() != 0 && 619239462Sdim X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || 620239462Sdim (IndexReg.getReg() != 0 && 621239462Sdim X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) 622239462Sdim return true; 623239462Sdim return false; 624239462Sdim} 625198090Srdivacky 626239462Sdim/// Is32BitMemOperand - Return true if the specified instruction has 627239462Sdim/// a 32-bit memory operand. Op specifies the operand # of the memoperand. 628239462Sdimstatic bool Is32BitMemOperand(const MachineInstr &MI, unsigned Op) { 629239462Sdim const MachineOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 630239462Sdim const MachineOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 631193323Sed 632239462Sdim if ((BaseReg.getReg() != 0 && 633239462Sdim X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || 634239462Sdim (IndexReg.getReg() != 0 && 635239462Sdim X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) 636239462Sdim return true; 637239462Sdim return false; 638239462Sdim} 639239462Sdim 640239462Sdim/// Is64BitMemOperand - Return true if the specified instruction has 641239462Sdim/// a 64-bit memory operand. Op specifies the operand # of the memoperand. 642239462Sdim#ifndef NDEBUG 643239462Sdimstatic bool Is64BitMemOperand(const MachineInstr &MI, unsigned Op) { 644239462Sdim const MachineOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 645239462Sdim const MachineOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 646239462Sdim 647239462Sdim if ((BaseReg.getReg() != 0 && 648239462Sdim X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || 649239462Sdim (IndexReg.getReg() != 0 && 650239462Sdim X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg()))) 651239462Sdim return true; 652239462Sdim return false; 653239462Sdim} 654239462Sdim#endif 655239462Sdim 656239462Sdimtemplate<class CodeEmitter> 657239462Sdimvoid Emitter<CodeEmitter>::emitOpcodePrefix(uint64_t TSFlags, 658239462Sdim int MemOperand, 659239462Sdim const MachineInstr &MI, 660239462Sdim const MCInstrDesc *Desc) const { 661193323Sed // Emit the lock opcode prefix as needed. 662198090Srdivacky if (Desc->TSFlags & X86II::LOCK) 663198090Srdivacky MCE.emitByte(0xF0); 664193323Sed 665193323Sed // Emit segment override opcode prefix as needed. 666239462Sdim emitSegmentOverridePrefix(TSFlags, MemOperand, MI); 667193323Sed 668193323Sed // Emit the repeat opcode prefix as needed. 669198090Srdivacky if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) 670198090Srdivacky MCE.emitByte(0xF3); 671193323Sed 672239462Sdim // Emit the address size opcode prefix as needed. 673239462Sdim bool need_address_override; 674239462Sdim if (TSFlags & X86II::AdSize) { 675239462Sdim need_address_override = true; 676239462Sdim } else if (MemOperand == -1) { 677239462Sdim need_address_override = false; 678239462Sdim } else if (Is64BitMode) { 679239462Sdim assert(!Is16BitMemOperand(MI, MemOperand)); 680239462Sdim need_address_override = Is32BitMemOperand(MI, MemOperand); 681239462Sdim } else { 682239462Sdim assert(!Is64BitMemOperand(MI, MemOperand)); 683239462Sdim need_address_override = Is16BitMemOperand(MI, MemOperand); 684239462Sdim } 685239462Sdim 686239462Sdim if (need_address_override) 687239462Sdim MCE.emitByte(0x67); 688239462Sdim 689193323Sed // Emit the operand size opcode prefix as needed. 690239462Sdim if (TSFlags & X86II::OpSize) 691198090Srdivacky MCE.emitByte(0x66); 692193323Sed 693193323Sed bool Need0FPrefix = false; 694193323Sed switch (Desc->TSFlags & X86II::Op0Mask) { 695239462Sdim case X86II::TB: // Two-byte opcode prefix 696239462Sdim case X86II::T8: // 0F 38 697239462Sdim case X86II::TA: // 0F 3A 698239462Sdim case X86II::A6: // 0F A6 699239462Sdim case X86II::A7: // 0F A7 700239462Sdim Need0FPrefix = true; 701239462Sdim break; 702239462Sdim case X86II::REP: break; // already handled. 703239462Sdim case X86II::T8XS: // F3 0F 38 704239462Sdim case X86II::XS: // F3 0F 705239462Sdim MCE.emitByte(0xF3); 706239462Sdim Need0FPrefix = true; 707239462Sdim break; 708239462Sdim case X86II::T8XD: // F2 0F 38 709239462Sdim case X86II::TAXD: // F2 0F 3A 710239462Sdim case X86II::XD: // F2 0F 711239462Sdim MCE.emitByte(0xF2); 712239462Sdim Need0FPrefix = true; 713239462Sdim break; 714239462Sdim case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB: 715239462Sdim case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF: 716239462Sdim MCE.emitByte(0xD8+ 717239462Sdim (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8) 718239462Sdim >> X86II::Op0Shift)); 719239462Sdim break; // Two-byte opcode prefix 720239462Sdim default: llvm_unreachable("Invalid prefix!"); 721239462Sdim case 0: break; // No prefix! 722193323Sed } 723193323Sed 724198090Srdivacky // Handle REX prefix. 725193323Sed if (Is64BitMode) { 726212904Sdim if (unsigned REX = determineREX(MI)) 727193323Sed MCE.emitByte(0x40 | REX); 728193323Sed } 729193323Sed 730193323Sed // 0x0F escape code must be emitted just before the opcode. 731193323Sed if (Need0FPrefix) 732193323Sed MCE.emitByte(0x0F); 733193323Sed 734193323Sed switch (Desc->TSFlags & X86II::Op0Mask) { 735239462Sdim case X86II::T8XD: // F2 0F 38 736239462Sdim case X86II::T8XS: // F3 0F 38 737239462Sdim case X86II::T8: // 0F 38 738239462Sdim MCE.emitByte(0x38); 739239462Sdim break; 740239462Sdim case X86II::TAXD: // F2 0F 38 741239462Sdim case X86II::TA: // 0F 3A 742239462Sdim MCE.emitByte(0x3A); 743239462Sdim break; 744239462Sdim case X86II::A6: // 0F A6 745239462Sdim MCE.emitByte(0xA6); 746239462Sdim break; 747239462Sdim case X86II::A7: // 0F A7 748239462Sdim MCE.emitByte(0xA7); 749239462Sdim break; 750193323Sed } 751239462Sdim} 752193323Sed 753239462Sdim// On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range 754239462Sdim// 0-7 and the difference between the 2 groups is given by the REX prefix. 755239462Sdim// In the VEX prefix, registers are seen sequencially from 0-15 and encoded 756239462Sdim// in 1's complement form, example: 757239462Sdim// 758239462Sdim// ModRM field => XMM9 => 1 759239462Sdim// VEX.VVVV => XMM9 => ~9 760239462Sdim// 761239462Sdim// See table 4-35 of Intel AVX Programming Reference for details. 762243830Sdimtemplate<class CodeEmitter> 763243830Sdimunsigned char 764243830SdimEmitter<CodeEmitter>::getVEXRegisterEncoding(const MachineInstr &MI, 765243830Sdim unsigned OpNum) const { 766239462Sdim unsigned SrcReg = MI.getOperand(OpNum).getReg(); 767243830Sdim unsigned SrcRegNum = getX86RegNum(MI.getOperand(OpNum).getReg()); 768239462Sdim if (X86II::isX86_64ExtendedReg(SrcReg)) 769239462Sdim SrcRegNum |= 8; 770239462Sdim 771239462Sdim // The registers represented through VEX_VVVV should 772239462Sdim // be encoded in 1's complement form. 773239462Sdim return (~SrcRegNum) & 0xf; 774239462Sdim} 775239462Sdim 776239462Sdim/// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed 777239462Sdimtemplate<class CodeEmitter> 778239462Sdimvoid Emitter<CodeEmitter>::emitSegmentOverridePrefix(uint64_t TSFlags, 779239462Sdim int MemOperand, 780239462Sdim const MachineInstr &MI) const { 781239462Sdim switch (TSFlags & X86II::SegOvrMask) { 782239462Sdim default: llvm_unreachable("Invalid segment!"); 783239462Sdim case 0: 784239462Sdim // No segment override, check for explicit one on memory operand. 785239462Sdim if (MemOperand != -1) { // If the instruction has a memory operand. 786239462Sdim switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) { 787239462Sdim default: llvm_unreachable("Unknown segment register!"); 788239462Sdim case 0: break; 789239462Sdim case X86::CS: MCE.emitByte(0x2E); break; 790239462Sdim case X86::SS: MCE.emitByte(0x36); break; 791239462Sdim case X86::DS: MCE.emitByte(0x3E); break; 792239462Sdim case X86::ES: MCE.emitByte(0x26); break; 793239462Sdim case X86::FS: MCE.emitByte(0x64); break; 794239462Sdim case X86::GS: MCE.emitByte(0x65); break; 795239462Sdim } 796239462Sdim } 797239462Sdim break; 798239462Sdim case X86II::FS: 799239462Sdim MCE.emitByte(0x64); 800239462Sdim break; 801239462Sdim case X86II::GS: 802239462Sdim MCE.emitByte(0x65); 803239462Sdim break; 804239462Sdim } 805239462Sdim} 806239462Sdim 807239462Sdimtemplate<class CodeEmitter> 808239462Sdimvoid Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags, 809239462Sdim int MemOperand, 810239462Sdim const MachineInstr &MI, 811239462Sdim const MCInstrDesc *Desc) const { 812239462Sdim bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 813239462Sdim bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3; 814249423Sdim bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4; 815239462Sdim 816239462Sdim // VEX_R: opcode externsion equivalent to REX.R in 817239462Sdim // 1's complement (inverted) form 818239462Sdim // 819239462Sdim // 1: Same as REX_R=0 (must be 1 in 32-bit mode) 820239462Sdim // 0: Same as REX_R=1 (64 bit mode only) 821239462Sdim // 822239462Sdim unsigned char VEX_R = 0x1; 823239462Sdim 824239462Sdim // VEX_X: equivalent to REX.X, only used when a 825239462Sdim // register is used for index in SIB Byte. 826239462Sdim // 827239462Sdim // 1: Same as REX.X=0 (must be 1 in 32-bit mode) 828239462Sdim // 0: Same as REX.X=1 (64-bit mode only) 829239462Sdim unsigned char VEX_X = 0x1; 830239462Sdim 831239462Sdim // VEX_B: 832239462Sdim // 833239462Sdim // 1: Same as REX_B=0 (ignored in 32-bit mode) 834239462Sdim // 0: Same as REX_B=1 (64 bit mode only) 835239462Sdim // 836239462Sdim unsigned char VEX_B = 0x1; 837239462Sdim 838239462Sdim // VEX_W: opcode specific (use like REX.W, or used for 839239462Sdim // opcode extension, or ignored, depending on the opcode byte) 840239462Sdim unsigned char VEX_W = 0; 841239462Sdim 842239462Sdim // XOP: Use XOP prefix byte 0x8f instead of VEX. 843263508Sdim bool XOP = false; 844239462Sdim 845239462Sdim // VEX_5M (VEX m-mmmmm field): 846239462Sdim // 847239462Sdim // 0b00000: Reserved for future use 848239462Sdim // 0b00001: implied 0F leading opcode 849239462Sdim // 0b00010: implied 0F 38 leading opcode bytes 850239462Sdim // 0b00011: implied 0F 3A leading opcode bytes 851239462Sdim // 0b00100-0b11111: Reserved for future use 852239462Sdim // 0b01000: XOP map select - 08h instructions with imm byte 853263508Sdim // 0b01001: XOP map select - 09h instructions with no imm byte 854263508Sdim // 0b01010: XOP map select - 0Ah instructions with imm dword 855239462Sdim unsigned char VEX_5M = 0x1; 856239462Sdim 857239462Sdim // VEX_4V (VEX vvvv field): a register specifier 858239462Sdim // (in 1's complement form) or 1111 if unused. 859239462Sdim unsigned char VEX_4V = 0xf; 860239462Sdim 861239462Sdim // VEX_L (Vector Length): 862239462Sdim // 863239462Sdim // 0: scalar or 128-bit vector 864239462Sdim // 1: 256-bit vector 865239462Sdim // 866239462Sdim unsigned char VEX_L = 0; 867239462Sdim 868239462Sdim // VEX_PP: opcode extension providing equivalent 869239462Sdim // functionality of a SIMD prefix 870239462Sdim // 871239462Sdim // 0b00: None 872239462Sdim // 0b01: 66 873239462Sdim // 0b10: F3 874239462Sdim // 0b11: F2 875239462Sdim // 876239462Sdim unsigned char VEX_PP = 0; 877239462Sdim 878239462Sdim // Encode the operand size opcode prefix as needed. 879239462Sdim if (TSFlags & X86II::OpSize) 880239462Sdim VEX_PP = 0x01; 881239462Sdim 882239462Sdim if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W) 883239462Sdim VEX_W = 1; 884239462Sdim 885239462Sdim if ((TSFlags >> X86II::VEXShift) & X86II::XOP) 886263508Sdim XOP = true; 887239462Sdim 888239462Sdim if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L) 889239462Sdim VEX_L = 1; 890239462Sdim 891239462Sdim switch (TSFlags & X86II::Op0Mask) { 892239462Sdim default: llvm_unreachable("Invalid prefix!"); 893239462Sdim case X86II::T8: // 0F 38 894239462Sdim VEX_5M = 0x2; 895239462Sdim break; 896239462Sdim case X86II::TA: // 0F 3A 897239462Sdim VEX_5M = 0x3; 898239462Sdim break; 899239462Sdim case X86II::T8XS: // F3 0F 38 900239462Sdim VEX_PP = 0x2; 901239462Sdim VEX_5M = 0x2; 902239462Sdim break; 903239462Sdim case X86II::T8XD: // F2 0F 38 904239462Sdim VEX_PP = 0x3; 905239462Sdim VEX_5M = 0x2; 906239462Sdim break; 907239462Sdim case X86II::TAXD: // F2 0F 3A 908239462Sdim VEX_PP = 0x3; 909239462Sdim VEX_5M = 0x3; 910239462Sdim break; 911239462Sdim case X86II::XS: // F3 0F 912239462Sdim VEX_PP = 0x2; 913239462Sdim break; 914239462Sdim case X86II::XD: // F2 0F 915239462Sdim VEX_PP = 0x3; 916239462Sdim break; 917239462Sdim case X86II::XOP8: 918239462Sdim VEX_5M = 0x8; 919239462Sdim break; 920239462Sdim case X86II::XOP9: 921239462Sdim VEX_5M = 0x9; 922239462Sdim break; 923263508Sdim case X86II::XOPA: 924263508Sdim VEX_5M = 0xA; 925263508Sdim break; 926263508Sdim case X86II::TB: // VEX_5M/VEX_PP already correct 927263508Sdim break; 928239462Sdim } 929239462Sdim 930239462Sdim 931239462Sdim // Classify VEX_B, VEX_4V, VEX_R, VEX_X 932239462Sdim unsigned NumOps = Desc->getNumOperands(); 933239462Sdim unsigned CurOp = 0; 934239462Sdim if (NumOps > 1 && Desc->getOperandConstraint(1, MCOI::TIED_TO) == 0) 935239462Sdim ++CurOp; 936239462Sdim else if (NumOps > 3 && Desc->getOperandConstraint(2, MCOI::TIED_TO) == 0) { 937239462Sdim assert(Desc->getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1); 938239462Sdim // Special case for GATHER with 2 TIED_TO operands 939239462Sdim // Skip the first 2 operands: dst, mask_wb 940239462Sdim CurOp += 2; 941239462Sdim } 942239462Sdim 943239462Sdim switch (TSFlags & X86II::FormMask) { 944239462Sdim case X86II::MRMInitReg: 945239462Sdim // Duplicate register. 946239462Sdim if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 947239462Sdim VEX_R = 0x0; 948239462Sdim 949239462Sdim if (HasVEX_4V) 950239462Sdim VEX_4V = getVEXRegisterEncoding(MI, CurOp); 951239462Sdim if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 952239462Sdim VEX_B = 0x0; 953239462Sdim if (HasVEX_4VOp3) 954239462Sdim VEX_4V = getVEXRegisterEncoding(MI, CurOp); 955239462Sdim break; 956239462Sdim case X86II::MRMDestMem: { 957239462Sdim // MRMDestMem instructions forms: 958239462Sdim // MemAddr, src1(ModR/M) 959239462Sdim // MemAddr, src1(VEX_4V), src2(ModR/M) 960239462Sdim // MemAddr, src1(ModR/M), imm8 961239462Sdim // 962239462Sdim if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrBaseReg).getReg())) 963239462Sdim VEX_B = 0x0; 964239462Sdim if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrIndexReg).getReg())) 965239462Sdim VEX_X = 0x0; 966239462Sdim 967239462Sdim CurOp = X86::AddrNumOperands; 968239462Sdim if (HasVEX_4V) 969239462Sdim VEX_4V = getVEXRegisterEncoding(MI, CurOp++); 970239462Sdim 971239462Sdim const MachineOperand &MO = MI.getOperand(CurOp); 972239462Sdim if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 973239462Sdim VEX_R = 0x0; 974239462Sdim break; 975239462Sdim } 976239462Sdim case X86II::MRMSrcMem: 977239462Sdim // MRMSrcMem instructions forms: 978239462Sdim // src1(ModR/M), MemAddr 979239462Sdim // src1(ModR/M), src2(VEX_4V), MemAddr 980239462Sdim // src1(ModR/M), MemAddr, imm8 981239462Sdim // src1(ModR/M), MemAddr, src2(VEX_I8IMM) 982239462Sdim // 983239462Sdim // FMA4: 984239462Sdim // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 985239462Sdim // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M), 986263508Sdim if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 987239462Sdim VEX_R = 0x0; 988263508Sdim CurOp++; 989239462Sdim 990263508Sdim if (HasVEX_4V) { 991263508Sdim VEX_4V = getVEXRegisterEncoding(MI, CurOp); 992263508Sdim CurOp++; 993263508Sdim } 994239462Sdim 995239462Sdim if (X86II::isX86_64ExtendedReg( 996239462Sdim MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) 997239462Sdim VEX_B = 0x0; 998239462Sdim if (X86II::isX86_64ExtendedReg( 999239462Sdim MI.getOperand(MemOperand+X86::AddrIndexReg).getReg())) 1000239462Sdim VEX_X = 0x0; 1001239462Sdim 1002239462Sdim if (HasVEX_4VOp3) 1003263508Sdim VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands); 1004239462Sdim break; 1005239462Sdim case X86II::MRM0m: case X86II::MRM1m: 1006239462Sdim case X86II::MRM2m: case X86II::MRM3m: 1007239462Sdim case X86II::MRM4m: case X86II::MRM5m: 1008239462Sdim case X86II::MRM6m: case X86II::MRM7m: { 1009239462Sdim // MRM[0-9]m instructions forms: 1010239462Sdim // MemAddr 1011239462Sdim // src1(VEX_4V), MemAddr 1012239462Sdim if (HasVEX_4V) 1013263508Sdim VEX_4V = getVEXRegisterEncoding(MI, CurOp++); 1014239462Sdim 1015239462Sdim if (X86II::isX86_64ExtendedReg( 1016239462Sdim MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) 1017239462Sdim VEX_B = 0x0; 1018239462Sdim if (X86II::isX86_64ExtendedReg( 1019239462Sdim MI.getOperand(MemOperand+X86::AddrIndexReg).getReg())) 1020239462Sdim VEX_X = 0x0; 1021239462Sdim break; 1022239462Sdim } 1023239462Sdim case X86II::MRMSrcReg: 1024239462Sdim // MRMSrcReg instructions forms: 1025239462Sdim // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 1026239462Sdim // dst(ModR/M), src1(ModR/M) 1027239462Sdim // dst(ModR/M), src1(ModR/M), imm8 1028239462Sdim // 1029239462Sdim if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 1030239462Sdim VEX_R = 0x0; 1031239462Sdim CurOp++; 1032239462Sdim 1033239462Sdim if (HasVEX_4V) 1034239462Sdim VEX_4V = getVEXRegisterEncoding(MI, CurOp++); 1035249423Sdim 1036249423Sdim if (HasMemOp4) // Skip second register source (encoded in I8IMM) 1037249423Sdim CurOp++; 1038249423Sdim 1039239462Sdim if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 1040239462Sdim VEX_B = 0x0; 1041239462Sdim CurOp++; 1042239462Sdim if (HasVEX_4VOp3) 1043239462Sdim VEX_4V = getVEXRegisterEncoding(MI, CurOp); 1044239462Sdim break; 1045239462Sdim case X86II::MRMDestReg: 1046239462Sdim // MRMDestReg instructions forms: 1047239462Sdim // dst(ModR/M), src(ModR/M) 1048239462Sdim // dst(ModR/M), src(ModR/M), imm8 1049249423Sdim // dst(ModR/M), src1(VEX_4V), src2(ModR/M) 1050249423Sdim if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 1051239462Sdim VEX_B = 0x0; 1052249423Sdim CurOp++; 1053249423Sdim 1054249423Sdim if (HasVEX_4V) 1055249423Sdim VEX_4V = getVEXRegisterEncoding(MI, CurOp++); 1056249423Sdim 1057249423Sdim if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 1058239462Sdim VEX_R = 0x0; 1059239462Sdim break; 1060239462Sdim case X86II::MRM0r: case X86II::MRM1r: 1061239462Sdim case X86II::MRM2r: case X86II::MRM3r: 1062239462Sdim case X86II::MRM4r: case X86II::MRM5r: 1063239462Sdim case X86II::MRM6r: case X86II::MRM7r: 1064239462Sdim // MRM0r-MRM7r instructions forms: 1065239462Sdim // dst(VEX_4V), src(ModR/M), imm8 1066263508Sdim VEX_4V = getVEXRegisterEncoding(MI, CurOp); 1067263508Sdim CurOp++; 1068263508Sdim 1069263508Sdim if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 1070239462Sdim VEX_B = 0x0; 1071239462Sdim break; 1072239462Sdim default: // RawFrm 1073239462Sdim break; 1074239462Sdim } 1075239462Sdim 1076239462Sdim // Emit segment override opcode prefix as needed. 1077239462Sdim emitSegmentOverridePrefix(TSFlags, MemOperand, MI); 1078239462Sdim 1079239462Sdim // VEX opcode prefix can have 2 or 3 bytes 1080239462Sdim // 1081239462Sdim // 3 bytes: 1082239462Sdim // +-----+ +--------------+ +-------------------+ 1083239462Sdim // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp | 1084239462Sdim // +-----+ +--------------+ +-------------------+ 1085239462Sdim // 2 bytes: 1086239462Sdim // +-----+ +-------------------+ 1087239462Sdim // | C5h | | R | vvvv | L | pp | 1088239462Sdim // +-----+ +-------------------+ 1089239462Sdim // 1090239462Sdim unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3); 1091239462Sdim 1092239462Sdim if (VEX_B && VEX_X && !VEX_W && !XOP && (VEX_5M == 1)) { // 2 byte VEX prefix 1093239462Sdim MCE.emitByte(0xC5); 1094239462Sdim MCE.emitByte(LastByte | (VEX_R << 7)); 1095239462Sdim return; 1096239462Sdim } 1097239462Sdim 1098239462Sdim // 3 byte VEX prefix 1099239462Sdim MCE.emitByte(XOP ? 0x8F : 0xC4); 1100239462Sdim MCE.emitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M); 1101239462Sdim MCE.emitByte(LastByte | (VEX_W << 7)); 1102239462Sdim} 1103239462Sdim 1104239462Sdimtemplate<class CodeEmitter> 1105239462Sdimvoid Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI, 1106239462Sdim const MCInstrDesc *Desc) { 1107239462Sdim DEBUG(dbgs() << MI); 1108239462Sdim 1109239462Sdim // If this is a pseudo instruction, lower it. 1110239462Sdim switch (Desc->getOpcode()) { 1111239462Sdim case X86::ADD16rr_DB: Desc = UpdateOp(MI, II, X86::OR16rr); break; 1112239462Sdim case X86::ADD32rr_DB: Desc = UpdateOp(MI, II, X86::OR32rr); break; 1113239462Sdim case X86::ADD64rr_DB: Desc = UpdateOp(MI, II, X86::OR64rr); break; 1114239462Sdim case X86::ADD16ri_DB: Desc = UpdateOp(MI, II, X86::OR16ri); break; 1115239462Sdim case X86::ADD32ri_DB: Desc = UpdateOp(MI, II, X86::OR32ri); break; 1116239462Sdim case X86::ADD64ri32_DB: Desc = UpdateOp(MI, II, X86::OR64ri32); break; 1117239462Sdim case X86::ADD16ri8_DB: Desc = UpdateOp(MI, II, X86::OR16ri8); break; 1118239462Sdim case X86::ADD32ri8_DB: Desc = UpdateOp(MI, II, X86::OR32ri8); break; 1119239462Sdim case X86::ADD64ri8_DB: Desc = UpdateOp(MI, II, X86::OR64ri8); break; 1120239462Sdim case X86::ACQUIRE_MOV8rm: Desc = UpdateOp(MI, II, X86::MOV8rm); break; 1121239462Sdim case X86::ACQUIRE_MOV16rm: Desc = UpdateOp(MI, II, X86::MOV16rm); break; 1122239462Sdim case X86::ACQUIRE_MOV32rm: Desc = UpdateOp(MI, II, X86::MOV32rm); break; 1123239462Sdim case X86::ACQUIRE_MOV64rm: Desc = UpdateOp(MI, II, X86::MOV64rm); break; 1124239462Sdim case X86::RELEASE_MOV8mr: Desc = UpdateOp(MI, II, X86::MOV8mr); break; 1125239462Sdim case X86::RELEASE_MOV16mr: Desc = UpdateOp(MI, II, X86::MOV16mr); break; 1126239462Sdim case X86::RELEASE_MOV32mr: Desc = UpdateOp(MI, II, X86::MOV32mr); break; 1127239462Sdim case X86::RELEASE_MOV64mr: Desc = UpdateOp(MI, II, X86::MOV64mr); break; 1128239462Sdim } 1129239462Sdim 1130239462Sdim 1131239462Sdim MCE.processDebugLoc(MI.getDebugLoc(), true); 1132239462Sdim 1133239462Sdim unsigned Opcode = Desc->Opcode; 1134239462Sdim 1135193323Sed // If this is a two-address instruction, skip one of the register operands. 1136193323Sed unsigned NumOps = Desc->getNumOperands(); 1137193323Sed unsigned CurOp = 0; 1138239462Sdim if (NumOps > 1 && Desc->getOperandConstraint(1, MCOI::TIED_TO) == 0) 1139193323Sed ++CurOp; 1140239462Sdim else if (NumOps > 3 && Desc->getOperandConstraint(2, MCOI::TIED_TO) == 0) { 1141239462Sdim assert(Desc->getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1); 1142239462Sdim // Special case for GATHER with 2 TIED_TO operands 1143239462Sdim // Skip the first 2 operands: dst, mask_wb 1144239462Sdim CurOp += 2; 1145239462Sdim } 1146193323Sed 1147239462Sdim uint64_t TSFlags = Desc->TSFlags; 1148239462Sdim 1149239462Sdim // Is this instruction encoded using the AVX VEX prefix? 1150239462Sdim bool HasVEXPrefix = (TSFlags >> X86II::VEXShift) & X86II::VEX; 1151239462Sdim // It uses the VEX.VVVV field? 1152239462Sdim bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 1153239462Sdim bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3; 1154239462Sdim bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4; 1155239462Sdim const unsigned MemOp4_I8IMMOperand = 2; 1156239462Sdim 1157239462Sdim // Determine where the memory operand starts, if present. 1158239462Sdim int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode); 1159239462Sdim if (MemoryOperand != -1) MemoryOperand += CurOp; 1160239462Sdim 1161239462Sdim if (!HasVEXPrefix) 1162239462Sdim emitOpcodePrefix(TSFlags, MemoryOperand, MI, Desc); 1163239462Sdim else 1164239462Sdim emitVEXOpcodePrefix(TSFlags, MemoryOperand, MI, Desc); 1165239462Sdim 1166203954Srdivacky unsigned char BaseOpcode = X86II::getBaseOpcodeFor(Desc->TSFlags); 1167239462Sdim switch (TSFlags & X86II::FormMask) { 1168198090Srdivacky default: 1169198090Srdivacky llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!"); 1170193323Sed case X86II::Pseudo: 1171193323Sed // Remember the current PC offset, this is the PIC relocation 1172193323Sed // base address. 1173193323Sed switch (Opcode) { 1174239462Sdim default: 1175212904Sdim llvm_unreachable("pseudo instructions should be removed before code" 1176198090Srdivacky " emission"); 1177212904Sdim // Do nothing for Int_MemBarrier - it's just a comment. Add a debug 1178212904Sdim // to make it slightly easier to see. 1179212904Sdim case X86::Int_MemBarrier: 1180212904Sdim DEBUG(dbgs() << "#MEMBARRIER\n"); 1181212904Sdim break; 1182239462Sdim 1183203954Srdivacky case TargetOpcode::INLINEASM: 1184193323Sed // We allow inline assembler nodes with empty bodies - they can 1185193323Sed // implicitly define registers, which is ok for JIT. 1186198090Srdivacky if (MI.getOperand(0).getSymbolName()[0]) 1187207618Srdivacky report_fatal_error("JIT does not support inline asm!"); 1188193323Sed break; 1189212904Sdim case TargetOpcode::PROLOG_LABEL: 1190205218Srdivacky case TargetOpcode::GC_LABEL: 1191203954Srdivacky case TargetOpcode::EH_LABEL: 1192205218Srdivacky MCE.emitLabel(MI.getOperand(0).getMCSymbol()); 1193193323Sed break; 1194239462Sdim 1195203954Srdivacky case TargetOpcode::IMPLICIT_DEF: 1196203954Srdivacky case TargetOpcode::KILL: 1197193323Sed break; 1198193323Sed case X86::MOVPC32r: { 1199193323Sed // This emits the "call" portion of this pseudo instruction. 1200193323Sed MCE.emitByte(BaseOpcode); 1201203954Srdivacky emitConstant(0, X86II::getSizeOfImm(Desc->TSFlags)); 1202193323Sed // Remember PIC base. 1203193323Sed PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset(); 1204193323Sed X86JITInfo *JTI = TM.getJITInfo(); 1205193323Sed JTI->setPICBase(MCE.getCurrentPCValue()); 1206193323Sed break; 1207193323Sed } 1208193323Sed } 1209193323Sed CurOp = NumOps; 1210193323Sed break; 1211198090Srdivacky case X86II::RawFrm: { 1212193323Sed MCE.emitByte(BaseOpcode); 1213193323Sed 1214198090Srdivacky if (CurOp == NumOps) 1215198090Srdivacky break; 1216239462Sdim 1217198090Srdivacky const MachineOperand &MO = MI.getOperand(CurOp++); 1218193323Sed 1219202375Srdivacky DEBUG(dbgs() << "RawFrm CurOp " << CurOp << "\n"); 1220202375Srdivacky DEBUG(dbgs() << "isMBB " << MO.isMBB() << "\n"); 1221202375Srdivacky DEBUG(dbgs() << "isGlobal " << MO.isGlobal() << "\n"); 1222202375Srdivacky DEBUG(dbgs() << "isSymbol " << MO.isSymbol() << "\n"); 1223202375Srdivacky DEBUG(dbgs() << "isImm " << MO.isImm() << "\n"); 1224193323Sed 1225198090Srdivacky if (MO.isMBB()) { 1226198090Srdivacky emitPCRelativeBlockAddress(MO.getMBB()); 1227198090Srdivacky break; 1228193323Sed } 1229239462Sdim 1230198090Srdivacky if (MO.isGlobal()) { 1231198090Srdivacky emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word, 1232199481Srdivacky MO.getOffset(), 0); 1233198090Srdivacky break; 1234198090Srdivacky } 1235239462Sdim 1236198090Srdivacky if (MO.isSymbol()) { 1237198090Srdivacky emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word); 1238198090Srdivacky break; 1239198090Srdivacky } 1240203954Srdivacky 1241203954Srdivacky // FIXME: Only used by hackish MCCodeEmitter, remove when dead. 1242203954Srdivacky if (MO.isJTI()) { 1243203954Srdivacky emitJumpTableAddress(MO.getIndex(), X86::reloc_pcrel_word); 1244203954Srdivacky break; 1245203954Srdivacky } 1246239462Sdim 1247198090Srdivacky assert(MO.isImm() && "Unknown RawFrm operand!"); 1248234353Sdim if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) { 1249198090Srdivacky // Fix up immediate operand for pc relative calls. 1250198090Srdivacky intptr_t Imm = (intptr_t)MO.getImm(); 1251198090Srdivacky Imm = Imm - MCE.getCurrentPCValue() - 4; 1252203954Srdivacky emitConstant(Imm, X86II::getSizeOfImm(Desc->TSFlags)); 1253198090Srdivacky } else 1254203954Srdivacky emitConstant(MO.getImm(), X86II::getSizeOfImm(Desc->TSFlags)); 1255193323Sed break; 1256198090Srdivacky } 1257239462Sdim 1258198090Srdivacky case X86II::AddRegFrm: { 1259226633Sdim MCE.emitByte(BaseOpcode + 1260243830Sdim getX86RegNum(MI.getOperand(CurOp++).getReg())); 1261239462Sdim 1262198090Srdivacky if (CurOp == NumOps) 1263198090Srdivacky break; 1264239462Sdim 1265198090Srdivacky const MachineOperand &MO1 = MI.getOperand(CurOp++); 1266203954Srdivacky unsigned Size = X86II::getSizeOfImm(Desc->TSFlags); 1267198090Srdivacky if (MO1.isImm()) { 1268198090Srdivacky emitConstant(MO1.getImm(), Size); 1269198090Srdivacky break; 1270193323Sed } 1271239462Sdim 1272198090Srdivacky unsigned rt = Is64BitMode ? X86::reloc_pcrel_word 1273198090Srdivacky : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); 1274263508Sdim if (Opcode == X86::MOV32ri64) 1275198090Srdivacky rt = X86::reloc_absolute_word; // FIXME: add X86II flag? 1276198090Srdivacky // This should not occur on Darwin for relocatable objects. 1277198090Srdivacky if (Opcode == X86::MOV64ri) 1278198090Srdivacky rt = X86::reloc_absolute_dword; // FIXME: add X86II flag? 1279198090Srdivacky if (MO1.isGlobal()) { 1280198090Srdivacky bool Indirect = gvNeedsNonLazyPtr(MO1, TM); 1281198090Srdivacky emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0, 1282199481Srdivacky Indirect); 1283198090Srdivacky } else if (MO1.isSymbol()) 1284198090Srdivacky emitExternalSymbolAddress(MO1.getSymbolName(), rt); 1285198090Srdivacky else if (MO1.isCPI()) 1286198090Srdivacky emitConstPoolAddress(MO1.getIndex(), rt); 1287198090Srdivacky else if (MO1.isJTI()) 1288198090Srdivacky emitJumpTableAddress(MO1.getIndex(), rt); 1289193323Sed break; 1290198090Srdivacky } 1291193323Sed 1292193323Sed case X86II::MRMDestReg: { 1293193323Sed MCE.emitByte(BaseOpcode); 1294249423Sdim 1295249423Sdim unsigned SrcRegNum = CurOp+1; 1296249423Sdim if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1297249423Sdim SrcRegNum++; 1298249423Sdim 1299193323Sed emitRegModRMByte(MI.getOperand(CurOp).getReg(), 1300249423Sdim getX86RegNum(MI.getOperand(SrcRegNum).getReg())); 1301249423Sdim CurOp = SrcRegNum + 1; 1302193323Sed break; 1303193323Sed } 1304193323Sed case X86II::MRMDestMem: { 1305193323Sed MCE.emitByte(BaseOpcode); 1306239462Sdim 1307239462Sdim unsigned SrcRegNum = CurOp + X86::AddrNumOperands; 1308239462Sdim if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1309239462Sdim SrcRegNum++; 1310193323Sed emitMemModRMByte(MI, CurOp, 1311243830Sdim getX86RegNum(MI.getOperand(SrcRegNum).getReg())); 1312239462Sdim CurOp = SrcRegNum + 1; 1313193323Sed break; 1314193323Sed } 1315193323Sed 1316239462Sdim case X86II::MRMSrcReg: { 1317193323Sed MCE.emitByte(BaseOpcode); 1318239462Sdim 1319239462Sdim unsigned SrcRegNum = CurOp+1; 1320239462Sdim if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1321239462Sdim ++SrcRegNum; 1322239462Sdim 1323239462Sdim if (HasMemOp4) // Skip 2nd src (which is encoded in I8IMM) 1324239462Sdim ++SrcRegNum; 1325239462Sdim 1326239462Sdim emitRegModRMByte(MI.getOperand(SrcRegNum).getReg(), 1327243830Sdim getX86RegNum(MI.getOperand(CurOp).getReg())); 1328239462Sdim // 2 operands skipped with HasMemOp4, compensate accordingly 1329239462Sdim CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1; 1330239462Sdim if (HasVEX_4VOp3) 1331239462Sdim ++CurOp; 1332193323Sed break; 1333239462Sdim } 1334193323Sed case X86II::MRMSrcMem: { 1335210299Sed int AddrOperands = X86::AddrNumOperands; 1336239462Sdim unsigned FirstMemOp = CurOp+1; 1337239462Sdim if (HasVEX_4V) { 1338239462Sdim ++AddrOperands; 1339239462Sdim ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV). 1340239462Sdim } 1341239462Sdim if (HasMemOp4) // Skip second register source (encoded in I8IMM) 1342239462Sdim ++FirstMemOp; 1343193323Sed 1344239462Sdim MCE.emitByte(BaseOpcode); 1345239462Sdim 1346193323Sed intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ? 1347203954Srdivacky X86II::getSizeOfImm(Desc->TSFlags) : 0; 1348239462Sdim emitMemModRMByte(MI, FirstMemOp, 1349243830Sdim getX86RegNum(MI.getOperand(CurOp).getReg()),PCAdj); 1350193323Sed CurOp += AddrOperands + 1; 1351239462Sdim if (HasVEX_4VOp3) 1352239462Sdim ++CurOp; 1353193323Sed break; 1354193323Sed } 1355193323Sed 1356193323Sed case X86II::MRM0r: case X86II::MRM1r: 1357193323Sed case X86II::MRM2r: case X86II::MRM3r: 1358193323Sed case X86II::MRM4r: case X86II::MRM5r: 1359193323Sed case X86II::MRM6r: case X86II::MRM7r: { 1360239462Sdim if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1361239462Sdim ++CurOp; 1362193323Sed MCE.emitByte(BaseOpcode); 1363203954Srdivacky emitRegModRMByte(MI.getOperand(CurOp++).getReg(), 1364203954Srdivacky (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r); 1365193323Sed 1366198090Srdivacky if (CurOp == NumOps) 1367198090Srdivacky break; 1368239462Sdim 1369198090Srdivacky const MachineOperand &MO1 = MI.getOperand(CurOp++); 1370203954Srdivacky unsigned Size = X86II::getSizeOfImm(Desc->TSFlags); 1371198090Srdivacky if (MO1.isImm()) { 1372198090Srdivacky emitConstant(MO1.getImm(), Size); 1373198090Srdivacky break; 1374193323Sed } 1375239462Sdim 1376198090Srdivacky unsigned rt = Is64BitMode ? X86::reloc_pcrel_word 1377198090Srdivacky : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); 1378198090Srdivacky if (Opcode == X86::MOV64ri32) 1379198090Srdivacky rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag? 1380198090Srdivacky if (MO1.isGlobal()) { 1381198090Srdivacky bool Indirect = gvNeedsNonLazyPtr(MO1, TM); 1382198090Srdivacky emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0, 1383199481Srdivacky Indirect); 1384198090Srdivacky } else if (MO1.isSymbol()) 1385198090Srdivacky emitExternalSymbolAddress(MO1.getSymbolName(), rt); 1386198090Srdivacky else if (MO1.isCPI()) 1387198090Srdivacky emitConstPoolAddress(MO1.getIndex(), rt); 1388198090Srdivacky else if (MO1.isJTI()) 1389198090Srdivacky emitJumpTableAddress(MO1.getIndex(), rt); 1390193323Sed break; 1391193323Sed } 1392193323Sed 1393193323Sed case X86II::MRM0m: case X86II::MRM1m: 1394193323Sed case X86II::MRM2m: case X86II::MRM3m: 1395193323Sed case X86II::MRM4m: case X86II::MRM5m: 1396193323Sed case X86II::MRM6m: case X86II::MRM7m: { 1397239462Sdim if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1398239462Sdim ++CurOp; 1399210299Sed intptr_t PCAdj = (CurOp + X86::AddrNumOperands != NumOps) ? 1400239462Sdim (MI.getOperand(CurOp+X86::AddrNumOperands).isImm() ? 1401203954Srdivacky X86II::getSizeOfImm(Desc->TSFlags) : 4) : 0; 1402193323Sed 1403193323Sed MCE.emitByte(BaseOpcode); 1404193323Sed emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m, 1405193323Sed PCAdj); 1406210299Sed CurOp += X86::AddrNumOperands; 1407193323Sed 1408198090Srdivacky if (CurOp == NumOps) 1409198090Srdivacky break; 1410239462Sdim 1411198090Srdivacky const MachineOperand &MO = MI.getOperand(CurOp++); 1412203954Srdivacky unsigned Size = X86II::getSizeOfImm(Desc->TSFlags); 1413198090Srdivacky if (MO.isImm()) { 1414198090Srdivacky emitConstant(MO.getImm(), Size); 1415198090Srdivacky break; 1416193323Sed } 1417239462Sdim 1418198090Srdivacky unsigned rt = Is64BitMode ? X86::reloc_pcrel_word 1419198090Srdivacky : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); 1420198090Srdivacky if (Opcode == X86::MOV64mi32) 1421198090Srdivacky rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag? 1422198090Srdivacky if (MO.isGlobal()) { 1423198090Srdivacky bool Indirect = gvNeedsNonLazyPtr(MO, TM); 1424198090Srdivacky emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0, 1425199481Srdivacky Indirect); 1426198090Srdivacky } else if (MO.isSymbol()) 1427198090Srdivacky emitExternalSymbolAddress(MO.getSymbolName(), rt); 1428198090Srdivacky else if (MO.isCPI()) 1429198090Srdivacky emitConstPoolAddress(MO.getIndex(), rt); 1430198090Srdivacky else if (MO.isJTI()) 1431198090Srdivacky emitJumpTableAddress(MO.getIndex(), rt); 1432193323Sed break; 1433193323Sed } 1434193323Sed 1435193323Sed case X86II::MRMInitReg: 1436193323Sed MCE.emitByte(BaseOpcode); 1437193323Sed // Duplicate register, used by things like MOV8r0 (aka xor reg,reg). 1438193323Sed emitRegModRMByte(MI.getOperand(CurOp).getReg(), 1439243830Sdim getX86RegNum(MI.getOperand(CurOp).getReg())); 1440193323Sed ++CurOp; 1441193323Sed break; 1442239462Sdim 1443203954Srdivacky case X86II::MRM_C1: 1444203954Srdivacky MCE.emitByte(BaseOpcode); 1445203954Srdivacky MCE.emitByte(0xC1); 1446203954Srdivacky break; 1447203954Srdivacky case X86II::MRM_C8: 1448203954Srdivacky MCE.emitByte(BaseOpcode); 1449203954Srdivacky MCE.emitByte(0xC8); 1450203954Srdivacky break; 1451203954Srdivacky case X86II::MRM_C9: 1452203954Srdivacky MCE.emitByte(BaseOpcode); 1453203954Srdivacky MCE.emitByte(0xC9); 1454203954Srdivacky break; 1455251662Sdim case X86II::MRM_CA: 1456251662Sdim MCE.emitByte(BaseOpcode); 1457251662Sdim MCE.emitByte(0xCA); 1458251662Sdim break; 1459251662Sdim case X86II::MRM_CB: 1460251662Sdim MCE.emitByte(BaseOpcode); 1461251662Sdim MCE.emitByte(0xCB); 1462251662Sdim break; 1463203954Srdivacky case X86II::MRM_E8: 1464203954Srdivacky MCE.emitByte(BaseOpcode); 1465203954Srdivacky MCE.emitByte(0xE8); 1466203954Srdivacky break; 1467203954Srdivacky case X86II::MRM_F0: 1468203954Srdivacky MCE.emitByte(BaseOpcode); 1469203954Srdivacky MCE.emitByte(0xF0); 1470203954Srdivacky break; 1471193323Sed } 1472193323Sed 1473239462Sdim while (CurOp != NumOps && NumOps - CurOp <= 2) { 1474239462Sdim // The last source register of a 4 operand instruction in AVX is encoded 1475239462Sdim // in bits[7:4] of a immediate byte. 1476239462Sdim if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) { 1477239462Sdim const MachineOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand 1478239462Sdim : CurOp); 1479239462Sdim ++CurOp; 1480243830Sdim unsigned RegNum = getX86RegNum(MO.getReg()) << 4; 1481239462Sdim if (X86II::isX86_64ExtendedReg(MO.getReg())) 1482239462Sdim RegNum |= 1 << 7; 1483239462Sdim // If there is an additional 5th operand it must be an immediate, which 1484239462Sdim // is encoded in bits[3:0] 1485239462Sdim if (CurOp != NumOps) { 1486239462Sdim const MachineOperand &MIMM = MI.getOperand(CurOp++); 1487239462Sdim if (MIMM.isImm()) { 1488239462Sdim unsigned Val = MIMM.getImm(); 1489239462Sdim assert(Val < 16 && "Immediate operand value out of range"); 1490239462Sdim RegNum |= Val; 1491239462Sdim } 1492239462Sdim } 1493239462Sdim emitConstant(RegNum, 1); 1494239462Sdim } else { 1495239462Sdim emitConstant(MI.getOperand(CurOp++).getImm(), 1496239462Sdim X86II::getSizeOfImm(Desc->TSFlags)); 1497239462Sdim } 1498239462Sdim } 1499239462Sdim 1500234353Sdim if (!MI.isVariadic() && CurOp != NumOps) { 1501198090Srdivacky#ifndef NDEBUG 1502202375Srdivacky dbgs() << "Cannot encode all operands of: " << MI << "\n"; 1503198090Srdivacky#endif 1504198090Srdivacky llvm_unreachable(0); 1505193323Sed } 1506198090Srdivacky 1507198090Srdivacky MCE.processDebugLoc(MI.getDebugLoc(), false); 1508193323Sed} 1509