Searched refs:CVMX_ADD_IO_SEG (Results 1 - 25 of 63) sorted by relevance

123

/freebsd-10.0-release/sys/contrib/octeon-sdk/
H A Dcvmx-pexp-defs.h59 return CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16;
62 #define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16)
70 return CVMX_ADD_IO_SEG(0x00011F0000008580ull);
73 #define CVMX_PEXP_NPEI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008580ull))
81 return CVMX_ADD_IO_SEG(0x00011F0000008680ull);
84 #define CVMX_PEXP_NPEI_BIST_STATUS2 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
92 return CVMX_ADD_IO_SEG(0x00011F0000008250ull);
95 #define CVMX_PEXP_NPEI_CTL_PORT0 (CVMX_ADD_IO_SEG(0x00011F0000008250ull))
103 return CVMX_ADD_IO_SEG(0x00011F0000008260ull);
106 #define CVMX_PEXP_NPEI_CTL_PORT1 (CVMX_ADD_IO_SEG(
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H A Dcvmx-spx0-defs.h61 return CVMX_ADD_IO_SEG(0x0001180090000388ull);
64 #define CVMX_SPX0_PLL_BW_CTL (CVMX_ADD_IO_SEG(0x0001180090000388ull))
72 return CVMX_ADD_IO_SEG(0x0001180090000380ull);
75 #define CVMX_SPX0_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180090000380ull))
H A Dcvmx-eoi-defs.h61 return CVMX_ADD_IO_SEG(0x0001180013000118ull);
64 #define CVMX_EOI_BIST_CTL_STA (CVMX_ADD_IO_SEG(0x0001180013000118ull))
72 return CVMX_ADD_IO_SEG(0x0001180013000000ull);
75 #define CVMX_EOI_CTL_STA (CVMX_ADD_IO_SEG(0x0001180013000000ull))
83 return CVMX_ADD_IO_SEG(0x0001180013000020ull);
86 #define CVMX_EOI_DEF_STA0 (CVMX_ADD_IO_SEG(0x0001180013000020ull))
94 return CVMX_ADD_IO_SEG(0x0001180013000028ull);
97 #define CVMX_EOI_DEF_STA1 (CVMX_ADD_IO_SEG(0x0001180013000028ull))
105 return CVMX_ADD_IO_SEG(0x0001180013000030ull);
108 #define CVMX_EOI_DEF_STA2 (CVMX_ADD_IO_SEG(
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H A Dcvmx-led-defs.h61 return CVMX_ADD_IO_SEG(0x0001180000001A48ull);
64 #define CVMX_LED_BLINK (CVMX_ADD_IO_SEG(0x0001180000001A48ull))
72 return CVMX_ADD_IO_SEG(0x0001180000001A08ull);
75 #define CVMX_LED_CLK_PHASE (CVMX_ADD_IO_SEG(0x0001180000001A08ull))
83 return CVMX_ADD_IO_SEG(0x0001180000001AF8ull);
86 #define CVMX_LED_CYLON (CVMX_ADD_IO_SEG(0x0001180000001AF8ull))
94 return CVMX_ADD_IO_SEG(0x0001180000001A18ull);
97 #define CVMX_LED_DBG (CVMX_ADD_IO_SEG(0x0001180000001A18ull))
105 return CVMX_ADD_IO_SEG(0x0001180000001A00ull);
108 #define CVMX_LED_EN (CVMX_ADD_IO_SEG(
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H A Dcvmx-gmxx-defs.h65 return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 0) * 0x8000000ull;
73 return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 1) * 0x8000000ull;
77 return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 7) * 0x1000000ull;
81 return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 0) * 0x8000000ull;
93 return CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 0) * 0x8000000ull;
101 return CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 1) * 0x8000000ull;
105 return CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 7) * 0x1000000ull;
109 return CVMX_ADD_IO_SEG(0x0001180008000400ull) + ((block_id) & 0) * 0x8000000ull;
117 return CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 15) + ((block_id) & 7) * 0x200000ull) * 8;
120 #define CVMX_GMXX_BPID_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(
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H A Dcvmx-endor-defs.h61 return CVMX_ADD_IO_SEG(0x00010F0000844004ull);
64 #define CVMX_ENDOR_ADMA_AUTO_CLK_GATE (CVMX_ADD_IO_SEG(0x00010F0000844004ull))
72 return CVMX_ADD_IO_SEG(0x00010F0000844044ull);
75 #define CVMX_ENDOR_ADMA_AXIERR_INTR (CVMX_ADD_IO_SEG(0x00010F0000844044ull))
83 return CVMX_ADD_IO_SEG(0x00010F0000844050ull);
86 #define CVMX_ENDOR_ADMA_AXI_RSPCODE (CVMX_ADD_IO_SEG(0x00010F0000844050ull))
94 return CVMX_ADD_IO_SEG(0x00010F0000844084ull);
97 #define CVMX_ENDOR_ADMA_AXI_SIGNAL (CVMX_ADD_IO_SEG(0x00010F0000844084ull))
105 return CVMX_ADD_IO_SEG(0x00010F0000844040ull);
108 #define CVMX_ENDOR_ADMA_DMADONE_INTR (CVMX_ADD_IO_SEG(
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H A Dcvmx-iob1-defs.h61 return CVMX_ADD_IO_SEG(0x00011800F00107F8ull);
64 #define CVMX_IOB1_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00107F8ull))
72 return CVMX_ADD_IO_SEG(0x00011800F0010050ull);
75 #define CVMX_IOB1_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0010050ull))
83 return CVMX_ADD_IO_SEG(0x00011800F00100B0ull);
86 #define CVMX_IOB1_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00100B0ull))
H A Dcvmx-stxx-defs.h62 return CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull;
65 #define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull)
74 return CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull;
77 #define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull)
86 return CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull;
89 #define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull)
98 return CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull;
101 #define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull)
110 return CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull;
113 #define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(
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H A Dcvmx-zip-defs.h61 return CVMX_ADD_IO_SEG(0x0001180038000080ull);
64 #define CVMX_ZIP_CMD_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180038000080ull))
72 return CVMX_ADD_IO_SEG(0x0001180038000008ull);
75 #define CVMX_ZIP_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180038000008ull))
83 return CVMX_ADD_IO_SEG(0x0001180038000000ull);
86 #define CVMX_ZIP_CMD_CTL (CVMX_ADD_IO_SEG(0x0001180038000000ull))
94 return CVMX_ADD_IO_SEG(0x00011800380000A0ull);
97 #define CVMX_ZIP_CONSTANTS (CVMX_ADD_IO_SEG(0x00011800380000A0ull))
105 return CVMX_ADD_IO_SEG(0x0001180038000520ull) + ((offset) & 1) * 8;
108 #define CVMX_ZIP_COREX_BIST_STATUS(offset) (CVMX_ADD_IO_SEG(
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H A Dcvmx-sso-defs.h61 return CVMX_ADD_IO_SEG(0x00016700000010E8ull);
64 #define CVMX_SSO_ACTIVE_CYCLES (CVMX_ADD_IO_SEG(0x00016700000010E8ull))
72 return CVMX_ADD_IO_SEG(0x0001670000001078ull);
75 #define CVMX_SSO_BIST_STAT (CVMX_ADD_IO_SEG(0x0001670000001078ull))
83 return CVMX_ADD_IO_SEG(0x0001670000001088ull);
86 #define CVMX_SSO_CFG (CVMX_ADD_IO_SEG(0x0001670000001088ull))
94 return CVMX_ADD_IO_SEG(0x0001670000001070ull);
97 #define CVMX_SSO_DS_PC (CVMX_ADD_IO_SEG(0x0001670000001070ull))
105 return CVMX_ADD_IO_SEG(0x0001670000001038ull);
108 #define CVMX_SSO_ERR (CVMX_ADD_IO_SEG(
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H A Dcvmx-pcsx-defs.h60 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
65 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
71 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
75 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
79 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
86 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
91 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
97 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
101 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
105 return CVMX_ADD_IO_SEG(
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H A Dcvmx-asx0-defs.h61 return CVMX_ADD_IO_SEG(0x00011800B0000208ull);
64 #define CVMX_ASX0_DBG_DATA_DRV (CVMX_ADD_IO_SEG(0x00011800B0000208ull))
72 return CVMX_ADD_IO_SEG(0x00011800B0000200ull);
75 #define CVMX_ASX0_DBG_DATA_ENABLE (CVMX_ADD_IO_SEG(0x00011800B0000200ull))
H A Dcvmx-smix-defs.h64 return CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 0) * 256;
73 return CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256;
77 return CVMX_ADD_IO_SEG(0x0001180000003818ull) + ((offset) & 3) * 128;
81 return CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256;
92 return CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 0) * 256;
101 return CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256;
105 return CVMX_ADD_IO_SEG(0x0001180000003800ull) + ((offset) & 3) * 128;
109 return CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256;
120 return CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 0) * 256;
129 return CVMX_ADD_IO_SEG(
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H A Dcvmx-pcsxx-defs.h62 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 1) * 0x8000000ull;
67 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 0) * 0x8000000ull;
71 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 7) * 0x1000000ull;
75 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 7) * 0x1000000ull;
84 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 1) * 0x8000000ull;
89 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 0) * 0x8000000ull;
93 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 7) * 0x1000000ull;
97 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 7) * 0x1000000ull;
106 return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 1) * 0x8000000ull;
111 return CVMX_ADD_IO_SEG(
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H A Dcvmx-tim-defs.h61 return CVMX_ADD_IO_SEG(0x0001180058000020ull);
64 #define CVMX_TIM_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180058000020ull))
72 return CVMX_ADD_IO_SEG(0x00011800580000A0ull);
75 #define CVMX_TIM_DBG2 (CVMX_ADD_IO_SEG(0x00011800580000A0ull))
83 return CVMX_ADD_IO_SEG(0x00011800580000A8ull);
86 #define CVMX_TIM_DBG3 (CVMX_ADD_IO_SEG(0x00011800580000A8ull))
94 return CVMX_ADD_IO_SEG(0x0001180058000018ull);
97 #define CVMX_TIM_ECC_CFG (CVMX_ADD_IO_SEG(0x0001180058000018ull))
105 return CVMX_ADD_IO_SEG(0x0001180058000010ull);
108 #define CVMX_TIM_FR_RN_TT (CVMX_ADD_IO_SEG(
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H A Dcvmx-pcm-defs.h65 return CVMX_ADD_IO_SEG(0x0001070000010000ull) + ((offset) & 1) * 16384;
68 #define CVMX_PCM_CLKX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001070000010000ull) + ((offset) & 1) * 16384)
80 return CVMX_ADD_IO_SEG(0x0001070000010038ull) + ((offset) & 1) * 16384;
83 #define CVMX_PCM_CLKX_DBG(offset) (CVMX_ADD_IO_SEG(0x0001070000010038ull) + ((offset) & 1) * 16384)
95 return CVMX_ADD_IO_SEG(0x0001070000010008ull) + ((offset) & 1) * 16384;
98 #define CVMX_PCM_CLKX_GEN(offset) (CVMX_ADD_IO_SEG(0x0001070000010008ull) + ((offset) & 1) * 16384)
H A Dcvmx-pcmx-defs.h65 return CVMX_ADD_IO_SEG(0x0001070000010018ull) + ((offset) & 3) * 16384;
68 #define CVMX_PCMX_DMA_CFG(offset) (CVMX_ADD_IO_SEG(0x0001070000010018ull) + ((offset) & 3) * 16384)
80 return CVMX_ADD_IO_SEG(0x0001070000010020ull) + ((offset) & 3) * 16384;
83 #define CVMX_PCMX_INT_ENA(offset) (CVMX_ADD_IO_SEG(0x0001070000010020ull) + ((offset) & 3) * 16384)
95 return CVMX_ADD_IO_SEG(0x0001070000010028ull) + ((offset) & 3) * 16384;
98 #define CVMX_PCMX_INT_SUM(offset) (CVMX_ADD_IO_SEG(0x0001070000010028ull) + ((offset) & 3) * 16384)
110 return CVMX_ADD_IO_SEG(0x0001070000010068ull) + ((offset) & 3) * 16384;
113 #define CVMX_PCMX_RXADDR(offset) (CVMX_ADD_IO_SEG(0x0001070000010068ull) + ((offset) & 3) * 16384)
125 return CVMX_ADD_IO_SEG(0x0001070000010060ull) + ((offset) & 3) * 16384;
128 #define CVMX_PCMX_RXCNT(offset) (CVMX_ADD_IO_SEG(
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H A Dcvmx-asxx-defs.h63 return CVMX_ADD_IO_SEG(0x00011800B0000180ull);
66 #define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull))
76 return CVMX_ADD_IO_SEG(0x00011800B0000188ull);
79 #define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull))
91 return CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull;
94 #define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull)
106 return CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull;
109 #define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull)
118 return CVMX_ADD_IO_SEG(0x00011800B0000190ull);
121 #define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(
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H A Dcvmx-ilk-defs.h61 return CVMX_ADD_IO_SEG(0x0001180014000038ull);
64 #define CVMX_ILK_BIST_SUM (CVMX_ADD_IO_SEG(0x0001180014000038ull))
72 return CVMX_ADD_IO_SEG(0x0001180014000000ull);
75 #define CVMX_ILK_GBL_CFG (CVMX_ADD_IO_SEG(0x0001180014000000ull))
83 return CVMX_ADD_IO_SEG(0x0001180014000008ull);
86 #define CVMX_ILK_GBL_INT (CVMX_ADD_IO_SEG(0x0001180014000008ull))
94 return CVMX_ADD_IO_SEG(0x0001180014000010ull);
97 #define CVMX_ILK_GBL_INT_EN (CVMX_ADD_IO_SEG(0x0001180014000010ull))
105 return CVMX_ADD_IO_SEG(0x0001180014000030ull);
108 #define CVMX_ILK_INT_SUM (CVMX_ADD_IO_SEG(
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H A Dcvmx-dfm-defs.h61 return CVMX_ADD_IO_SEG(0x00011800D4000220ull);
64 #define CVMX_DFM_CHAR_CTL (CVMX_ADD_IO_SEG(0x00011800D4000220ull))
72 return CVMX_ADD_IO_SEG(0x00011800D4000228ull);
75 #define CVMX_DFM_CHAR_MASK0 (CVMX_ADD_IO_SEG(0x00011800D4000228ull))
83 return CVMX_ADD_IO_SEG(0x00011800D4000238ull);
86 #define CVMX_DFM_CHAR_MASK2 (CVMX_ADD_IO_SEG(0x00011800D4000238ull))
94 return CVMX_ADD_IO_SEG(0x00011800D4000318ull);
97 #define CVMX_DFM_CHAR_MASK4 (CVMX_ADD_IO_SEG(0x00011800D4000318ull))
105 return CVMX_ADD_IO_SEG(0x00011800D40001B8ull);
108 #define CVMX_DFM_COMP_CTL2 (CVMX_ADD_IO_SEG(
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H A Dcvmx-key-defs.h61 return CVMX_ADD_IO_SEG(0x0001180020000018ull);
64 #define CVMX_KEY_BIST_REG (CVMX_ADD_IO_SEG(0x0001180020000018ull))
72 return CVMX_ADD_IO_SEG(0x0001180020000010ull);
75 #define CVMX_KEY_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180020000010ull))
83 return CVMX_ADD_IO_SEG(0x0001180020000008ull);
86 #define CVMX_KEY_INT_ENB (CVMX_ADD_IO_SEG(0x0001180020000008ull))
94 return CVMX_ADD_IO_SEG(0x0001180020000000ull);
97 #define CVMX_KEY_INT_SUM (CVMX_ADD_IO_SEG(0x0001180020000000ull))
H A Dcvmx-smi-defs.h61 return CVMX_ADD_IO_SEG(0x0001180000001828ull);
64 #define CVMX_SMI_DRV_CTL (CVMX_ADD_IO_SEG(0x0001180000001828ull))
H A Dcvmx-spxx-defs.h62 return CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull;
65 #define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull)
74 return CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull;
77 #define CVMX_SPXX_BIST_STAT(block_id) (CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull)
86 return CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull;
89 #define CVMX_SPXX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull)
98 return CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull;
101 #define CVMX_SPXX_CLK_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull)
110 return CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull;
113 #define CVMX_SPXX_DBG_DESKEW_CTL(block_id) (CVMX_ADD_IO_SEG(
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H A Dcvmx-ndf-defs.h61 return CVMX_ADD_IO_SEG(0x0001070001000018ull);
64 #define CVMX_NDF_BT_PG_INFO (CVMX_ADD_IO_SEG(0x0001070001000018ull))
72 return CVMX_ADD_IO_SEG(0x0001070001000000ull);
75 #define CVMX_NDF_CMD (CVMX_ADD_IO_SEG(0x0001070001000000ull))
83 return CVMX_ADD_IO_SEG(0x0001070001000030ull);
86 #define CVMX_NDF_DRBELL (CVMX_ADD_IO_SEG(0x0001070001000030ull))
94 return CVMX_ADD_IO_SEG(0x0001070001000010ull);
97 #define CVMX_NDF_ECC_CNT (CVMX_ADD_IO_SEG(0x0001070001000010ull))
105 return CVMX_ADD_IO_SEG(0x0001070001000020ull);
108 #define CVMX_NDF_INT (CVMX_ADD_IO_SEG(
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H A Dcvmx-srxx-defs.h62 return CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull;
65 #define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull)
74 return CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull;
77 #define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull)
86 return CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8;
89 #define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
98 return CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull;
101 #define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull)
110 return CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull;
113 #define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(
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