1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-tim-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon tim. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_TIM_DEFS_H__ 53232812Sjmallett#define __CVMX_TIM_DEFS_H__ 54215976Sjmallett 55232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56232812Sjmallett#define CVMX_TIM_BIST_RESULT CVMX_TIM_BIST_RESULT_FUNC() 57232812Sjmallettstatic inline uint64_t CVMX_TIM_BIST_RESULT_FUNC(void) 58232812Sjmallett{ 59232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 60232812Sjmallett cvmx_warn("CVMX_TIM_BIST_RESULT not supported on this chip\n"); 61232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058000020ull); 62232812Sjmallett} 63232812Sjmallett#else 64232812Sjmallett#define CVMX_TIM_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180058000020ull)) 65232812Sjmallett#endif 66232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67232812Sjmallett#define CVMX_TIM_DBG2 CVMX_TIM_DBG2_FUNC() 68232812Sjmallettstatic inline uint64_t CVMX_TIM_DBG2_FUNC(void) 69232812Sjmallett{ 70232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 71232812Sjmallett cvmx_warn("CVMX_TIM_DBG2 not supported on this chip\n"); 72232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800580000A0ull); 73232812Sjmallett} 74232812Sjmallett#else 75232812Sjmallett#define CVMX_TIM_DBG2 (CVMX_ADD_IO_SEG(0x00011800580000A0ull)) 76232812Sjmallett#endif 77232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78232812Sjmallett#define CVMX_TIM_DBG3 CVMX_TIM_DBG3_FUNC() 79232812Sjmallettstatic inline uint64_t CVMX_TIM_DBG3_FUNC(void) 80232812Sjmallett{ 81232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 82232812Sjmallett cvmx_warn("CVMX_TIM_DBG3 not supported on this chip\n"); 83232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800580000A8ull); 84232812Sjmallett} 85232812Sjmallett#else 86232812Sjmallett#define CVMX_TIM_DBG3 (CVMX_ADD_IO_SEG(0x00011800580000A8ull)) 87232812Sjmallett#endif 88232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89232812Sjmallett#define CVMX_TIM_ECC_CFG CVMX_TIM_ECC_CFG_FUNC() 90232812Sjmallettstatic inline uint64_t CVMX_TIM_ECC_CFG_FUNC(void) 91232812Sjmallett{ 92232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 93232812Sjmallett cvmx_warn("CVMX_TIM_ECC_CFG not supported on this chip\n"); 94232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058000018ull); 95232812Sjmallett} 96232812Sjmallett#else 97232812Sjmallett#define CVMX_TIM_ECC_CFG (CVMX_ADD_IO_SEG(0x0001180058000018ull)) 98232812Sjmallett#endif 99232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100232812Sjmallett#define CVMX_TIM_FR_RN_TT CVMX_TIM_FR_RN_TT_FUNC() 101232812Sjmallettstatic inline uint64_t CVMX_TIM_FR_RN_TT_FUNC(void) 102232812Sjmallett{ 103232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 104232812Sjmallett cvmx_warn("CVMX_TIM_FR_RN_TT not supported on this chip\n"); 105232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058000010ull); 106232812Sjmallett} 107232812Sjmallett#else 108232812Sjmallett#define CVMX_TIM_FR_RN_TT (CVMX_ADD_IO_SEG(0x0001180058000010ull)) 109232812Sjmallett#endif 110232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111232812Sjmallett#define CVMX_TIM_GPIO_EN CVMX_TIM_GPIO_EN_FUNC() 112232812Sjmallettstatic inline uint64_t CVMX_TIM_GPIO_EN_FUNC(void) 113232812Sjmallett{ 114232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 115232812Sjmallett cvmx_warn("CVMX_TIM_GPIO_EN not supported on this chip\n"); 116232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058000080ull); 117232812Sjmallett} 118232812Sjmallett#else 119232812Sjmallett#define CVMX_TIM_GPIO_EN (CVMX_ADD_IO_SEG(0x0001180058000080ull)) 120232812Sjmallett#endif 121232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122232812Sjmallett#define CVMX_TIM_INT0 CVMX_TIM_INT0_FUNC() 123232812Sjmallettstatic inline uint64_t CVMX_TIM_INT0_FUNC(void) 124232812Sjmallett{ 125232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 126232812Sjmallett cvmx_warn("CVMX_TIM_INT0 not supported on this chip\n"); 127232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058000030ull); 128232812Sjmallett} 129232812Sjmallett#else 130232812Sjmallett#define CVMX_TIM_INT0 (CVMX_ADD_IO_SEG(0x0001180058000030ull)) 131232812Sjmallett#endif 132232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133232812Sjmallett#define CVMX_TIM_INT0_EN CVMX_TIM_INT0_EN_FUNC() 134232812Sjmallettstatic inline uint64_t CVMX_TIM_INT0_EN_FUNC(void) 135232812Sjmallett{ 136232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 137232812Sjmallett cvmx_warn("CVMX_TIM_INT0_EN not supported on this chip\n"); 138232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058000038ull); 139232812Sjmallett} 140232812Sjmallett#else 141232812Sjmallett#define CVMX_TIM_INT0_EN (CVMX_ADD_IO_SEG(0x0001180058000038ull)) 142232812Sjmallett#endif 143232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144232812Sjmallett#define CVMX_TIM_INT0_EVENT CVMX_TIM_INT0_EVENT_FUNC() 145232812Sjmallettstatic inline uint64_t CVMX_TIM_INT0_EVENT_FUNC(void) 146232812Sjmallett{ 147232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 148232812Sjmallett cvmx_warn("CVMX_TIM_INT0_EVENT not supported on this chip\n"); 149232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058000040ull); 150232812Sjmallett} 151232812Sjmallett#else 152232812Sjmallett#define CVMX_TIM_INT0_EVENT (CVMX_ADD_IO_SEG(0x0001180058000040ull)) 153232812Sjmallett#endif 154232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155232812Sjmallett#define CVMX_TIM_INT_ECCERR CVMX_TIM_INT_ECCERR_FUNC() 156232812Sjmallettstatic inline uint64_t CVMX_TIM_INT_ECCERR_FUNC(void) 157232812Sjmallett{ 158232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 159232812Sjmallett cvmx_warn("CVMX_TIM_INT_ECCERR not supported on this chip\n"); 160232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058000060ull); 161232812Sjmallett} 162232812Sjmallett#else 163232812Sjmallett#define CVMX_TIM_INT_ECCERR (CVMX_ADD_IO_SEG(0x0001180058000060ull)) 164232812Sjmallett#endif 165232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166232812Sjmallett#define CVMX_TIM_INT_ECCERR_EN CVMX_TIM_INT_ECCERR_EN_FUNC() 167232812Sjmallettstatic inline uint64_t CVMX_TIM_INT_ECCERR_EN_FUNC(void) 168232812Sjmallett{ 169232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 170232812Sjmallett cvmx_warn("CVMX_TIM_INT_ECCERR_EN not supported on this chip\n"); 171232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058000068ull); 172232812Sjmallett} 173232812Sjmallett#else 174232812Sjmallett#define CVMX_TIM_INT_ECCERR_EN (CVMX_ADD_IO_SEG(0x0001180058000068ull)) 175232812Sjmallett#endif 176232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177232812Sjmallett#define CVMX_TIM_INT_ECCERR_EVENT0 CVMX_TIM_INT_ECCERR_EVENT0_FUNC() 178232812Sjmallettstatic inline uint64_t CVMX_TIM_INT_ECCERR_EVENT0_FUNC(void) 179232812Sjmallett{ 180232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 181232812Sjmallett cvmx_warn("CVMX_TIM_INT_ECCERR_EVENT0 not supported on this chip\n"); 182232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058000070ull); 183232812Sjmallett} 184232812Sjmallett#else 185232812Sjmallett#define CVMX_TIM_INT_ECCERR_EVENT0 (CVMX_ADD_IO_SEG(0x0001180058000070ull)) 186232812Sjmallett#endif 187232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188232812Sjmallett#define CVMX_TIM_INT_ECCERR_EVENT1 CVMX_TIM_INT_ECCERR_EVENT1_FUNC() 189232812Sjmallettstatic inline uint64_t CVMX_TIM_INT_ECCERR_EVENT1_FUNC(void) 190232812Sjmallett{ 191232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 192232812Sjmallett cvmx_warn("CVMX_TIM_INT_ECCERR_EVENT1 not supported on this chip\n"); 193232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058000078ull); 194232812Sjmallett} 195232812Sjmallett#else 196232812Sjmallett#define CVMX_TIM_INT_ECCERR_EVENT1 (CVMX_ADD_IO_SEG(0x0001180058000078ull)) 197232812Sjmallett#endif 198232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199232812Sjmallett#define CVMX_TIM_MEM_DEBUG0 CVMX_TIM_MEM_DEBUG0_FUNC() 200232812Sjmallettstatic inline uint64_t CVMX_TIM_MEM_DEBUG0_FUNC(void) 201232812Sjmallett{ 202232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 203232812Sjmallett cvmx_warn("CVMX_TIM_MEM_DEBUG0 not supported on this chip\n"); 204232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058001100ull); 205232812Sjmallett} 206232812Sjmallett#else 207215976Sjmallett#define CVMX_TIM_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180058001100ull)) 208232812Sjmallett#endif 209232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210232812Sjmallett#define CVMX_TIM_MEM_DEBUG1 CVMX_TIM_MEM_DEBUG1_FUNC() 211232812Sjmallettstatic inline uint64_t CVMX_TIM_MEM_DEBUG1_FUNC(void) 212232812Sjmallett{ 213232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 214232812Sjmallett cvmx_warn("CVMX_TIM_MEM_DEBUG1 not supported on this chip\n"); 215232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058001108ull); 216232812Sjmallett} 217232812Sjmallett#else 218215976Sjmallett#define CVMX_TIM_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180058001108ull)) 219232812Sjmallett#endif 220232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221232812Sjmallett#define CVMX_TIM_MEM_DEBUG2 CVMX_TIM_MEM_DEBUG2_FUNC() 222232812Sjmallettstatic inline uint64_t CVMX_TIM_MEM_DEBUG2_FUNC(void) 223232812Sjmallett{ 224232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 225232812Sjmallett cvmx_warn("CVMX_TIM_MEM_DEBUG2 not supported on this chip\n"); 226232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058001110ull); 227232812Sjmallett} 228232812Sjmallett#else 229215976Sjmallett#define CVMX_TIM_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180058001110ull)) 230232812Sjmallett#endif 231232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232232812Sjmallett#define CVMX_TIM_MEM_RING0 CVMX_TIM_MEM_RING0_FUNC() 233232812Sjmallettstatic inline uint64_t CVMX_TIM_MEM_RING0_FUNC(void) 234232812Sjmallett{ 235232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 236232812Sjmallett cvmx_warn("CVMX_TIM_MEM_RING0 not supported on this chip\n"); 237232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058001000ull); 238232812Sjmallett} 239232812Sjmallett#else 240215976Sjmallett#define CVMX_TIM_MEM_RING0 (CVMX_ADD_IO_SEG(0x0001180058001000ull)) 241232812Sjmallett#endif 242232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243232812Sjmallett#define CVMX_TIM_MEM_RING1 CVMX_TIM_MEM_RING1_FUNC() 244232812Sjmallettstatic inline uint64_t CVMX_TIM_MEM_RING1_FUNC(void) 245232812Sjmallett{ 246232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 247232812Sjmallett cvmx_warn("CVMX_TIM_MEM_RING1 not supported on this chip\n"); 248232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058001008ull); 249232812Sjmallett} 250232812Sjmallett#else 251215976Sjmallett#define CVMX_TIM_MEM_RING1 (CVMX_ADD_IO_SEG(0x0001180058001008ull)) 252232812Sjmallett#endif 253232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254232812Sjmallett#define CVMX_TIM_REG_BIST_RESULT CVMX_TIM_REG_BIST_RESULT_FUNC() 255232812Sjmallettstatic inline uint64_t CVMX_TIM_REG_BIST_RESULT_FUNC(void) 256232812Sjmallett{ 257232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 258232812Sjmallett cvmx_warn("CVMX_TIM_REG_BIST_RESULT not supported on this chip\n"); 259232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058000080ull); 260232812Sjmallett} 261232812Sjmallett#else 262215976Sjmallett#define CVMX_TIM_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180058000080ull)) 263232812Sjmallett#endif 264232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265232812Sjmallett#define CVMX_TIM_REG_ERROR CVMX_TIM_REG_ERROR_FUNC() 266232812Sjmallettstatic inline uint64_t CVMX_TIM_REG_ERROR_FUNC(void) 267232812Sjmallett{ 268232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 269232812Sjmallett cvmx_warn("CVMX_TIM_REG_ERROR not supported on this chip\n"); 270232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058000088ull); 271232812Sjmallett} 272232812Sjmallett#else 273215976Sjmallett#define CVMX_TIM_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180058000088ull)) 274232812Sjmallett#endif 275215976Sjmallett#define CVMX_TIM_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180058000000ull)) 276232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 277232812Sjmallett#define CVMX_TIM_REG_INT_MASK CVMX_TIM_REG_INT_MASK_FUNC() 278232812Sjmallettstatic inline uint64_t CVMX_TIM_REG_INT_MASK_FUNC(void) 279232812Sjmallett{ 280232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 281232812Sjmallett cvmx_warn("CVMX_TIM_REG_INT_MASK not supported on this chip\n"); 282232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058000090ull); 283232812Sjmallett} 284232812Sjmallett#else 285215976Sjmallett#define CVMX_TIM_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180058000090ull)) 286232812Sjmallett#endif 287232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 288232812Sjmallett#define CVMX_TIM_REG_READ_IDX CVMX_TIM_REG_READ_IDX_FUNC() 289232812Sjmallettstatic inline uint64_t CVMX_TIM_REG_READ_IDX_FUNC(void) 290232812Sjmallett{ 291232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 292232812Sjmallett cvmx_warn("CVMX_TIM_REG_READ_IDX not supported on this chip\n"); 293232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058000008ull); 294232812Sjmallett} 295232812Sjmallett#else 296215976Sjmallett#define CVMX_TIM_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180058000008ull)) 297232812Sjmallett#endif 298232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 299232812Sjmallettstatic inline uint64_t CVMX_TIM_RINGX_CTL0(unsigned long offset) 300232812Sjmallett{ 301232812Sjmallett if (!( 302232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 303232812Sjmallett cvmx_warn("CVMX_TIM_RINGX_CTL0(%lu) is invalid on this chip\n", offset); 304232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058002000ull) + ((offset) & 63) * 8; 305232812Sjmallett} 306232812Sjmallett#else 307232812Sjmallett#define CVMX_TIM_RINGX_CTL0(offset) (CVMX_ADD_IO_SEG(0x0001180058002000ull) + ((offset) & 63) * 8) 308232812Sjmallett#endif 309232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 310232812Sjmallettstatic inline uint64_t CVMX_TIM_RINGX_CTL1(unsigned long offset) 311232812Sjmallett{ 312232812Sjmallett if (!( 313232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 314232812Sjmallett cvmx_warn("CVMX_TIM_RINGX_CTL1(%lu) is invalid on this chip\n", offset); 315232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058002400ull) + ((offset) & 63) * 8; 316232812Sjmallett} 317232812Sjmallett#else 318232812Sjmallett#define CVMX_TIM_RINGX_CTL1(offset) (CVMX_ADD_IO_SEG(0x0001180058002400ull) + ((offset) & 63) * 8) 319232812Sjmallett#endif 320232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 321232812Sjmallettstatic inline uint64_t CVMX_TIM_RINGX_CTL2(unsigned long offset) 322232812Sjmallett{ 323232812Sjmallett if (!( 324232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 325232812Sjmallett cvmx_warn("CVMX_TIM_RINGX_CTL2(%lu) is invalid on this chip\n", offset); 326232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058002800ull) + ((offset) & 63) * 8; 327232812Sjmallett} 328232812Sjmallett#else 329232812Sjmallett#define CVMX_TIM_RINGX_CTL2(offset) (CVMX_ADD_IO_SEG(0x0001180058002800ull) + ((offset) & 63) * 8) 330232812Sjmallett#endif 331232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 332232812Sjmallettstatic inline uint64_t CVMX_TIM_RINGX_DBG0(unsigned long offset) 333232812Sjmallett{ 334232812Sjmallett if (!( 335232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 336232812Sjmallett cvmx_warn("CVMX_TIM_RINGX_DBG0(%lu) is invalid on this chip\n", offset); 337232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058003000ull) + ((offset) & 63) * 8; 338232812Sjmallett} 339232812Sjmallett#else 340232812Sjmallett#define CVMX_TIM_RINGX_DBG0(offset) (CVMX_ADD_IO_SEG(0x0001180058003000ull) + ((offset) & 63) * 8) 341232812Sjmallett#endif 342232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 343232812Sjmallettstatic inline uint64_t CVMX_TIM_RINGX_DBG1(unsigned long offset) 344232812Sjmallett{ 345232812Sjmallett if (!( 346232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 347232812Sjmallett cvmx_warn("CVMX_TIM_RINGX_DBG1(%lu) is invalid on this chip\n", offset); 348232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180058001200ull) + ((offset) & 63) * 8; 349232812Sjmallett} 350232812Sjmallett#else 351232812Sjmallett#define CVMX_TIM_RINGX_DBG1(offset) (CVMX_ADD_IO_SEG(0x0001180058001200ull) + ((offset) & 63) * 8) 352232812Sjmallett#endif 353215976Sjmallett 354215976Sjmallett/** 355232812Sjmallett * cvmx_tim_bist_result 356232812Sjmallett * 357232812Sjmallett * Notes: 358232812Sjmallett * Access to the internal BiST results 359232812Sjmallett * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail). 360232812Sjmallett */ 361232812Sjmallettunion cvmx_tim_bist_result { 362232812Sjmallett uint64_t u64; 363232812Sjmallett struct cvmx_tim_bist_result_s { 364232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 365232812Sjmallett uint64_t reserved_3_63 : 61; 366232812Sjmallett uint64_t wqe_fifo : 1; /**< BIST result of the NCB_WQE FIFO (0=pass, !0=fail) */ 367232812Sjmallett uint64_t lslr_fifo : 1; /**< BIST result of the NCB_LSLR FIFO (0=pass, !0=fail) */ 368232812Sjmallett uint64_t rds_mem : 1; /**< BIST result of the RDS memory (0=pass, !0=fail) */ 369232812Sjmallett#else 370232812Sjmallett uint64_t rds_mem : 1; 371232812Sjmallett uint64_t lslr_fifo : 1; 372232812Sjmallett uint64_t wqe_fifo : 1; 373232812Sjmallett uint64_t reserved_3_63 : 61; 374232812Sjmallett#endif 375232812Sjmallett } s; 376232812Sjmallett struct cvmx_tim_bist_result_s cn68xx; 377232812Sjmallett struct cvmx_tim_bist_result_s cn68xxp1; 378232812Sjmallett}; 379232812Sjmalletttypedef union cvmx_tim_bist_result cvmx_tim_bist_result_t; 380232812Sjmallett 381232812Sjmallett/** 382232812Sjmallett * cvmx_tim_dbg2 383232812Sjmallett */ 384232812Sjmallettunion cvmx_tim_dbg2 { 385232812Sjmallett uint64_t u64; 386232812Sjmallett struct cvmx_tim_dbg2_s { 387232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 388232812Sjmallett uint64_t mem_alloc_reg : 8; /**< NCB Load Memory Allocation status */ 389232812Sjmallett uint64_t reserved_51_55 : 5; 390232812Sjmallett uint64_t gnt_fifo_level : 3; /**< NCB GRANT FIFO level */ 391232812Sjmallett uint64_t reserved_45_47 : 3; 392232812Sjmallett uint64_t rwf_fifo_level : 5; /**< NCB requests FIFO level */ 393232812Sjmallett uint64_t wqe_fifo_level : 8; /**< NCB WQE LD FIFO level */ 394232812Sjmallett uint64_t reserved_16_31 : 16; 395232812Sjmallett uint64_t fsm3_state : 4; /**< FSM 3 current state */ 396232812Sjmallett uint64_t fsm2_state : 4; /**< FSM 2 current state */ 397232812Sjmallett uint64_t fsm1_state : 4; /**< FSM 1 current state */ 398232812Sjmallett uint64_t fsm0_state : 4; /**< FSM 0 current state */ 399232812Sjmallett#else 400232812Sjmallett uint64_t fsm0_state : 4; 401232812Sjmallett uint64_t fsm1_state : 4; 402232812Sjmallett uint64_t fsm2_state : 4; 403232812Sjmallett uint64_t fsm3_state : 4; 404232812Sjmallett uint64_t reserved_16_31 : 16; 405232812Sjmallett uint64_t wqe_fifo_level : 8; 406232812Sjmallett uint64_t rwf_fifo_level : 5; 407232812Sjmallett uint64_t reserved_45_47 : 3; 408232812Sjmallett uint64_t gnt_fifo_level : 3; 409232812Sjmallett uint64_t reserved_51_55 : 5; 410232812Sjmallett uint64_t mem_alloc_reg : 8; 411232812Sjmallett#endif 412232812Sjmallett } s; 413232812Sjmallett struct cvmx_tim_dbg2_s cn68xx; 414232812Sjmallett struct cvmx_tim_dbg2_s cn68xxp1; 415232812Sjmallett}; 416232812Sjmalletttypedef union cvmx_tim_dbg2 cvmx_tim_dbg2_t; 417232812Sjmallett 418232812Sjmallett/** 419232812Sjmallett * cvmx_tim_dbg3 420232812Sjmallett */ 421232812Sjmallettunion cvmx_tim_dbg3 { 422232812Sjmallett uint64_t u64; 423232812Sjmallett struct cvmx_tim_dbg3_s { 424232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 425232812Sjmallett uint64_t rings_pending_vec : 64; /**< Pending rings vector. Indicates which ring in TIM are 426232812Sjmallett pending traversal. Bit 0 represents ring 0 while bit 63 427232812Sjmallett represents ring 63. */ 428232812Sjmallett#else 429232812Sjmallett uint64_t rings_pending_vec : 64; 430232812Sjmallett#endif 431232812Sjmallett } s; 432232812Sjmallett struct cvmx_tim_dbg3_s cn68xx; 433232812Sjmallett struct cvmx_tim_dbg3_s cn68xxp1; 434232812Sjmallett}; 435232812Sjmalletttypedef union cvmx_tim_dbg3 cvmx_tim_dbg3_t; 436232812Sjmallett 437232812Sjmallett/** 438232812Sjmallett * cvmx_tim_ecc_cfg 439232812Sjmallett */ 440232812Sjmallettunion cvmx_tim_ecc_cfg { 441232812Sjmallett uint64_t u64; 442232812Sjmallett struct cvmx_tim_ecc_cfg_s { 443232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 444232812Sjmallett uint64_t reserved_3_63 : 61; 445232812Sjmallett uint64_t ecc_flp_syn : 2; /**< ECC Flip Syndrome. Flip the ECC's syndrome for testing 446232812Sjmallett purposes, to test SBE and DBE ECC interrupts. */ 447232812Sjmallett uint64_t ecc_en : 1; /**< Enable ECC correction of the Ring Data Structre memory. 448232812Sjmallett ECC is enabled by default. */ 449232812Sjmallett#else 450232812Sjmallett uint64_t ecc_en : 1; 451232812Sjmallett uint64_t ecc_flp_syn : 2; 452232812Sjmallett uint64_t reserved_3_63 : 61; 453232812Sjmallett#endif 454232812Sjmallett } s; 455232812Sjmallett struct cvmx_tim_ecc_cfg_s cn68xx; 456232812Sjmallett struct cvmx_tim_ecc_cfg_s cn68xxp1; 457232812Sjmallett}; 458232812Sjmalletttypedef union cvmx_tim_ecc_cfg cvmx_tim_ecc_cfg_t; 459232812Sjmallett 460232812Sjmallett/** 461232812Sjmallett * cvmx_tim_fr_rn_tt 462232812Sjmallett * 463232812Sjmallett * Notes: 464232812Sjmallett * For every 64 entries in a bucket interval should be at 465232812Sjmallett * least 1us. 466232812Sjmallett * Minimal recommended value for Threshold register is 1us 467232812Sjmallett */ 468232812Sjmallettunion cvmx_tim_fr_rn_tt { 469232812Sjmallett uint64_t u64; 470232812Sjmallett struct cvmx_tim_fr_rn_tt_s { 471232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 472232812Sjmallett uint64_t reserved_54_63 : 10; 473232812Sjmallett uint64_t thld_gp : 22; /**< Free Running Timer Threshold. Defines the reset value 474232812Sjmallett for the free running timer when it reaches zero during 475232812Sjmallett it's count down. This threshold only applies to the 476232812Sjmallett timer that is driven by GPIO edge as defined at 477232812Sjmallett TIM_REG_FLAGS.GPIO_EDGE 478232812Sjmallett ***NOTE: Added in pass 2.0 */ 479232812Sjmallett uint64_t reserved_22_31 : 10; 480232812Sjmallett uint64_t fr_rn_tt : 22; /**< Free Running Timer Threshold. Defines the reset value 481232812Sjmallett for the free running timer when it reaches zero during 482232812Sjmallett it's count down. 483232812Sjmallett FR_RN_TT will be used in both cases where free running 484232812Sjmallett clock is driven externally or internally. 485232812Sjmallett Interval programming guidelines: 486232812Sjmallett For every 64 entries in a bucket interval should be at 487232812Sjmallett least 1us. 488232812Sjmallett Minimal recommended value for FR_RN_TT is 1us. */ 489232812Sjmallett#else 490232812Sjmallett uint64_t fr_rn_tt : 22; 491232812Sjmallett uint64_t reserved_22_31 : 10; 492232812Sjmallett uint64_t thld_gp : 22; 493232812Sjmallett uint64_t reserved_54_63 : 10; 494232812Sjmallett#endif 495232812Sjmallett } s; 496232812Sjmallett struct cvmx_tim_fr_rn_tt_s cn68xx; 497232812Sjmallett struct cvmx_tim_fr_rn_tt_cn68xxp1 { 498232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 499232812Sjmallett uint64_t reserved_22_63 : 42; 500232812Sjmallett uint64_t fr_rn_tt : 22; /**< Free Running Timer Threshold. Defines the reset value 501232812Sjmallett for the free running timer when it reaches zero during 502232812Sjmallett it's count down. 503232812Sjmallett FR_RN_TT will be used in both cases where free running 504232812Sjmallett clock is driven externally or internally. 505232812Sjmallett Interval programming guidelines: 506232812Sjmallett For every 64 entries in a bucket interval should be at 507232812Sjmallett least 1us. 508232812Sjmallett Minimal recommended value for FR_RN_TT is 1us. */ 509232812Sjmallett#else 510232812Sjmallett uint64_t fr_rn_tt : 22; 511232812Sjmallett uint64_t reserved_22_63 : 42; 512232812Sjmallett#endif 513232812Sjmallett } cn68xxp1; 514232812Sjmallett}; 515232812Sjmalletttypedef union cvmx_tim_fr_rn_tt cvmx_tim_fr_rn_tt_t; 516232812Sjmallett 517232812Sjmallett/** 518232812Sjmallett * cvmx_tim_gpio_en 519232812Sjmallett */ 520232812Sjmallettunion cvmx_tim_gpio_en { 521232812Sjmallett uint64_t u64; 522232812Sjmallett struct cvmx_tim_gpio_en_s { 523232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 524232812Sjmallett uint64_t gpio_en : 64; /**< Each bit correspond to rings [63:0] respectively. 525232812Sjmallett This register reflects the values written to 526232812Sjmallett TIM_RING63..0_CTL1.ENA_GPIO 527232812Sjmallett ***NOTE: Added in pass 2.0 for debug only. RESERVED */ 528232812Sjmallett#else 529232812Sjmallett uint64_t gpio_en : 64; 530232812Sjmallett#endif 531232812Sjmallett } s; 532232812Sjmallett struct cvmx_tim_gpio_en_s cn68xx; 533232812Sjmallett}; 534232812Sjmalletttypedef union cvmx_tim_gpio_en cvmx_tim_gpio_en_t; 535232812Sjmallett 536232812Sjmallett/** 537232812Sjmallett * cvmx_tim_int0 538232812Sjmallett * 539232812Sjmallett * Notes: 540232812Sjmallett * A ring is in error if its interval has elapsed more than once without having been serviced. This is 541232812Sjmallett * usually a programming error where number of entries in the bucket is too large for the interval 542232812Sjmallett * specified for the ring. 543232812Sjmallett * Any bit in the INT field should be cleared by writing '1' to it. 544232812Sjmallett */ 545232812Sjmallettunion cvmx_tim_int0 { 546232812Sjmallett uint64_t u64; 547232812Sjmallett struct cvmx_tim_int0_s { 548232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 549232812Sjmallett uint64_t int0 : 64; /**< Interrupt bit per ring. Each bit indicates the 550232812Sjmallett ring number in error. Each bit in this reg is set 551232812Sjmallett regardless of TIM_INT0_EN value. */ 552232812Sjmallett#else 553232812Sjmallett uint64_t int0 : 64; 554232812Sjmallett#endif 555232812Sjmallett } s; 556232812Sjmallett struct cvmx_tim_int0_s cn68xx; 557232812Sjmallett struct cvmx_tim_int0_s cn68xxp1; 558232812Sjmallett}; 559232812Sjmalletttypedef union cvmx_tim_int0 cvmx_tim_int0_t; 560232812Sjmallett 561232812Sjmallett/** 562232812Sjmallett * cvmx_tim_int0_en 563232812Sjmallett * 564232812Sjmallett * Notes: 565232812Sjmallett * When bit at TIM_INT0_EN is set it enables the corresponding TIM_INTO's bit for interrupt generation 566232812Sjmallett * If enable bit is cleared the corresponding bit at TIM_INT0 will still be set. 567232812Sjmallett * Interrupt to the cores is generated by : |(TIM_INT0 & TIM_INT0_EN0) 568232812Sjmallett */ 569232812Sjmallettunion cvmx_tim_int0_en { 570232812Sjmallett uint64_t u64; 571232812Sjmallett struct cvmx_tim_int0_en_s { 572232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 573232812Sjmallett uint64_t int0_en : 64; /**< Bit enable corresponding to TIM_INT0. */ 574232812Sjmallett#else 575232812Sjmallett uint64_t int0_en : 64; 576232812Sjmallett#endif 577232812Sjmallett } s; 578232812Sjmallett struct cvmx_tim_int0_en_s cn68xx; 579232812Sjmallett struct cvmx_tim_int0_en_s cn68xxp1; 580232812Sjmallett}; 581232812Sjmalletttypedef union cvmx_tim_int0_en cvmx_tim_int0_en_t; 582232812Sjmallett 583232812Sjmallett/** 584232812Sjmallett * cvmx_tim_int0_event 585232812Sjmallett */ 586232812Sjmallettunion cvmx_tim_int0_event { 587232812Sjmallett uint64_t u64; 588232812Sjmallett struct cvmx_tim_int0_event_s { 589232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 590232812Sjmallett uint64_t reserved_6_63 : 58; 591232812Sjmallett uint64_t ring_id : 6; /**< The first Ring ID where an interrupt occurred. */ 592232812Sjmallett#else 593232812Sjmallett uint64_t ring_id : 6; 594232812Sjmallett uint64_t reserved_6_63 : 58; 595232812Sjmallett#endif 596232812Sjmallett } s; 597232812Sjmallett struct cvmx_tim_int0_event_s cn68xx; 598232812Sjmallett struct cvmx_tim_int0_event_s cn68xxp1; 599232812Sjmallett}; 600232812Sjmalletttypedef union cvmx_tim_int0_event cvmx_tim_int0_event_t; 601232812Sjmallett 602232812Sjmallett/** 603232812Sjmallett * cvmx_tim_int_eccerr 604232812Sjmallett * 605232812Sjmallett * Notes: 606232812Sjmallett * Each bit in this reg is set regardless of TIM_INT_ECCERR_EN value. 607232812Sjmallett * 608232812Sjmallett */ 609232812Sjmallettunion cvmx_tim_int_eccerr { 610232812Sjmallett uint64_t u64; 611232812Sjmallett struct cvmx_tim_int_eccerr_s { 612232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 613232812Sjmallett uint64_t reserved_2_63 : 62; 614232812Sjmallett uint64_t dbe : 1; /**< TIM RDS memory had a Double Bit Error */ 615232812Sjmallett uint64_t sbe : 1; /**< TIM RDS memory had a Single Bit Error */ 616232812Sjmallett#else 617232812Sjmallett uint64_t sbe : 1; 618232812Sjmallett uint64_t dbe : 1; 619232812Sjmallett uint64_t reserved_2_63 : 62; 620232812Sjmallett#endif 621232812Sjmallett } s; 622232812Sjmallett struct cvmx_tim_int_eccerr_s cn68xx; 623232812Sjmallett struct cvmx_tim_int_eccerr_s cn68xxp1; 624232812Sjmallett}; 625232812Sjmalletttypedef union cvmx_tim_int_eccerr cvmx_tim_int_eccerr_t; 626232812Sjmallett 627232812Sjmallett/** 628232812Sjmallett * cvmx_tim_int_eccerr_en 629232812Sjmallett * 630232812Sjmallett * Notes: 631232812Sjmallett * When mask bit is set, the corresponding bit in TIM_INT_ECCERR is enabled. If mask bit is cleared the 632232812Sjmallett * corresponding bit in TIM_INT_ECCERR will still be set but interrupt will not be reported. 633232812Sjmallett */ 634232812Sjmallettunion cvmx_tim_int_eccerr_en { 635232812Sjmallett uint64_t u64; 636232812Sjmallett struct cvmx_tim_int_eccerr_en_s { 637232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 638232812Sjmallett uint64_t reserved_2_63 : 62; 639232812Sjmallett uint64_t dbe_en : 1; /**< Bit mask corresponding to TIM_REG_ECCERR.DBE */ 640232812Sjmallett uint64_t sbe_en : 1; /**< Bit mask corresponding to TIM_REG_ECCERR.SBE */ 641232812Sjmallett#else 642232812Sjmallett uint64_t sbe_en : 1; 643232812Sjmallett uint64_t dbe_en : 1; 644232812Sjmallett uint64_t reserved_2_63 : 62; 645232812Sjmallett#endif 646232812Sjmallett } s; 647232812Sjmallett struct cvmx_tim_int_eccerr_en_s cn68xx; 648232812Sjmallett struct cvmx_tim_int_eccerr_en_s cn68xxp1; 649232812Sjmallett}; 650232812Sjmalletttypedef union cvmx_tim_int_eccerr_en cvmx_tim_int_eccerr_en_t; 651232812Sjmallett 652232812Sjmallett/** 653232812Sjmallett * cvmx_tim_int_eccerr_event0 654232812Sjmallett */ 655232812Sjmallettunion cvmx_tim_int_eccerr_event0 { 656232812Sjmallett uint64_t u64; 657232812Sjmallett struct cvmx_tim_int_eccerr_event0_s { 658232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 659232812Sjmallett uint64_t reserved_15_63 : 49; 660232812Sjmallett uint64_t synd : 7; /**< ECC Syndrome */ 661232812Sjmallett uint64_t add : 8; /**< Memory address where the Error occurred. */ 662232812Sjmallett#else 663232812Sjmallett uint64_t add : 8; 664232812Sjmallett uint64_t synd : 7; 665232812Sjmallett uint64_t reserved_15_63 : 49; 666232812Sjmallett#endif 667232812Sjmallett } s; 668232812Sjmallett struct cvmx_tim_int_eccerr_event0_s cn68xx; 669232812Sjmallett struct cvmx_tim_int_eccerr_event0_s cn68xxp1; 670232812Sjmallett}; 671232812Sjmalletttypedef union cvmx_tim_int_eccerr_event0 cvmx_tim_int_eccerr_event0_t; 672232812Sjmallett 673232812Sjmallett/** 674232812Sjmallett * cvmx_tim_int_eccerr_event1 675232812Sjmallett */ 676232812Sjmallettunion cvmx_tim_int_eccerr_event1 { 677232812Sjmallett uint64_t u64; 678232812Sjmallett struct cvmx_tim_int_eccerr_event1_s { 679232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 680232812Sjmallett uint64_t reserved_55_63 : 9; 681232812Sjmallett uint64_t org_ecc : 7; /**< Original ECC bits where the error occured. */ 682232812Sjmallett uint64_t org_rds_dat : 48; /**< Memory original data where the error occured. */ 683232812Sjmallett#else 684232812Sjmallett uint64_t org_rds_dat : 48; 685232812Sjmallett uint64_t org_ecc : 7; 686232812Sjmallett uint64_t reserved_55_63 : 9; 687232812Sjmallett#endif 688232812Sjmallett } s; 689232812Sjmallett struct cvmx_tim_int_eccerr_event1_s cn68xx; 690232812Sjmallett struct cvmx_tim_int_eccerr_event1_s cn68xxp1; 691232812Sjmallett}; 692232812Sjmalletttypedef union cvmx_tim_int_eccerr_event1 cvmx_tim_int_eccerr_event1_t; 693232812Sjmallett 694232812Sjmallett/** 695215976Sjmallett * cvmx_tim_mem_debug0 696215976Sjmallett * 697215976Sjmallett * Notes: 698215976Sjmallett * Internal per-ring state intended for debug use only - tim.ctl[47:0] 699215976Sjmallett * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any 700215976Sjmallett * CSR read operations to this address can be performed. 701215976Sjmallett */ 702232812Sjmallettunion cvmx_tim_mem_debug0 { 703215976Sjmallett uint64_t u64; 704232812Sjmallett struct cvmx_tim_mem_debug0_s { 705232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 706215976Sjmallett uint64_t reserved_48_63 : 16; 707215976Sjmallett uint64_t ena : 1; /**< Ring timer enable */ 708215976Sjmallett uint64_t reserved_46_46 : 1; 709215976Sjmallett uint64_t count : 22; /**< Time offset for the ring 710215976Sjmallett Set to INTERVAL and counts down by 1 every 1024 711215976Sjmallett cycles when ENA==1. The HW forces a bucket 712215976Sjmallett traversal (and resets COUNT to INTERVAL) whenever 713215976Sjmallett the decrement would cause COUNT to go negative. 714215976Sjmallett COUNT is unpredictable whenever ENA==0. 715215976Sjmallett COUNT is reset to INTERVAL whenever TIM_MEM_RING1 716215976Sjmallett is written for the ring. */ 717215976Sjmallett uint64_t reserved_22_23 : 2; 718215976Sjmallett uint64_t interval : 22; /**< Timer interval - 1 */ 719215976Sjmallett#else 720215976Sjmallett uint64_t interval : 22; 721215976Sjmallett uint64_t reserved_22_23 : 2; 722215976Sjmallett uint64_t count : 22; 723215976Sjmallett uint64_t reserved_46_46 : 1; 724215976Sjmallett uint64_t ena : 1; 725215976Sjmallett uint64_t reserved_48_63 : 16; 726215976Sjmallett#endif 727215976Sjmallett } s; 728215976Sjmallett struct cvmx_tim_mem_debug0_s cn30xx; 729215976Sjmallett struct cvmx_tim_mem_debug0_s cn31xx; 730215976Sjmallett struct cvmx_tim_mem_debug0_s cn38xx; 731215976Sjmallett struct cvmx_tim_mem_debug0_s cn38xxp2; 732215976Sjmallett struct cvmx_tim_mem_debug0_s cn50xx; 733215976Sjmallett struct cvmx_tim_mem_debug0_s cn52xx; 734215976Sjmallett struct cvmx_tim_mem_debug0_s cn52xxp1; 735215976Sjmallett struct cvmx_tim_mem_debug0_s cn56xx; 736215976Sjmallett struct cvmx_tim_mem_debug0_s cn56xxp1; 737215976Sjmallett struct cvmx_tim_mem_debug0_s cn58xx; 738215976Sjmallett struct cvmx_tim_mem_debug0_s cn58xxp1; 739232812Sjmallett struct cvmx_tim_mem_debug0_s cn61xx; 740215976Sjmallett struct cvmx_tim_mem_debug0_s cn63xx; 741215976Sjmallett struct cvmx_tim_mem_debug0_s cn63xxp1; 742232812Sjmallett struct cvmx_tim_mem_debug0_s cn66xx; 743232812Sjmallett struct cvmx_tim_mem_debug0_s cnf71xx; 744215976Sjmallett}; 745215976Sjmalletttypedef union cvmx_tim_mem_debug0 cvmx_tim_mem_debug0_t; 746215976Sjmallett 747215976Sjmallett/** 748215976Sjmallett * cvmx_tim_mem_debug1 749215976Sjmallett * 750215976Sjmallett * Notes: 751215976Sjmallett * Internal per-ring state intended for debug use only - tim.sta[63:0] 752215976Sjmallett * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any 753215976Sjmallett * CSR read operations to this address can be performed. 754215976Sjmallett */ 755232812Sjmallettunion cvmx_tim_mem_debug1 { 756215976Sjmallett uint64_t u64; 757232812Sjmallett struct cvmx_tim_mem_debug1_s { 758232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 759215976Sjmallett uint64_t bucket : 13; /**< Current bucket[12:0] 760215976Sjmallett Reset to 0 whenever TIM_MEM_RING0 is written for 761215976Sjmallett the ring. Incremented (modulo BSIZE) once per 762215976Sjmallett bucket traversal. 763215976Sjmallett See TIM_MEM_DEBUG2[BUCKET]. */ 764215976Sjmallett uint64_t base : 31; /**< Pointer[35:5] to bucket[0] */ 765215976Sjmallett uint64_t bsize : 20; /**< Number of buckets - 1 */ 766215976Sjmallett#else 767215976Sjmallett uint64_t bsize : 20; 768215976Sjmallett uint64_t base : 31; 769215976Sjmallett uint64_t bucket : 13; 770215976Sjmallett#endif 771215976Sjmallett } s; 772215976Sjmallett struct cvmx_tim_mem_debug1_s cn30xx; 773215976Sjmallett struct cvmx_tim_mem_debug1_s cn31xx; 774215976Sjmallett struct cvmx_tim_mem_debug1_s cn38xx; 775215976Sjmallett struct cvmx_tim_mem_debug1_s cn38xxp2; 776215976Sjmallett struct cvmx_tim_mem_debug1_s cn50xx; 777215976Sjmallett struct cvmx_tim_mem_debug1_s cn52xx; 778215976Sjmallett struct cvmx_tim_mem_debug1_s cn52xxp1; 779215976Sjmallett struct cvmx_tim_mem_debug1_s cn56xx; 780215976Sjmallett struct cvmx_tim_mem_debug1_s cn56xxp1; 781215976Sjmallett struct cvmx_tim_mem_debug1_s cn58xx; 782215976Sjmallett struct cvmx_tim_mem_debug1_s cn58xxp1; 783232812Sjmallett struct cvmx_tim_mem_debug1_s cn61xx; 784215976Sjmallett struct cvmx_tim_mem_debug1_s cn63xx; 785215976Sjmallett struct cvmx_tim_mem_debug1_s cn63xxp1; 786232812Sjmallett struct cvmx_tim_mem_debug1_s cn66xx; 787232812Sjmallett struct cvmx_tim_mem_debug1_s cnf71xx; 788215976Sjmallett}; 789215976Sjmalletttypedef union cvmx_tim_mem_debug1 cvmx_tim_mem_debug1_t; 790215976Sjmallett 791215976Sjmallett/** 792215976Sjmallett * cvmx_tim_mem_debug2 793215976Sjmallett * 794215976Sjmallett * Notes: 795215976Sjmallett * Internal per-ring state intended for debug use only - tim.sta[95:64] 796215976Sjmallett * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any 797215976Sjmallett * CSR read operations to this address can be performed. 798215976Sjmallett */ 799232812Sjmallettunion cvmx_tim_mem_debug2 { 800215976Sjmallett uint64_t u64; 801232812Sjmallett struct cvmx_tim_mem_debug2_s { 802232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 803215976Sjmallett uint64_t reserved_24_63 : 40; 804215976Sjmallett uint64_t cpool : 3; /**< Free list used to free chunks */ 805215976Sjmallett uint64_t csize : 13; /**< Number of words per chunk */ 806215976Sjmallett uint64_t reserved_7_7 : 1; 807215976Sjmallett uint64_t bucket : 7; /**< Current bucket[19:13] 808215976Sjmallett See TIM_MEM_DEBUG1[BUCKET]. */ 809215976Sjmallett#else 810215976Sjmallett uint64_t bucket : 7; 811215976Sjmallett uint64_t reserved_7_7 : 1; 812215976Sjmallett uint64_t csize : 13; 813215976Sjmallett uint64_t cpool : 3; 814215976Sjmallett uint64_t reserved_24_63 : 40; 815215976Sjmallett#endif 816215976Sjmallett } s; 817215976Sjmallett struct cvmx_tim_mem_debug2_s cn30xx; 818215976Sjmallett struct cvmx_tim_mem_debug2_s cn31xx; 819215976Sjmallett struct cvmx_tim_mem_debug2_s cn38xx; 820215976Sjmallett struct cvmx_tim_mem_debug2_s cn38xxp2; 821215976Sjmallett struct cvmx_tim_mem_debug2_s cn50xx; 822215976Sjmallett struct cvmx_tim_mem_debug2_s cn52xx; 823215976Sjmallett struct cvmx_tim_mem_debug2_s cn52xxp1; 824215976Sjmallett struct cvmx_tim_mem_debug2_s cn56xx; 825215976Sjmallett struct cvmx_tim_mem_debug2_s cn56xxp1; 826215976Sjmallett struct cvmx_tim_mem_debug2_s cn58xx; 827215976Sjmallett struct cvmx_tim_mem_debug2_s cn58xxp1; 828232812Sjmallett struct cvmx_tim_mem_debug2_s cn61xx; 829215976Sjmallett struct cvmx_tim_mem_debug2_s cn63xx; 830215976Sjmallett struct cvmx_tim_mem_debug2_s cn63xxp1; 831232812Sjmallett struct cvmx_tim_mem_debug2_s cn66xx; 832232812Sjmallett struct cvmx_tim_mem_debug2_s cnf71xx; 833215976Sjmallett}; 834215976Sjmalletttypedef union cvmx_tim_mem_debug2 cvmx_tim_mem_debug2_t; 835215976Sjmallett 836215976Sjmallett/** 837215976Sjmallett * cvmx_tim_mem_ring0 838215976Sjmallett * 839215976Sjmallett * Notes: 840215976Sjmallett * TIM_MEM_RING0 must not be written for a ring when TIM_MEM_RING1[ENA] is set for the ring. 841215976Sjmallett * Every write to TIM_MEM_RING0 clears the current bucket for the ring. (The current bucket is 842215976Sjmallett * readable via TIM_MEM_DEBUG2[BUCKET],TIM_MEM_DEBUG1[BUCKET].) 843215976Sjmallett * BASE is a 32-byte aligned pointer[35:0]. Only pointer[35:5] are stored because pointer[4:0] = 0. 844215976Sjmallett * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any 845215976Sjmallett * CSR read operations to this address can be performed. 846215976Sjmallett */ 847232812Sjmallettunion cvmx_tim_mem_ring0 { 848215976Sjmallett uint64_t u64; 849232812Sjmallett struct cvmx_tim_mem_ring0_s { 850232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 851215976Sjmallett uint64_t reserved_55_63 : 9; 852215976Sjmallett uint64_t first_bucket : 31; /**< Pointer[35:5] to bucket[0] */ 853215976Sjmallett uint64_t num_buckets : 20; /**< Number of buckets - 1 */ 854215976Sjmallett uint64_t ring : 4; /**< Ring ID */ 855215976Sjmallett#else 856215976Sjmallett uint64_t ring : 4; 857215976Sjmallett uint64_t num_buckets : 20; 858215976Sjmallett uint64_t first_bucket : 31; 859215976Sjmallett uint64_t reserved_55_63 : 9; 860215976Sjmallett#endif 861215976Sjmallett } s; 862215976Sjmallett struct cvmx_tim_mem_ring0_s cn30xx; 863215976Sjmallett struct cvmx_tim_mem_ring0_s cn31xx; 864215976Sjmallett struct cvmx_tim_mem_ring0_s cn38xx; 865215976Sjmallett struct cvmx_tim_mem_ring0_s cn38xxp2; 866215976Sjmallett struct cvmx_tim_mem_ring0_s cn50xx; 867215976Sjmallett struct cvmx_tim_mem_ring0_s cn52xx; 868215976Sjmallett struct cvmx_tim_mem_ring0_s cn52xxp1; 869215976Sjmallett struct cvmx_tim_mem_ring0_s cn56xx; 870215976Sjmallett struct cvmx_tim_mem_ring0_s cn56xxp1; 871215976Sjmallett struct cvmx_tim_mem_ring0_s cn58xx; 872215976Sjmallett struct cvmx_tim_mem_ring0_s cn58xxp1; 873232812Sjmallett struct cvmx_tim_mem_ring0_s cn61xx; 874215976Sjmallett struct cvmx_tim_mem_ring0_s cn63xx; 875215976Sjmallett struct cvmx_tim_mem_ring0_s cn63xxp1; 876232812Sjmallett struct cvmx_tim_mem_ring0_s cn66xx; 877232812Sjmallett struct cvmx_tim_mem_ring0_s cnf71xx; 878215976Sjmallett}; 879215976Sjmalletttypedef union cvmx_tim_mem_ring0 cvmx_tim_mem_ring0_t; 880215976Sjmallett 881215976Sjmallett/** 882215976Sjmallett * cvmx_tim_mem_ring1 883215976Sjmallett * 884215976Sjmallett * Notes: 885215976Sjmallett * After a 1->0 transition on ENA, the HW will still complete a bucket traversal for the ring 886215976Sjmallett * if it was pending or active prior to the transition. (SW must delay to ensure the completion 887215976Sjmallett * of the traversal before reprogramming the ring.) 888215976Sjmallett * Every write to TIM_MEM_RING1 resets the current time offset for the ring to the INTERVAL value. 889215976Sjmallett * (The current time offset for the ring is readable via TIM_MEM_DEBUG0[COUNT].) 890215976Sjmallett * CSIZE must be at least 16. It is illegal to program CSIZE to a value that is less than 16. 891215976Sjmallett * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any 892215976Sjmallett * CSR read operations to this address can be performed. 893215976Sjmallett */ 894232812Sjmallettunion cvmx_tim_mem_ring1 { 895215976Sjmallett uint64_t u64; 896232812Sjmallett struct cvmx_tim_mem_ring1_s { 897232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 898215976Sjmallett uint64_t reserved_43_63 : 21; 899215976Sjmallett uint64_t enable : 1; /**< Ring timer enable 900215976Sjmallett When clear, the ring is disabled and TIM 901215976Sjmallett will not traverse any new buckets for the ring. */ 902215976Sjmallett uint64_t pool : 3; /**< Free list used to free chunks */ 903215976Sjmallett uint64_t words_per_chunk : 13; /**< Number of words per chunk */ 904215976Sjmallett uint64_t interval : 22; /**< Timer interval - 1, measured in 1024 cycle ticks */ 905215976Sjmallett uint64_t ring : 4; /**< Ring ID */ 906215976Sjmallett#else 907215976Sjmallett uint64_t ring : 4; 908215976Sjmallett uint64_t interval : 22; 909215976Sjmallett uint64_t words_per_chunk : 13; 910215976Sjmallett uint64_t pool : 3; 911215976Sjmallett uint64_t enable : 1; 912215976Sjmallett uint64_t reserved_43_63 : 21; 913215976Sjmallett#endif 914215976Sjmallett } s; 915215976Sjmallett struct cvmx_tim_mem_ring1_s cn30xx; 916215976Sjmallett struct cvmx_tim_mem_ring1_s cn31xx; 917215976Sjmallett struct cvmx_tim_mem_ring1_s cn38xx; 918215976Sjmallett struct cvmx_tim_mem_ring1_s cn38xxp2; 919215976Sjmallett struct cvmx_tim_mem_ring1_s cn50xx; 920215976Sjmallett struct cvmx_tim_mem_ring1_s cn52xx; 921215976Sjmallett struct cvmx_tim_mem_ring1_s cn52xxp1; 922215976Sjmallett struct cvmx_tim_mem_ring1_s cn56xx; 923215976Sjmallett struct cvmx_tim_mem_ring1_s cn56xxp1; 924215976Sjmallett struct cvmx_tim_mem_ring1_s cn58xx; 925215976Sjmallett struct cvmx_tim_mem_ring1_s cn58xxp1; 926232812Sjmallett struct cvmx_tim_mem_ring1_s cn61xx; 927215976Sjmallett struct cvmx_tim_mem_ring1_s cn63xx; 928215976Sjmallett struct cvmx_tim_mem_ring1_s cn63xxp1; 929232812Sjmallett struct cvmx_tim_mem_ring1_s cn66xx; 930232812Sjmallett struct cvmx_tim_mem_ring1_s cnf71xx; 931215976Sjmallett}; 932215976Sjmalletttypedef union cvmx_tim_mem_ring1 cvmx_tim_mem_ring1_t; 933215976Sjmallett 934215976Sjmallett/** 935215976Sjmallett * cvmx_tim_reg_bist_result 936215976Sjmallett * 937215976Sjmallett * Notes: 938215976Sjmallett * Access to the internal BiST results 939215976Sjmallett * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail). 940215976Sjmallett */ 941232812Sjmallettunion cvmx_tim_reg_bist_result { 942215976Sjmallett uint64_t u64; 943232812Sjmallett struct cvmx_tim_reg_bist_result_s { 944232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 945215976Sjmallett uint64_t reserved_4_63 : 60; 946215976Sjmallett uint64_t sta : 2; /**< BiST result of the STA memories (0=pass, !0=fail) */ 947215976Sjmallett uint64_t ncb : 1; /**< BiST result of the NCB memories (0=pass, !0=fail) */ 948215976Sjmallett uint64_t ctl : 1; /**< BiST result of the CTL memories (0=pass, !0=fail) */ 949215976Sjmallett#else 950215976Sjmallett uint64_t ctl : 1; 951215976Sjmallett uint64_t ncb : 1; 952215976Sjmallett uint64_t sta : 2; 953215976Sjmallett uint64_t reserved_4_63 : 60; 954215976Sjmallett#endif 955215976Sjmallett } s; 956215976Sjmallett struct cvmx_tim_reg_bist_result_s cn30xx; 957215976Sjmallett struct cvmx_tim_reg_bist_result_s cn31xx; 958215976Sjmallett struct cvmx_tim_reg_bist_result_s cn38xx; 959215976Sjmallett struct cvmx_tim_reg_bist_result_s cn38xxp2; 960215976Sjmallett struct cvmx_tim_reg_bist_result_s cn50xx; 961215976Sjmallett struct cvmx_tim_reg_bist_result_s cn52xx; 962215976Sjmallett struct cvmx_tim_reg_bist_result_s cn52xxp1; 963215976Sjmallett struct cvmx_tim_reg_bist_result_s cn56xx; 964215976Sjmallett struct cvmx_tim_reg_bist_result_s cn56xxp1; 965215976Sjmallett struct cvmx_tim_reg_bist_result_s cn58xx; 966215976Sjmallett struct cvmx_tim_reg_bist_result_s cn58xxp1; 967232812Sjmallett struct cvmx_tim_reg_bist_result_s cn61xx; 968215976Sjmallett struct cvmx_tim_reg_bist_result_s cn63xx; 969215976Sjmallett struct cvmx_tim_reg_bist_result_s cn63xxp1; 970232812Sjmallett struct cvmx_tim_reg_bist_result_s cn66xx; 971232812Sjmallett struct cvmx_tim_reg_bist_result_s cnf71xx; 972215976Sjmallett}; 973215976Sjmalletttypedef union cvmx_tim_reg_bist_result cvmx_tim_reg_bist_result_t; 974215976Sjmallett 975215976Sjmallett/** 976215976Sjmallett * cvmx_tim_reg_error 977215976Sjmallett * 978215976Sjmallett * Notes: 979215976Sjmallett * A ring is in error if its interval has elapsed more than once without having been serviced. 980215976Sjmallett * During a CSR write to this register, the write data is used as a mask to clear the selected mask 981215976Sjmallett * bits (mask'[15:0] = mask[15:0] & ~write_data[15:0]). 982215976Sjmallett */ 983232812Sjmallettunion cvmx_tim_reg_error { 984215976Sjmallett uint64_t u64; 985232812Sjmallett struct cvmx_tim_reg_error_s { 986232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 987215976Sjmallett uint64_t reserved_16_63 : 48; 988215976Sjmallett uint64_t mask : 16; /**< Bit mask indicating the rings in error */ 989215976Sjmallett#else 990215976Sjmallett uint64_t mask : 16; 991215976Sjmallett uint64_t reserved_16_63 : 48; 992215976Sjmallett#endif 993215976Sjmallett } s; 994215976Sjmallett struct cvmx_tim_reg_error_s cn30xx; 995215976Sjmallett struct cvmx_tim_reg_error_s cn31xx; 996215976Sjmallett struct cvmx_tim_reg_error_s cn38xx; 997215976Sjmallett struct cvmx_tim_reg_error_s cn38xxp2; 998215976Sjmallett struct cvmx_tim_reg_error_s cn50xx; 999215976Sjmallett struct cvmx_tim_reg_error_s cn52xx; 1000215976Sjmallett struct cvmx_tim_reg_error_s cn52xxp1; 1001215976Sjmallett struct cvmx_tim_reg_error_s cn56xx; 1002215976Sjmallett struct cvmx_tim_reg_error_s cn56xxp1; 1003215976Sjmallett struct cvmx_tim_reg_error_s cn58xx; 1004215976Sjmallett struct cvmx_tim_reg_error_s cn58xxp1; 1005232812Sjmallett struct cvmx_tim_reg_error_s cn61xx; 1006215976Sjmallett struct cvmx_tim_reg_error_s cn63xx; 1007215976Sjmallett struct cvmx_tim_reg_error_s cn63xxp1; 1008232812Sjmallett struct cvmx_tim_reg_error_s cn66xx; 1009232812Sjmallett struct cvmx_tim_reg_error_s cnf71xx; 1010215976Sjmallett}; 1011215976Sjmalletttypedef union cvmx_tim_reg_error cvmx_tim_reg_error_t; 1012215976Sjmallett 1013215976Sjmallett/** 1014215976Sjmallett * cvmx_tim_reg_flags 1015215976Sjmallett * 1016232812Sjmallett * 13e20 reserved 1017232812Sjmallett * 1018232812Sjmallett * 1019215976Sjmallett * Notes: 1020215976Sjmallett * TIM has a counter that causes a periodic tick every 1024 cycles. This counter is shared by all 1021215976Sjmallett * rings. (Each tick causes the HW to decrement the time offset (i.e. COUNT) for all enabled rings.) 1022215976Sjmallett * When ENA_TIM==0, the HW stops this shared periodic counter, so there are no more ticks, and there 1023215976Sjmallett * are no more new bucket traversals (for any ring). 1024215976Sjmallett * 1025215976Sjmallett * If ENA_TIM transitions 1->0, TIM will no longer create new bucket traversals, but there may 1026215976Sjmallett * have been previous ones. If there are ring bucket traversals that were already pending but 1027215976Sjmallett * not currently active (i.e. bucket traversals that need to be done by the HW, but haven't been yet) 1028215976Sjmallett * during this ENA_TIM 1->0 transition, then these bucket traversals will remain pending until 1029215976Sjmallett * ENA_TIM is later set to one. Bucket traversals that were already in progress will complete 1030215976Sjmallett * after the 1->0 ENA_TIM transition, though. 1031215976Sjmallett */ 1032232812Sjmallettunion cvmx_tim_reg_flags { 1033215976Sjmallett uint64_t u64; 1034232812Sjmallett struct cvmx_tim_reg_flags_s { 1035232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1036232812Sjmallett uint64_t reserved_7_63 : 57; 1037232812Sjmallett uint64_t gpio_edge : 2; /**< Edge used for GPIO timing 1038232812Sjmallett 2'b10 - TIM counts high to low transitions 1039232812Sjmallett 2'b01 - TIM counts low to high transitions 1040232812Sjmallett 2'b11 - TIM counts Both low to high and high to low 1041232812Sjmallett transitions */ 1042232812Sjmallett uint64_t ena_gpio : 1; /**< Enable the external control of GPIO over the free 1043232812Sjmallett running timer. 1044232812Sjmallett When set, free running timer will be driven by GPIO. 1045232812Sjmallett Free running timer will count posedge or negedge of the 1046232812Sjmallett GPIO pin based on GPIO_EDGE register. */ 1047232812Sjmallett uint64_t ena_dfb : 1; /**< Enable Don't Free Buffer. When set chunk buffer 1048232812Sjmallett would not be released by the TIM back to FPA. */ 1049232812Sjmallett uint64_t reset : 1; /**< Reset oneshot pulse for free-running structures */ 1050232812Sjmallett uint64_t enable_dwb : 1; /**< Enables non-zero DonwWriteBacks when set 1051232812Sjmallett When set, enables the use of 1052232812Sjmallett DontWriteBacks during the buffer freeing 1053232812Sjmallett operations. */ 1054232812Sjmallett uint64_t enable_timers : 1; /**< Enables the TIM section when set 1055232812Sjmallett When set, TIM is in normal operation. 1056232812Sjmallett When clear, time is effectively stopped for all 1057232812Sjmallett rings in TIM. */ 1058232812Sjmallett#else 1059232812Sjmallett uint64_t enable_timers : 1; 1060232812Sjmallett uint64_t enable_dwb : 1; 1061232812Sjmallett uint64_t reset : 1; 1062232812Sjmallett uint64_t ena_dfb : 1; 1063232812Sjmallett uint64_t ena_gpio : 1; 1064232812Sjmallett uint64_t gpio_edge : 2; 1065232812Sjmallett uint64_t reserved_7_63 : 57; 1066232812Sjmallett#endif 1067232812Sjmallett } s; 1068232812Sjmallett struct cvmx_tim_reg_flags_cn30xx { 1069232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1070215976Sjmallett uint64_t reserved_3_63 : 61; 1071215976Sjmallett uint64_t reset : 1; /**< Reset oneshot pulse for free-running structures */ 1072215976Sjmallett uint64_t enable_dwb : 1; /**< Enables non-zero DonwWriteBacks when set 1073215976Sjmallett When set, enables the use of 1074215976Sjmallett DontWriteBacks during the buffer freeing 1075215976Sjmallett operations. */ 1076215976Sjmallett uint64_t enable_timers : 1; /**< Enables the TIM section when set 1077215976Sjmallett When set, TIM is in normal operation. 1078215976Sjmallett When clear, time is effectively stopped for all 1079215976Sjmallett rings in TIM. */ 1080215976Sjmallett#else 1081215976Sjmallett uint64_t enable_timers : 1; 1082215976Sjmallett uint64_t enable_dwb : 1; 1083215976Sjmallett uint64_t reset : 1; 1084215976Sjmallett uint64_t reserved_3_63 : 61; 1085215976Sjmallett#endif 1086232812Sjmallett } cn30xx; 1087232812Sjmallett struct cvmx_tim_reg_flags_cn30xx cn31xx; 1088232812Sjmallett struct cvmx_tim_reg_flags_cn30xx cn38xx; 1089232812Sjmallett struct cvmx_tim_reg_flags_cn30xx cn38xxp2; 1090232812Sjmallett struct cvmx_tim_reg_flags_cn30xx cn50xx; 1091232812Sjmallett struct cvmx_tim_reg_flags_cn30xx cn52xx; 1092232812Sjmallett struct cvmx_tim_reg_flags_cn30xx cn52xxp1; 1093232812Sjmallett struct cvmx_tim_reg_flags_cn30xx cn56xx; 1094232812Sjmallett struct cvmx_tim_reg_flags_cn30xx cn56xxp1; 1095232812Sjmallett struct cvmx_tim_reg_flags_cn30xx cn58xx; 1096232812Sjmallett struct cvmx_tim_reg_flags_cn30xx cn58xxp1; 1097232812Sjmallett struct cvmx_tim_reg_flags_cn30xx cn61xx; 1098232812Sjmallett struct cvmx_tim_reg_flags_cn30xx cn63xx; 1099232812Sjmallett struct cvmx_tim_reg_flags_cn30xx cn63xxp1; 1100232812Sjmallett struct cvmx_tim_reg_flags_cn30xx cn66xx; 1101232812Sjmallett struct cvmx_tim_reg_flags_s cn68xx; 1102232812Sjmallett struct cvmx_tim_reg_flags_s cn68xxp1; 1103232812Sjmallett struct cvmx_tim_reg_flags_cn30xx cnf71xx; 1104215976Sjmallett}; 1105215976Sjmalletttypedef union cvmx_tim_reg_flags cvmx_tim_reg_flags_t; 1106215976Sjmallett 1107215976Sjmallett/** 1108215976Sjmallett * cvmx_tim_reg_int_mask 1109215976Sjmallett * 1110215976Sjmallett * Notes: 1111215976Sjmallett * Note that this CSR is present only in chip revisions beginning with pass2. 1112215976Sjmallett * When mask bit is set, the interrupt is enabled. 1113215976Sjmallett */ 1114232812Sjmallettunion cvmx_tim_reg_int_mask { 1115215976Sjmallett uint64_t u64; 1116232812Sjmallett struct cvmx_tim_reg_int_mask_s { 1117232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1118215976Sjmallett uint64_t reserved_16_63 : 48; 1119215976Sjmallett uint64_t mask : 16; /**< Bit mask corresponding to TIM_REG_ERROR.MASK above */ 1120215976Sjmallett#else 1121215976Sjmallett uint64_t mask : 16; 1122215976Sjmallett uint64_t reserved_16_63 : 48; 1123215976Sjmallett#endif 1124215976Sjmallett } s; 1125215976Sjmallett struct cvmx_tim_reg_int_mask_s cn30xx; 1126215976Sjmallett struct cvmx_tim_reg_int_mask_s cn31xx; 1127215976Sjmallett struct cvmx_tim_reg_int_mask_s cn38xx; 1128215976Sjmallett struct cvmx_tim_reg_int_mask_s cn38xxp2; 1129215976Sjmallett struct cvmx_tim_reg_int_mask_s cn50xx; 1130215976Sjmallett struct cvmx_tim_reg_int_mask_s cn52xx; 1131215976Sjmallett struct cvmx_tim_reg_int_mask_s cn52xxp1; 1132215976Sjmallett struct cvmx_tim_reg_int_mask_s cn56xx; 1133215976Sjmallett struct cvmx_tim_reg_int_mask_s cn56xxp1; 1134215976Sjmallett struct cvmx_tim_reg_int_mask_s cn58xx; 1135215976Sjmallett struct cvmx_tim_reg_int_mask_s cn58xxp1; 1136232812Sjmallett struct cvmx_tim_reg_int_mask_s cn61xx; 1137215976Sjmallett struct cvmx_tim_reg_int_mask_s cn63xx; 1138215976Sjmallett struct cvmx_tim_reg_int_mask_s cn63xxp1; 1139232812Sjmallett struct cvmx_tim_reg_int_mask_s cn66xx; 1140232812Sjmallett struct cvmx_tim_reg_int_mask_s cnf71xx; 1141215976Sjmallett}; 1142215976Sjmalletttypedef union cvmx_tim_reg_int_mask cvmx_tim_reg_int_mask_t; 1143215976Sjmallett 1144215976Sjmallett/** 1145215976Sjmallett * cvmx_tim_reg_read_idx 1146215976Sjmallett * 1147215976Sjmallett * Notes: 1148215976Sjmallett * Provides the read index during a CSR read operation to any of the CSRs that are physically stored 1149215976Sjmallett * as memories. The names of these CSRs begin with the prefix "TIM_MEM_". 1150215976Sjmallett * IDX[7:0] is the read index. INC[7:0] is an increment that is added to IDX[7:0] after any CSR read. 1151215976Sjmallett * The intended use is to initially write this CSR such that IDX=0 and INC=1. Then, the entire 1152215976Sjmallett * contents of a CSR memory can be read with consecutive CSR read commands. 1153215976Sjmallett */ 1154232812Sjmallettunion cvmx_tim_reg_read_idx { 1155215976Sjmallett uint64_t u64; 1156232812Sjmallett struct cvmx_tim_reg_read_idx_s { 1157232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1158215976Sjmallett uint64_t reserved_16_63 : 48; 1159215976Sjmallett uint64_t inc : 8; /**< Increment to add to current index for next index */ 1160215976Sjmallett uint64_t index : 8; /**< Index to use for next memory CSR read */ 1161215976Sjmallett#else 1162215976Sjmallett uint64_t index : 8; 1163215976Sjmallett uint64_t inc : 8; 1164215976Sjmallett uint64_t reserved_16_63 : 48; 1165215976Sjmallett#endif 1166215976Sjmallett } s; 1167215976Sjmallett struct cvmx_tim_reg_read_idx_s cn30xx; 1168215976Sjmallett struct cvmx_tim_reg_read_idx_s cn31xx; 1169215976Sjmallett struct cvmx_tim_reg_read_idx_s cn38xx; 1170215976Sjmallett struct cvmx_tim_reg_read_idx_s cn38xxp2; 1171215976Sjmallett struct cvmx_tim_reg_read_idx_s cn50xx; 1172215976Sjmallett struct cvmx_tim_reg_read_idx_s cn52xx; 1173215976Sjmallett struct cvmx_tim_reg_read_idx_s cn52xxp1; 1174215976Sjmallett struct cvmx_tim_reg_read_idx_s cn56xx; 1175215976Sjmallett struct cvmx_tim_reg_read_idx_s cn56xxp1; 1176215976Sjmallett struct cvmx_tim_reg_read_idx_s cn58xx; 1177215976Sjmallett struct cvmx_tim_reg_read_idx_s cn58xxp1; 1178232812Sjmallett struct cvmx_tim_reg_read_idx_s cn61xx; 1179215976Sjmallett struct cvmx_tim_reg_read_idx_s cn63xx; 1180215976Sjmallett struct cvmx_tim_reg_read_idx_s cn63xxp1; 1181232812Sjmallett struct cvmx_tim_reg_read_idx_s cn66xx; 1182232812Sjmallett struct cvmx_tim_reg_read_idx_s cnf71xx; 1183215976Sjmallett}; 1184215976Sjmalletttypedef union cvmx_tim_reg_read_idx cvmx_tim_reg_read_idx_t; 1185215976Sjmallett 1186232812Sjmallett/** 1187232812Sjmallett * cvmx_tim_ring#_ctl0 1188232812Sjmallett * 1189232812Sjmallett * Notes: 1190232812Sjmallett * This CSR is a memory of 64 entries 1191232812Sjmallett * After a 1 to 0 transition on ENA, the HW will still complete a bucket traversal for the ring 1192232812Sjmallett * if it was pending or active prior to the transition. (SW must delay to ensure the completion 1193232812Sjmallett * of the traversal before reprogramming the ring.) 1194232812Sjmallett */ 1195232812Sjmallettunion cvmx_tim_ringx_ctl0 { 1196232812Sjmallett uint64_t u64; 1197232812Sjmallett struct cvmx_tim_ringx_ctl0_s { 1198232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1199232812Sjmallett uint64_t reserved_47_63 : 17; 1200232812Sjmallett uint64_t ena : 1; /**< Ring timer enable */ 1201232812Sjmallett uint64_t intc : 2; /**< Interval count for Error. Defines how many intervals 1202232812Sjmallett could elapse from bucket expiration till actual 1203232812Sjmallett bucket traversal before HW asserts an error. 1204232812Sjmallett Typical value is 0,1,2. */ 1205232812Sjmallett uint64_t timercount : 22; /**< Timer Count represents the ring offset; how many timer 1206232812Sjmallett ticks have left till the interval expiration. 1207232812Sjmallett Typical initialization value should be Interval/Constant, 1208232812Sjmallett it is recommended that constant should be unique per ring 1209232812Sjmallett This will create an offset between the rings. 1210232812Sjmallett Once ENA is set, 1211232812Sjmallett TIMERCOUNT counts down timer ticks. When TIMERCOUNT 1212232812Sjmallett reaches zero, ring's interval expired and the HW forces 1213232812Sjmallett a bucket traversal (and resets TIMERCOUNT to INTERVAL) 1214232812Sjmallett TIMERCOUNT is unpredictable whenever ENA==0. 1215232812Sjmallett It is SW responsibility to set TIMERCOUNT before 1216232812Sjmallett TIM_RINGX_CTL0.ENA transitions from 0 to 1. 1217232812Sjmallett When the field is set to X it would take X+1 timer tick 1218232812Sjmallett for the interval to expire. */ 1219232812Sjmallett uint64_t interval : 22; /**< Timer interval. Measured in Timer Ticks, where timer 1220232812Sjmallett ticks are defined by TIM_FR_RN_TT.FR_RN_TT. */ 1221232812Sjmallett#else 1222232812Sjmallett uint64_t interval : 22; 1223232812Sjmallett uint64_t timercount : 22; 1224232812Sjmallett uint64_t intc : 2; 1225232812Sjmallett uint64_t ena : 1; 1226232812Sjmallett uint64_t reserved_47_63 : 17; 1227215976Sjmallett#endif 1228232812Sjmallett } s; 1229232812Sjmallett struct cvmx_tim_ringx_ctl0_s cn68xx; 1230232812Sjmallett struct cvmx_tim_ringx_ctl0_s cn68xxp1; 1231232812Sjmallett}; 1232232812Sjmalletttypedef union cvmx_tim_ringx_ctl0 cvmx_tim_ringx_ctl0_t; 1233232812Sjmallett 1234232812Sjmallett/** 1235232812Sjmallett * cvmx_tim_ring#_ctl1 1236232812Sjmallett * 1237232812Sjmallett * Notes: 1238232812Sjmallett * This CSR is a memory of 64 entries 1239232812Sjmallett * ***NOTE: Added fields in pass 2.0 1240232812Sjmallett */ 1241232812Sjmallettunion cvmx_tim_ringx_ctl1 { 1242232812Sjmallett uint64_t u64; 1243232812Sjmallett struct cvmx_tim_ringx_ctl1_s { 1244232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1245232812Sjmallett uint64_t reserved_47_63 : 17; 1246232812Sjmallett uint64_t ena_gpio : 1; /**< When set, ring's timer tick will be generated by the 1247232812Sjmallett GPIO Timer. GPIO edge is defined by 1248232812Sjmallett TIM_REG_FLAGS.GPIO_EDGE 1249232812Sjmallett Default value zero means that timer ticks will 1250232812Sjmallett be genearated from the Internal Timer */ 1251232812Sjmallett uint64_t ena_prd : 1; /**< Enable Periodic Mode which would disable the memory 1252232812Sjmallett write of zeros to num_entries and chunk_remainder 1253232812Sjmallett when a bucket is traveresed. */ 1254232812Sjmallett uint64_t ena_dwb : 1; /**< When set, enables the use of Dont Write Back during 1255232812Sjmallett FPA buffer freeing operations */ 1256232812Sjmallett uint64_t ena_dfb : 1; /**< Enable Don't Free Buffer. When set chunk buffer 1257232812Sjmallett would not be released by the TIM back to FPA. */ 1258232812Sjmallett uint64_t cpool : 3; /**< FPA Free list to free chunks to. */ 1259232812Sjmallett uint64_t bucket : 20; /**< Current bucket. Should be set to zero by SW at 1260232812Sjmallett enable time. 1261232812Sjmallett Incremented once per bucket traversal. */ 1262232812Sjmallett uint64_t bsize : 20; /**< Number of buckets minus one. If BSIZE==0 there is 1263232812Sjmallett only one bucket in the ring. */ 1264232812Sjmallett#else 1265232812Sjmallett uint64_t bsize : 20; 1266232812Sjmallett uint64_t bucket : 20; 1267232812Sjmallett uint64_t cpool : 3; 1268232812Sjmallett uint64_t ena_dfb : 1; 1269232812Sjmallett uint64_t ena_dwb : 1; 1270232812Sjmallett uint64_t ena_prd : 1; 1271232812Sjmallett uint64_t ena_gpio : 1; 1272232812Sjmallett uint64_t reserved_47_63 : 17; 1273232812Sjmallett#endif 1274232812Sjmallett } s; 1275232812Sjmallett struct cvmx_tim_ringx_ctl1_s cn68xx; 1276232812Sjmallett struct cvmx_tim_ringx_ctl1_cn68xxp1 { 1277232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1278232812Sjmallett uint64_t reserved_43_63 : 21; 1279232812Sjmallett uint64_t cpool : 3; /**< FPA Free list to free chunks to. */ 1280232812Sjmallett uint64_t bucket : 20; /**< Current bucket. Should be set to zero by SW at 1281232812Sjmallett enable time. 1282232812Sjmallett Incremented once per bucket traversal. */ 1283232812Sjmallett uint64_t bsize : 20; /**< Number of buckets minus one. If BSIZE==0 there is 1284232812Sjmallett only one bucket in the ring. */ 1285232812Sjmallett#else 1286232812Sjmallett uint64_t bsize : 20; 1287232812Sjmallett uint64_t bucket : 20; 1288232812Sjmallett uint64_t cpool : 3; 1289232812Sjmallett uint64_t reserved_43_63 : 21; 1290232812Sjmallett#endif 1291232812Sjmallett } cn68xxp1; 1292232812Sjmallett}; 1293232812Sjmalletttypedef union cvmx_tim_ringx_ctl1 cvmx_tim_ringx_ctl1_t; 1294232812Sjmallett 1295232812Sjmallett/** 1296232812Sjmallett * cvmx_tim_ring#_ctl2 1297232812Sjmallett * 1298232812Sjmallett * Notes: 1299232812Sjmallett * BASE is a 32-byte aligned pointer[35:0]. Only pointer[35:5] are stored because pointer[4:0] = 0. 1300232812Sjmallett * This CSR is a memory of 64 entries 1301232812Sjmallett */ 1302232812Sjmallettunion cvmx_tim_ringx_ctl2 { 1303232812Sjmallett uint64_t u64; 1304232812Sjmallett struct cvmx_tim_ringx_ctl2_s { 1305232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1306232812Sjmallett uint64_t reserved_47_63 : 17; 1307232812Sjmallett uint64_t csize : 13; /**< Number of words per chunk. CSIZE mod(16) should be 1308232812Sjmallett zero. */ 1309232812Sjmallett uint64_t reserved_31_33 : 3; 1310232812Sjmallett uint64_t base : 31; /**< Pointer[35:5] to bucket[0] */ 1311232812Sjmallett#else 1312232812Sjmallett uint64_t base : 31; 1313232812Sjmallett uint64_t reserved_31_33 : 3; 1314232812Sjmallett uint64_t csize : 13; 1315232812Sjmallett uint64_t reserved_47_63 : 17; 1316232812Sjmallett#endif 1317232812Sjmallett } s; 1318232812Sjmallett struct cvmx_tim_ringx_ctl2_s cn68xx; 1319232812Sjmallett struct cvmx_tim_ringx_ctl2_s cn68xxp1; 1320232812Sjmallett}; 1321232812Sjmalletttypedef union cvmx_tim_ringx_ctl2 cvmx_tim_ringx_ctl2_t; 1322232812Sjmallett 1323232812Sjmallett/** 1324232812Sjmallett * cvmx_tim_ring#_dbg0 1325232812Sjmallett */ 1326232812Sjmallettunion cvmx_tim_ringx_dbg0 { 1327232812Sjmallett uint64_t u64; 1328232812Sjmallett struct cvmx_tim_ringx_dbg0_s { 1329232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1330232812Sjmallett uint64_t fr_rn_ht : 22; /**< Free Running Hardware Timer. Shared by all rings and is 1331232812Sjmallett used to generate the Timer Tick based on 1332232812Sjmallett FR_RN_TT. */ 1333232812Sjmallett uint64_t timercount : 22; /**< Timer Count represents the ring's offset. 1334232812Sjmallett Refer to TIM_RINGX_CTL0. */ 1335232812Sjmallett uint64_t cur_bucket : 20; /**< Current bucket. Indicates the ring's current bucket. 1336232812Sjmallett Refer to TIM_RINGX_CTL1.BUCKET. */ 1337232812Sjmallett#else 1338232812Sjmallett uint64_t cur_bucket : 20; 1339232812Sjmallett uint64_t timercount : 22; 1340232812Sjmallett uint64_t fr_rn_ht : 22; 1341232812Sjmallett#endif 1342232812Sjmallett } s; 1343232812Sjmallett struct cvmx_tim_ringx_dbg0_s cn68xx; 1344232812Sjmallett struct cvmx_tim_ringx_dbg0_s cn68xxp1; 1345232812Sjmallett}; 1346232812Sjmalletttypedef union cvmx_tim_ringx_dbg0 cvmx_tim_ringx_dbg0_t; 1347232812Sjmallett 1348232812Sjmallett/** 1349232812Sjmallett * cvmx_tim_ring#_dbg1 1350232812Sjmallett */ 1351232812Sjmallettunion cvmx_tim_ringx_dbg1 { 1352232812Sjmallett uint64_t u64; 1353232812Sjmallett struct cvmx_tim_ringx_dbg1_s { 1354232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1355232812Sjmallett uint64_t reserved_2_63 : 62; 1356232812Sjmallett uint64_t ring_esr : 2; /**< Ring Expiration Status Register. 1357232812Sjmallett This register hold the expiration status of the ring. 1358232812Sjmallett 2'b00 - Ring was recently traversed. 1359232812Sjmallett 2'b01 - Interval expired. Ring is queued to be traversed. 1360232812Sjmallett 2'b10 - 1st interval expiration while ring is queued to be 1361232812Sjmallett traversed. 1362232812Sjmallett 2'b11 - 2nd interval expiration while ring is queued to be 1363232812Sjmallett traversed. */ 1364232812Sjmallett#else 1365232812Sjmallett uint64_t ring_esr : 2; 1366232812Sjmallett uint64_t reserved_2_63 : 62; 1367232812Sjmallett#endif 1368232812Sjmallett } s; 1369232812Sjmallett struct cvmx_tim_ringx_dbg1_s cn68xx; 1370232812Sjmallett struct cvmx_tim_ringx_dbg1_s cn68xxp1; 1371232812Sjmallett}; 1372232812Sjmalletttypedef union cvmx_tim_ringx_dbg1 cvmx_tim_ringx_dbg1_t; 1373232812Sjmallett 1374232812Sjmallett#endif 1375