1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-ndf-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon ndf. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_NDF_DEFS_H__ 53232812Sjmallett#define __CVMX_NDF_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallett#define CVMX_NDF_BT_PG_INFO CVMX_NDF_BT_PG_INFO_FUNC() 57215976Sjmallettstatic inline uint64_t CVMX_NDF_BT_PG_INFO_FUNC(void) 58215976Sjmallett{ 59232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 60215976Sjmallett cvmx_warn("CVMX_NDF_BT_PG_INFO not supported on this chip\n"); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070001000018ull); 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_NDF_BT_PG_INFO (CVMX_ADD_IO_SEG(0x0001070001000018ull)) 65215976Sjmallett#endif 66215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67215976Sjmallett#define CVMX_NDF_CMD CVMX_NDF_CMD_FUNC() 68215976Sjmallettstatic inline uint64_t CVMX_NDF_CMD_FUNC(void) 69215976Sjmallett{ 70232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 71215976Sjmallett cvmx_warn("CVMX_NDF_CMD not supported on this chip\n"); 72215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070001000000ull); 73215976Sjmallett} 74215976Sjmallett#else 75215976Sjmallett#define CVMX_NDF_CMD (CVMX_ADD_IO_SEG(0x0001070001000000ull)) 76215976Sjmallett#endif 77215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78215976Sjmallett#define CVMX_NDF_DRBELL CVMX_NDF_DRBELL_FUNC() 79215976Sjmallettstatic inline uint64_t CVMX_NDF_DRBELL_FUNC(void) 80215976Sjmallett{ 81232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 82215976Sjmallett cvmx_warn("CVMX_NDF_DRBELL not supported on this chip\n"); 83215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070001000030ull); 84215976Sjmallett} 85215976Sjmallett#else 86215976Sjmallett#define CVMX_NDF_DRBELL (CVMX_ADD_IO_SEG(0x0001070001000030ull)) 87215976Sjmallett#endif 88215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89215976Sjmallett#define CVMX_NDF_ECC_CNT CVMX_NDF_ECC_CNT_FUNC() 90215976Sjmallettstatic inline uint64_t CVMX_NDF_ECC_CNT_FUNC(void) 91215976Sjmallett{ 92232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 93215976Sjmallett cvmx_warn("CVMX_NDF_ECC_CNT not supported on this chip\n"); 94215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070001000010ull); 95215976Sjmallett} 96215976Sjmallett#else 97215976Sjmallett#define CVMX_NDF_ECC_CNT (CVMX_ADD_IO_SEG(0x0001070001000010ull)) 98215976Sjmallett#endif 99215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100215976Sjmallett#define CVMX_NDF_INT CVMX_NDF_INT_FUNC() 101215976Sjmallettstatic inline uint64_t CVMX_NDF_INT_FUNC(void) 102215976Sjmallett{ 103232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 104215976Sjmallett cvmx_warn("CVMX_NDF_INT not supported on this chip\n"); 105215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070001000020ull); 106215976Sjmallett} 107215976Sjmallett#else 108215976Sjmallett#define CVMX_NDF_INT (CVMX_ADD_IO_SEG(0x0001070001000020ull)) 109215976Sjmallett#endif 110215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111215976Sjmallett#define CVMX_NDF_INT_EN CVMX_NDF_INT_EN_FUNC() 112215976Sjmallettstatic inline uint64_t CVMX_NDF_INT_EN_FUNC(void) 113215976Sjmallett{ 114232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 115215976Sjmallett cvmx_warn("CVMX_NDF_INT_EN not supported on this chip\n"); 116215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070001000028ull); 117215976Sjmallett} 118215976Sjmallett#else 119215976Sjmallett#define CVMX_NDF_INT_EN (CVMX_ADD_IO_SEG(0x0001070001000028ull)) 120215976Sjmallett#endif 121215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122215976Sjmallett#define CVMX_NDF_MISC CVMX_NDF_MISC_FUNC() 123215976Sjmallettstatic inline uint64_t CVMX_NDF_MISC_FUNC(void) 124215976Sjmallett{ 125232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 126215976Sjmallett cvmx_warn("CVMX_NDF_MISC not supported on this chip\n"); 127215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070001000008ull); 128215976Sjmallett} 129215976Sjmallett#else 130215976Sjmallett#define CVMX_NDF_MISC (CVMX_ADD_IO_SEG(0x0001070001000008ull)) 131215976Sjmallett#endif 132215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133215976Sjmallett#define CVMX_NDF_ST_REG CVMX_NDF_ST_REG_FUNC() 134215976Sjmallettstatic inline uint64_t CVMX_NDF_ST_REG_FUNC(void) 135215976Sjmallett{ 136232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 137215976Sjmallett cvmx_warn("CVMX_NDF_ST_REG not supported on this chip\n"); 138215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070001000038ull); 139215976Sjmallett} 140215976Sjmallett#else 141215976Sjmallett#define CVMX_NDF_ST_REG (CVMX_ADD_IO_SEG(0x0001070001000038ull)) 142215976Sjmallett#endif 143215976Sjmallett 144215976Sjmallett/** 145215976Sjmallett * cvmx_ndf_bt_pg_info 146215976Sjmallett * 147215976Sjmallett * Notes: 148215976Sjmallett * NDF_BT_PG_INFO provides page size and number of column plus row address cycles information. SW writes to this CSR 149215976Sjmallett * during boot from Nand Flash. Additionally SW also writes the multiplier value for timing parameters. This value is 150215976Sjmallett * used during boot, in the SET_TM_PARAM command. This information is used only by the boot load state machine and is 151215976Sjmallett * otherwise a don't care, once boot is disabled. Also, boot dma's do not use this value. 152215976Sjmallett * 153215976Sjmallett * Bytes per Nand Flash page = 2 ** (SIZE + 1) times 256 bytes. 154215976Sjmallett * 512, 1k, 2k, 4k, 8k, 16k, 32k and 64k are legal bytes per page values 155215976Sjmallett * 156215976Sjmallett * Legal values for ADR_CYC field are 3 through 8. SW CSR writes with a value less than 3 will write a 3 to this 157215976Sjmallett * field, and a SW CSR write with a value greater than 8, will write an 8 to this field. 158215976Sjmallett * 159215976Sjmallett * Like all NDF_... registers, 64-bit operations must be used to access this register 160215976Sjmallett */ 161232812Sjmallettunion cvmx_ndf_bt_pg_info { 162215976Sjmallett uint64_t u64; 163232812Sjmallett struct cvmx_ndf_bt_pg_info_s { 164232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 165215976Sjmallett uint64_t reserved_11_63 : 53; 166215976Sjmallett uint64_t t_mult : 4; /**< Boot time TIM_MULT[3:0] field of SET__TM_PAR[63:0] 167215976Sjmallett command */ 168215976Sjmallett uint64_t adr_cyc : 4; /**< # of column address cycles */ 169215976Sjmallett uint64_t size : 3; /**< bytes per page in the nand device */ 170215976Sjmallett#else 171215976Sjmallett uint64_t size : 3; 172215976Sjmallett uint64_t adr_cyc : 4; 173215976Sjmallett uint64_t t_mult : 4; 174215976Sjmallett uint64_t reserved_11_63 : 53; 175215976Sjmallett#endif 176215976Sjmallett } s; 177215976Sjmallett struct cvmx_ndf_bt_pg_info_s cn52xx; 178215976Sjmallett struct cvmx_ndf_bt_pg_info_s cn63xx; 179215976Sjmallett struct cvmx_ndf_bt_pg_info_s cn63xxp1; 180232812Sjmallett struct cvmx_ndf_bt_pg_info_s cn66xx; 181232812Sjmallett struct cvmx_ndf_bt_pg_info_s cn68xx; 182232812Sjmallett struct cvmx_ndf_bt_pg_info_s cn68xxp1; 183215976Sjmallett}; 184215976Sjmalletttypedef union cvmx_ndf_bt_pg_info cvmx_ndf_bt_pg_info_t; 185215976Sjmallett 186215976Sjmallett/** 187215976Sjmallett * cvmx_ndf_cmd 188215976Sjmallett * 189215976Sjmallett * Notes: 190215976Sjmallett * When SW reads this csr, RD_VAL bit in NDF_MISC csr is cleared to 0. SW must always write all 8 bytes whenever it writes 191215976Sjmallett * this csr. If there are fewer than 8 bytes left in the command sequence that SW wants the NAND flash controller to execute, it 192215976Sjmallett * must insert Idle (WAIT) commands to make up 8 bytes. SW also must ensure there is enough vacancy in the command fifo to accept these 193215976Sjmallett * 8 bytes, by first reading the FR_BYT field in the NDF_MISC csr. 194215976Sjmallett * 195215976Sjmallett * Like all NDF_... registers, 64-bit operations must be used to access this register 196215976Sjmallett */ 197232812Sjmallettunion cvmx_ndf_cmd { 198215976Sjmallett uint64_t u64; 199232812Sjmallett struct cvmx_ndf_cmd_s { 200232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 201215976Sjmallett uint64_t nf_cmd : 64; /**< 8 Command Bytes */ 202215976Sjmallett#else 203215976Sjmallett uint64_t nf_cmd : 64; 204215976Sjmallett#endif 205215976Sjmallett } s; 206215976Sjmallett struct cvmx_ndf_cmd_s cn52xx; 207215976Sjmallett struct cvmx_ndf_cmd_s cn63xx; 208215976Sjmallett struct cvmx_ndf_cmd_s cn63xxp1; 209232812Sjmallett struct cvmx_ndf_cmd_s cn66xx; 210232812Sjmallett struct cvmx_ndf_cmd_s cn68xx; 211232812Sjmallett struct cvmx_ndf_cmd_s cn68xxp1; 212215976Sjmallett}; 213215976Sjmalletttypedef union cvmx_ndf_cmd cvmx_ndf_cmd_t; 214215976Sjmallett 215215976Sjmallett/** 216215976Sjmallett * cvmx_ndf_drbell 217215976Sjmallett * 218215976Sjmallett * Notes: 219215976Sjmallett * SW csr writes will increment CNT by the signed 8 bit value being written. SW csr reads return the current CNT value. 220215976Sjmallett * HW will also modify the value of the CNT field. Everytime HW executes a BUS_ACQ[15:0] command, to arbitrate and win the 221215976Sjmallett * flash bus, it decrements the CNT field by 1. If the CNT field is already 0 or negative, HW command execution unit will 222215976Sjmallett * stall when it fetches the new BUS_ACQ[15:0] command, from the command fifo. Only when the SW writes to this CSR with a 223215976Sjmallett * non-zero data value, can the execution unit come out of the stalled condition, and resume execution. 224215976Sjmallett * 225215976Sjmallett * The intended use of this doorbell CSR is to control execution of the Nand Flash commands. The NDF execution unit 226215976Sjmallett * has to arbitrate for the flash bus, before it can enable a Nand Flash device connected to the Octeon chip, by 227215976Sjmallett * asserting the device's chip enable. Therefore SW should first load the command fifo, with a full sequence of 228215976Sjmallett * commands to perform a Nand Flash device task. This command sequence will start with a bus acquire command and 229215976Sjmallett * the last command in the sequence will be a bus release command. The execution unit will start execution of 230215976Sjmallett * the sequence only if the [CNT] field is non-zero when it fetches the bus acquire command, which is the first 231215976Sjmallett * command in this sequence. SW can also, load multiple such sequences, each starting with a chip enable command 232215976Sjmallett * and ending with a chip disable command, and then write a non-zero data value to this csr to increment the 233215976Sjmallett * CNT field by the number of the command sequences, loaded to the command fifo. 234215976Sjmallett * 235215976Sjmallett * Like all NDF_... registers, 64-bit operations must be used to access this register 236215976Sjmallett */ 237232812Sjmallettunion cvmx_ndf_drbell { 238215976Sjmallett uint64_t u64; 239232812Sjmallett struct cvmx_ndf_drbell_s { 240232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 241215976Sjmallett uint64_t reserved_8_63 : 56; 242215976Sjmallett uint64_t cnt : 8; /**< Doorbell count register, 2's complement 8 bit value */ 243215976Sjmallett#else 244215976Sjmallett uint64_t cnt : 8; 245215976Sjmallett uint64_t reserved_8_63 : 56; 246215976Sjmallett#endif 247215976Sjmallett } s; 248215976Sjmallett struct cvmx_ndf_drbell_s cn52xx; 249215976Sjmallett struct cvmx_ndf_drbell_s cn63xx; 250215976Sjmallett struct cvmx_ndf_drbell_s cn63xxp1; 251232812Sjmallett struct cvmx_ndf_drbell_s cn66xx; 252232812Sjmallett struct cvmx_ndf_drbell_s cn68xx; 253232812Sjmallett struct cvmx_ndf_drbell_s cn68xxp1; 254215976Sjmallett}; 255215976Sjmalletttypedef union cvmx_ndf_drbell cvmx_ndf_drbell_t; 256215976Sjmallett 257215976Sjmallett/** 258215976Sjmallett * cvmx_ndf_ecc_cnt 259215976Sjmallett * 260215976Sjmallett * Notes: 261215976Sjmallett * XOR_ECC[31:8] = [ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256] xor [ecc_258, ecc_257, ecc_256] 262215976Sjmallett * ecc_258, ecc_257 and ecc_256 are bytes stored in Nand Flash and read out during boot 263215976Sjmallett * ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256 are generated from data read out from Nand Flash 264215976Sjmallett * 265215976Sjmallett * Like all NDF_... registers, 64-bit operations must be used to access this register 266215976Sjmallett */ 267232812Sjmallettunion cvmx_ndf_ecc_cnt { 268215976Sjmallett uint64_t u64; 269232812Sjmallett struct cvmx_ndf_ecc_cnt_s { 270232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 271215976Sjmallett uint64_t reserved_32_63 : 32; 272215976Sjmallett uint64_t xor_ecc : 24; /**< result of XOR of ecc read bytes and ecc genarated 273215976Sjmallett bytes. The value pertains to the last 1 bit ecc err */ 274215976Sjmallett uint64_t ecc_err : 8; /**< Count = \# of 1 bit errors fixed during boot 275215976Sjmallett This count saturates instead of wrapping around. */ 276215976Sjmallett#else 277215976Sjmallett uint64_t ecc_err : 8; 278215976Sjmallett uint64_t xor_ecc : 24; 279215976Sjmallett uint64_t reserved_32_63 : 32; 280215976Sjmallett#endif 281215976Sjmallett } s; 282215976Sjmallett struct cvmx_ndf_ecc_cnt_s cn52xx; 283215976Sjmallett struct cvmx_ndf_ecc_cnt_s cn63xx; 284215976Sjmallett struct cvmx_ndf_ecc_cnt_s cn63xxp1; 285232812Sjmallett struct cvmx_ndf_ecc_cnt_s cn66xx; 286232812Sjmallett struct cvmx_ndf_ecc_cnt_s cn68xx; 287232812Sjmallett struct cvmx_ndf_ecc_cnt_s cn68xxp1; 288215976Sjmallett}; 289215976Sjmalletttypedef union cvmx_ndf_ecc_cnt cvmx_ndf_ecc_cnt_t; 290215976Sjmallett 291215976Sjmallett/** 292215976Sjmallett * cvmx_ndf_int 293215976Sjmallett * 294215976Sjmallett * Notes: 295215976Sjmallett * FULL status is updated when the command fifo becomes full as a result of SW writing a new command to it. 296215976Sjmallett * 297215976Sjmallett * EMPTY status is updated when the command fifo becomes empty as a result of command execution unit fetching the 298215976Sjmallett * last instruction out of the command fifo. 299215976Sjmallett * 300215976Sjmallett * Like all NDF_... registers, 64-bit operations must be used to access this register 301215976Sjmallett */ 302232812Sjmallettunion cvmx_ndf_int { 303215976Sjmallett uint64_t u64; 304232812Sjmallett struct cvmx_ndf_int_s { 305232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 306215976Sjmallett uint64_t reserved_7_63 : 57; 307215976Sjmallett uint64_t ovrf : 1; /**< NDF_CMD write when fifo is full. Generally a 308215976Sjmallett fatal error. */ 309215976Sjmallett uint64_t ecc_mult : 1; /**< Multi bit ECC error detected during boot */ 310215976Sjmallett uint64_t ecc_1bit : 1; /**< Single bit ECC error detected and fixed during boot */ 311215976Sjmallett uint64_t sm_bad : 1; /**< One of the state machines in a bad state */ 312215976Sjmallett uint64_t wdog : 1; /**< Watch Dog timer expired during command execution */ 313215976Sjmallett uint64_t full : 1; /**< Command fifo is full */ 314215976Sjmallett uint64_t empty : 1; /**< Command fifo is empty */ 315215976Sjmallett#else 316215976Sjmallett uint64_t empty : 1; 317215976Sjmallett uint64_t full : 1; 318215976Sjmallett uint64_t wdog : 1; 319215976Sjmallett uint64_t sm_bad : 1; 320215976Sjmallett uint64_t ecc_1bit : 1; 321215976Sjmallett uint64_t ecc_mult : 1; 322215976Sjmallett uint64_t ovrf : 1; 323215976Sjmallett uint64_t reserved_7_63 : 57; 324215976Sjmallett#endif 325215976Sjmallett } s; 326215976Sjmallett struct cvmx_ndf_int_s cn52xx; 327215976Sjmallett struct cvmx_ndf_int_s cn63xx; 328215976Sjmallett struct cvmx_ndf_int_s cn63xxp1; 329232812Sjmallett struct cvmx_ndf_int_s cn66xx; 330232812Sjmallett struct cvmx_ndf_int_s cn68xx; 331232812Sjmallett struct cvmx_ndf_int_s cn68xxp1; 332215976Sjmallett}; 333215976Sjmalletttypedef union cvmx_ndf_int cvmx_ndf_int_t; 334215976Sjmallett 335215976Sjmallett/** 336215976Sjmallett * cvmx_ndf_int_en 337215976Sjmallett * 338215976Sjmallett * Notes: 339215976Sjmallett * Like all NDF_... registers, 64-bit operations must be used to access this register 340215976Sjmallett * 341215976Sjmallett */ 342232812Sjmallettunion cvmx_ndf_int_en { 343215976Sjmallett uint64_t u64; 344232812Sjmallett struct cvmx_ndf_int_en_s { 345232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 346215976Sjmallett uint64_t reserved_7_63 : 57; 347215976Sjmallett uint64_t ovrf : 1; /**< Wrote to a full command fifo */ 348215976Sjmallett uint64_t ecc_mult : 1; /**< Multi bit ECC error detected during boot */ 349215976Sjmallett uint64_t ecc_1bit : 1; /**< Single bit ECC error detected and fixed during boot */ 350215976Sjmallett uint64_t sm_bad : 1; /**< One of the state machines in a bad state */ 351215976Sjmallett uint64_t wdog : 1; /**< Watch Dog timer expired during command execution */ 352215976Sjmallett uint64_t full : 1; /**< Command fifo is full */ 353215976Sjmallett uint64_t empty : 1; /**< Command fifo is empty */ 354215976Sjmallett#else 355215976Sjmallett uint64_t empty : 1; 356215976Sjmallett uint64_t full : 1; 357215976Sjmallett uint64_t wdog : 1; 358215976Sjmallett uint64_t sm_bad : 1; 359215976Sjmallett uint64_t ecc_1bit : 1; 360215976Sjmallett uint64_t ecc_mult : 1; 361215976Sjmallett uint64_t ovrf : 1; 362215976Sjmallett uint64_t reserved_7_63 : 57; 363215976Sjmallett#endif 364215976Sjmallett } s; 365215976Sjmallett struct cvmx_ndf_int_en_s cn52xx; 366215976Sjmallett struct cvmx_ndf_int_en_s cn63xx; 367215976Sjmallett struct cvmx_ndf_int_en_s cn63xxp1; 368232812Sjmallett struct cvmx_ndf_int_en_s cn66xx; 369232812Sjmallett struct cvmx_ndf_int_en_s cn68xx; 370232812Sjmallett struct cvmx_ndf_int_en_s cn68xxp1; 371215976Sjmallett}; 372215976Sjmalletttypedef union cvmx_ndf_int_en cvmx_ndf_int_en_t; 373215976Sjmallett 374215976Sjmallett/** 375215976Sjmallett * cvmx_ndf_misc 376215976Sjmallett * 377215976Sjmallett * Notes: 378215976Sjmallett * NBR_HWM this field specifies the high water mark for the NCB outbound load/store commands receive fifo. 379215976Sjmallett * the fifo size is 16 entries. 380215976Sjmallett * 381215976Sjmallett * WAIT_CNT this field allows glitch filtering of the WAIT_n input to octeon, from Flash Memory. The count 382215976Sjmallett * represents number of eclk cycles. 383215976Sjmallett * 384215976Sjmallett * FR_BYT this field specifies \# of unfilled bytes in the command fifo. Bytes become unfilled as commands 385215976Sjmallett * complete execution and exit. (fifo is 256 bytes when BT_DIS=0, and 1536 bytes when BT_DIS=1) 386215976Sjmallett * 387215976Sjmallett * RD_DONE this W1C bit is set to 1 by HW when it reads the last 8 bytes out of the command fifo, 388215976Sjmallett * in response to RD_CMD bit being set to 1 by SW. 389215976Sjmallett * 390215976Sjmallett * RD_VAL this read only bit is set to 1 by HW when it reads next 8 bytes from command fifo in response 391215976Sjmallett * to RD_CMD bit being set to 1. A SW read of NDF_CMD csr clears this bit to 0. 392215976Sjmallett * 393215976Sjmallett * RD_CMD this R/W bit starts read out from the command fifo, 8 bytes at a time. SW should first read the 394215976Sjmallett * RD_VAL bit in this csr to see if next 8 bytes from the command fifo are available in the 395215976Sjmallett * NDF_CMD csr. All command fifo reads start and end on an 8 byte boundary. A RD_CMD in the 396215976Sjmallett * middle of command execution will cause the execution to freeze until RD_DONE is set to 1. RD_CMD 397215976Sjmallett * bit will be cleared on any NDF_CMD csr write by SW. 398215976Sjmallett * 399215976Sjmallett * BT_DMA this indicates to the NAND flash boot control state machine that boot dma read can begin. 400215976Sjmallett * SW should set this bit to 1 after SW has loaded the command fifo. HW sets the bit to 0 401215976Sjmallett * when boot dma command execution is complete. If chip enable 0 is not nand flash, this bit is 402215976Sjmallett * permanently 1'b0 with SW writes ignored. Whenever BT_DIS=1, this bit will be 0. 403215976Sjmallett * 404215976Sjmallett * BT_DIS this R/W bit indicates to NAND flash boot control state machine that boot operation has ended. 405215976Sjmallett * whenever this bit changes from 0 to a 1, the command fifo is emptied as a side effect. This bit must 406215976Sjmallett * never be set when booting from nand flash and region zero is enabled. 407215976Sjmallett * 408215976Sjmallett * EX_DIS When 1, command execution stops after completing execution of all commands currently in the command 409215976Sjmallett * fifo. Once command execution has stopped, and then new commands are loaded into the command fifo, execution 410215976Sjmallett * will not resume as long as this bit is 1. When this bit is 0, command execution will resume if command fifo 411215976Sjmallett * is not empty. EX_DIS should be set to 1, during boot i.e. when BT_DIS = 0. 412215976Sjmallett * 413215976Sjmallett * RST_FF reset command fifo to make it empty, any command inflight is not aborted before reseting 414215976Sjmallett * the fifo. The fifo comes up empty at the end of power on reset. 415215976Sjmallett * 416215976Sjmallett * Like all NDF_... registers, 64-bit operations must be used to access this register 417215976Sjmallett */ 418232812Sjmallettunion cvmx_ndf_misc { 419215976Sjmallett uint64_t u64; 420232812Sjmallett struct cvmx_ndf_misc_s { 421232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 422215976Sjmallett uint64_t reserved_28_63 : 36; 423215976Sjmallett uint64_t mb_dis : 1; /**< Disable multibit error hangs and allow boot loads 424215976Sjmallett or boot dma's proceed as if no multi bit errors 425215976Sjmallett occured. HW will fix single bit errors as usual */ 426215976Sjmallett uint64_t nbr_hwm : 3; /**< Hi Water mark for NBR fifo or load/stores */ 427215976Sjmallett uint64_t wait_cnt : 6; /**< WAIT input filter count */ 428215976Sjmallett uint64_t fr_byt : 11; /**< Number of unfilled Command fifo bytes */ 429215976Sjmallett uint64_t rd_done : 1; /**< This W1C bit is set to 1 by HW when it completes 430215976Sjmallett command fifo read out, in response to RD_CMD */ 431215976Sjmallett uint64_t rd_val : 1; /**< This RO bit is set to 1 by HW when it reads next 8 432215976Sjmallett bytes from Command fifo into the NDF_CMD csr 433215976Sjmallett SW reads NDF_CMD csr, HW clears this bit to 0 */ 434215976Sjmallett uint64_t rd_cmd : 1; /**< When 1, HW reads out contents of the Command fifo 8 435215976Sjmallett bytes at a time into the NDF_CMD csr */ 436215976Sjmallett uint64_t bt_dma : 1; /**< When set to 1, boot time dma is enabled */ 437215976Sjmallett uint64_t bt_dis : 1; /**< When boot operation is over SW must set to 1 438215976Sjmallett causes boot state mchines to sleep */ 439215976Sjmallett uint64_t ex_dis : 1; /**< When set to 1, suspends execution of commands at 440215976Sjmallett next command in the fifo. */ 441215976Sjmallett uint64_t rst_ff : 1; /**< 1=reset command fifo to make it empty, 442215976Sjmallett 0=normal operation */ 443215976Sjmallett#else 444215976Sjmallett uint64_t rst_ff : 1; 445215976Sjmallett uint64_t ex_dis : 1; 446215976Sjmallett uint64_t bt_dis : 1; 447215976Sjmallett uint64_t bt_dma : 1; 448215976Sjmallett uint64_t rd_cmd : 1; 449215976Sjmallett uint64_t rd_val : 1; 450215976Sjmallett uint64_t rd_done : 1; 451215976Sjmallett uint64_t fr_byt : 11; 452215976Sjmallett uint64_t wait_cnt : 6; 453215976Sjmallett uint64_t nbr_hwm : 3; 454215976Sjmallett uint64_t mb_dis : 1; 455215976Sjmallett uint64_t reserved_28_63 : 36; 456215976Sjmallett#endif 457215976Sjmallett } s; 458232812Sjmallett struct cvmx_ndf_misc_cn52xx { 459232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 460215976Sjmallett uint64_t reserved_27_63 : 37; 461215976Sjmallett uint64_t nbr_hwm : 3; /**< Hi Water mark for NBR fifo or load/stores */ 462215976Sjmallett uint64_t wait_cnt : 6; /**< WAIT input filter count */ 463215976Sjmallett uint64_t fr_byt : 11; /**< Number of unfilled Command fifo bytes */ 464215976Sjmallett uint64_t rd_done : 1; /**< This W1C bit is set to 1 by HW when it completes 465215976Sjmallett command fifo read out, in response to RD_CMD */ 466215976Sjmallett uint64_t rd_val : 1; /**< This RO bit is set to 1 by HW when it reads next 8 467215976Sjmallett bytes from Command fifo into the NDF_CMD csr 468215976Sjmallett SW reads NDF_CMD csr, HW clears this bit to 0 */ 469215976Sjmallett uint64_t rd_cmd : 1; /**< When 1, HW reads out contents of the Command fifo 8 470215976Sjmallett bytes at a time into the NDF_CMD csr */ 471215976Sjmallett uint64_t bt_dma : 1; /**< When set to 1, boot time dma is enabled */ 472215976Sjmallett uint64_t bt_dis : 1; /**< When boot operation is over SW must set to 1 473215976Sjmallett causes boot state mchines to sleep */ 474215976Sjmallett uint64_t ex_dis : 1; /**< When set to 1, suspends execution of commands at 475215976Sjmallett next command in the fifo. */ 476215976Sjmallett uint64_t rst_ff : 1; /**< 1=reset command fifo to make it empty, 477215976Sjmallett 0=normal operation */ 478215976Sjmallett#else 479215976Sjmallett uint64_t rst_ff : 1; 480215976Sjmallett uint64_t ex_dis : 1; 481215976Sjmallett uint64_t bt_dis : 1; 482215976Sjmallett uint64_t bt_dma : 1; 483215976Sjmallett uint64_t rd_cmd : 1; 484215976Sjmallett uint64_t rd_val : 1; 485215976Sjmallett uint64_t rd_done : 1; 486215976Sjmallett uint64_t fr_byt : 11; 487215976Sjmallett uint64_t wait_cnt : 6; 488215976Sjmallett uint64_t nbr_hwm : 3; 489215976Sjmallett uint64_t reserved_27_63 : 37; 490215976Sjmallett#endif 491215976Sjmallett } cn52xx; 492215976Sjmallett struct cvmx_ndf_misc_s cn63xx; 493215976Sjmallett struct cvmx_ndf_misc_s cn63xxp1; 494232812Sjmallett struct cvmx_ndf_misc_s cn66xx; 495232812Sjmallett struct cvmx_ndf_misc_s cn68xx; 496232812Sjmallett struct cvmx_ndf_misc_s cn68xxp1; 497215976Sjmallett}; 498215976Sjmalletttypedef union cvmx_ndf_misc cvmx_ndf_misc_t; 499215976Sjmallett 500215976Sjmallett/** 501215976Sjmallett * cvmx_ndf_st_reg 502215976Sjmallett * 503215976Sjmallett * Notes: 504215976Sjmallett * This CSR aggregates all state machines used in nand flash controller for debug. 505215976Sjmallett * Like all NDF_... registers, 64-bit operations must be used to access this register 506215976Sjmallett */ 507232812Sjmallettunion cvmx_ndf_st_reg { 508215976Sjmallett uint64_t u64; 509232812Sjmallett struct cvmx_ndf_st_reg_s { 510232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 511215976Sjmallett uint64_t reserved_16_63 : 48; 512215976Sjmallett uint64_t exe_idle : 1; /**< Command Execution status 1=IDLE, 0=Busy 513215976Sjmallett 1 means execution of command sequence is complete 514215976Sjmallett and command fifo is empty */ 515215976Sjmallett uint64_t exe_sm : 4; /**< Command Execution State machine states */ 516215976Sjmallett uint64_t bt_sm : 4; /**< Boot load and Boot dma State machine states */ 517215976Sjmallett uint64_t rd_ff_bad : 1; /**< CMD fifo read back State machine in bad state */ 518215976Sjmallett uint64_t rd_ff : 2; /**< CMD fifo read back State machine states */ 519215976Sjmallett uint64_t main_bad : 1; /**< Main State machine in bad state */ 520215976Sjmallett uint64_t main_sm : 3; /**< Main State machine states */ 521215976Sjmallett#else 522215976Sjmallett uint64_t main_sm : 3; 523215976Sjmallett uint64_t main_bad : 1; 524215976Sjmallett uint64_t rd_ff : 2; 525215976Sjmallett uint64_t rd_ff_bad : 1; 526215976Sjmallett uint64_t bt_sm : 4; 527215976Sjmallett uint64_t exe_sm : 4; 528215976Sjmallett uint64_t exe_idle : 1; 529215976Sjmallett uint64_t reserved_16_63 : 48; 530215976Sjmallett#endif 531215976Sjmallett } s; 532215976Sjmallett struct cvmx_ndf_st_reg_s cn52xx; 533215976Sjmallett struct cvmx_ndf_st_reg_s cn63xx; 534215976Sjmallett struct cvmx_ndf_st_reg_s cn63xxp1; 535232812Sjmallett struct cvmx_ndf_st_reg_s cn66xx; 536232812Sjmallett struct cvmx_ndf_st_reg_s cn68xx; 537232812Sjmallett struct cvmx_ndf_st_reg_s cn68xxp1; 538215976Sjmallett}; 539215976Sjmalletttypedef union cvmx_ndf_st_reg cvmx_ndf_st_reg_t; 540215976Sjmallett 541215976Sjmallett#endif 542