1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-asxx-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon asxx. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_ASXX_DEFS_H__ 53#define __CVMX_ASXX_DEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_ASXX_GMII_RX_CLK_SET(unsigned long block_id) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 60 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 61 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))))) 62 cvmx_warn("CVMX_ASXX_GMII_RX_CLK_SET(%lu) is invalid on this chip\n", block_id); 63 return CVMX_ADD_IO_SEG(0x00011800B0000180ull); 64} 65#else 66#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull)) 67#endif 68#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 69static inline uint64_t CVMX_ASXX_GMII_RX_DAT_SET(unsigned long block_id) 70{ 71 if (!( 72 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 73 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 74 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))))) 75 cvmx_warn("CVMX_ASXX_GMII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id); 76 return CVMX_ADD_IO_SEG(0x00011800B0000188ull); 77} 78#else 79#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull)) 80#endif 81#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 82static inline uint64_t CVMX_ASXX_INT_EN(unsigned long block_id) 83{ 84 if (!( 85 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 86 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 87 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 88 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 89 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 90 cvmx_warn("CVMX_ASXX_INT_EN(%lu) is invalid on this chip\n", block_id); 91 return CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull; 92} 93#else 94#define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull) 95#endif 96#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 97static inline uint64_t CVMX_ASXX_INT_REG(unsigned long block_id) 98{ 99 if (!( 100 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 101 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 102 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 103 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 104 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 105 cvmx_warn("CVMX_ASXX_INT_REG(%lu) is invalid on this chip\n", block_id); 106 return CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull; 107} 108#else 109#define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull) 110#endif 111#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 112static inline uint64_t CVMX_ASXX_MII_RX_DAT_SET(unsigned long block_id) 113{ 114 if (!( 115 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 116 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))))) 117 cvmx_warn("CVMX_ASXX_MII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id); 118 return CVMX_ADD_IO_SEG(0x00011800B0000190ull); 119} 120#else 121#define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull)) 122#endif 123#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 124static inline uint64_t CVMX_ASXX_PRT_LOOP(unsigned long block_id) 125{ 126 if (!( 127 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 128 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 129 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 130 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 131 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 132 cvmx_warn("CVMX_ASXX_PRT_LOOP(%lu) is invalid on this chip\n", block_id); 133 return CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull; 134} 135#else 136#define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull) 137#endif 138#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 139static inline uint64_t CVMX_ASXX_RLD_BYPASS(unsigned long block_id) 140{ 141 if (!( 142 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 143 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 144 cvmx_warn("CVMX_ASXX_RLD_BYPASS(%lu) is invalid on this chip\n", block_id); 145 return CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull; 146} 147#else 148#define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull) 149#endif 150#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 151static inline uint64_t CVMX_ASXX_RLD_BYPASS_SETTING(unsigned long block_id) 152{ 153 if (!( 154 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 155 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 156 cvmx_warn("CVMX_ASXX_RLD_BYPASS_SETTING(%lu) is invalid on this chip\n", block_id); 157 return CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull; 158} 159#else 160#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull) 161#endif 162#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 163static inline uint64_t CVMX_ASXX_RLD_COMP(unsigned long block_id) 164{ 165 if (!( 166 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 167 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 168 cvmx_warn("CVMX_ASXX_RLD_COMP(%lu) is invalid on this chip\n", block_id); 169 return CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull; 170} 171#else 172#define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull) 173#endif 174#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 175static inline uint64_t CVMX_ASXX_RLD_DATA_DRV(unsigned long block_id) 176{ 177 if (!( 178 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 179 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 180 cvmx_warn("CVMX_ASXX_RLD_DATA_DRV(%lu) is invalid on this chip\n", block_id); 181 return CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull; 182} 183#else 184#define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull) 185#endif 186#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 187static inline uint64_t CVMX_ASXX_RLD_FCRAM_MODE(unsigned long block_id) 188{ 189 if (!( 190 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))))) 191 cvmx_warn("CVMX_ASXX_RLD_FCRAM_MODE(%lu) is invalid on this chip\n", block_id); 192 return CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull; 193} 194#else 195#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull) 196#endif 197#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 198static inline uint64_t CVMX_ASXX_RLD_NCTL_STRONG(unsigned long block_id) 199{ 200 if (!( 201 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 202 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 203 cvmx_warn("CVMX_ASXX_RLD_NCTL_STRONG(%lu) is invalid on this chip\n", block_id); 204 return CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull; 205} 206#else 207#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull) 208#endif 209#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210static inline uint64_t CVMX_ASXX_RLD_NCTL_WEAK(unsigned long block_id) 211{ 212 if (!( 213 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 214 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 215 cvmx_warn("CVMX_ASXX_RLD_NCTL_WEAK(%lu) is invalid on this chip\n", block_id); 216 return CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull; 217} 218#else 219#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull) 220#endif 221#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 222static inline uint64_t CVMX_ASXX_RLD_PCTL_STRONG(unsigned long block_id) 223{ 224 if (!( 225 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 226 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 227 cvmx_warn("CVMX_ASXX_RLD_PCTL_STRONG(%lu) is invalid on this chip\n", block_id); 228 return CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull; 229} 230#else 231#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull) 232#endif 233#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 234static inline uint64_t CVMX_ASXX_RLD_PCTL_WEAK(unsigned long block_id) 235{ 236 if (!( 237 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 238 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 239 cvmx_warn("CVMX_ASXX_RLD_PCTL_WEAK(%lu) is invalid on this chip\n", block_id); 240 return CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull; 241} 242#else 243#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull) 244#endif 245#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 246static inline uint64_t CVMX_ASXX_RLD_SETTING(unsigned long block_id) 247{ 248 if (!( 249 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 250 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 251 cvmx_warn("CVMX_ASXX_RLD_SETTING(%lu) is invalid on this chip\n", block_id); 252 return CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull; 253} 254#else 255#define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull) 256#endif 257#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 258static inline uint64_t CVMX_ASXX_RX_CLK_SETX(unsigned long offset, unsigned long block_id) 259{ 260 if (!( 261 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) || 262 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) || 263 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) || 264 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) || 265 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))))) 266 cvmx_warn("CVMX_ASXX_RX_CLK_SETX(%lu,%lu) is invalid on this chip\n", offset, block_id); 267 return CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8; 268} 269#else 270#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) 271#endif 272#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 273static inline uint64_t CVMX_ASXX_RX_PRT_EN(unsigned long block_id) 274{ 275 if (!( 276 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 277 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 278 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 279 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 280 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 281 cvmx_warn("CVMX_ASXX_RX_PRT_EN(%lu) is invalid on this chip\n", block_id); 282 return CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull; 283} 284#else 285#define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull) 286#endif 287#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 288static inline uint64_t CVMX_ASXX_RX_WOL(unsigned long block_id) 289{ 290 if (!( 291 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))))) 292 cvmx_warn("CVMX_ASXX_RX_WOL(%lu) is invalid on this chip\n", block_id); 293 return CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull; 294} 295#else 296#define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull) 297#endif 298#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 299static inline uint64_t CVMX_ASXX_RX_WOL_MSK(unsigned long block_id) 300{ 301 if (!( 302 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))))) 303 cvmx_warn("CVMX_ASXX_RX_WOL_MSK(%lu) is invalid on this chip\n", block_id); 304 return CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull; 305} 306#else 307#define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull) 308#endif 309#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 310static inline uint64_t CVMX_ASXX_RX_WOL_POWOK(unsigned long block_id) 311{ 312 if (!( 313 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))))) 314 cvmx_warn("CVMX_ASXX_RX_WOL_POWOK(%lu) is invalid on this chip\n", block_id); 315 return CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull; 316} 317#else 318#define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull) 319#endif 320#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 321static inline uint64_t CVMX_ASXX_RX_WOL_SIG(unsigned long block_id) 322{ 323 if (!( 324 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))))) 325 cvmx_warn("CVMX_ASXX_RX_WOL_SIG(%lu) is invalid on this chip\n", block_id); 326 return CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull; 327} 328#else 329#define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull) 330#endif 331#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 332static inline uint64_t CVMX_ASXX_TX_CLK_SETX(unsigned long offset, unsigned long block_id) 333{ 334 if (!( 335 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) || 336 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) || 337 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) || 338 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) || 339 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))))) 340 cvmx_warn("CVMX_ASXX_TX_CLK_SETX(%lu,%lu) is invalid on this chip\n", offset, block_id); 341 return CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8; 342} 343#else 344#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) 345#endif 346#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 347static inline uint64_t CVMX_ASXX_TX_COMP_BYP(unsigned long block_id) 348{ 349 if (!( 350 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 351 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 352 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 353 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 354 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 355 cvmx_warn("CVMX_ASXX_TX_COMP_BYP(%lu) is invalid on this chip\n", block_id); 356 return CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull; 357} 358#else 359#define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull) 360#endif 361#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 362static inline uint64_t CVMX_ASXX_TX_HI_WATERX(unsigned long offset, unsigned long block_id) 363{ 364 if (!( 365 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) || 366 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) || 367 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) || 368 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) || 369 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))))) 370 cvmx_warn("CVMX_ASXX_TX_HI_WATERX(%lu,%lu) is invalid on this chip\n", offset, block_id); 371 return CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8; 372} 373#else 374#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) 375#endif 376#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 377static inline uint64_t CVMX_ASXX_TX_PRT_EN(unsigned long block_id) 378{ 379 if (!( 380 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 381 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 382 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 383 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 384 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 385 cvmx_warn("CVMX_ASXX_TX_PRT_EN(%lu) is invalid on this chip\n", block_id); 386 return CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull; 387} 388#else 389#define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull) 390#endif 391 392/** 393 * cvmx_asx#_gmii_rx_clk_set 394 * 395 * ASX_GMII_RX_CLK_SET = GMII Clock delay setting 396 * 397 */ 398union cvmx_asxx_gmii_rx_clk_set { 399 uint64_t u64; 400 struct cvmx_asxx_gmii_rx_clk_set_s { 401#ifdef __BIG_ENDIAN_BITFIELD 402 uint64_t reserved_5_63 : 59; 403 uint64_t setting : 5; /**< Setting to place on the RXCLK (GMII receive clk) 404 delay line. The intrinsic delay can range from 405 50ps to 80ps per tap. */ 406#else 407 uint64_t setting : 5; 408 uint64_t reserved_5_63 : 59; 409#endif 410 } s; 411 struct cvmx_asxx_gmii_rx_clk_set_s cn30xx; 412 struct cvmx_asxx_gmii_rx_clk_set_s cn31xx; 413 struct cvmx_asxx_gmii_rx_clk_set_s cn50xx; 414}; 415typedef union cvmx_asxx_gmii_rx_clk_set cvmx_asxx_gmii_rx_clk_set_t; 416 417/** 418 * cvmx_asx#_gmii_rx_dat_set 419 * 420 * ASX_GMII_RX_DAT_SET = GMII Clock delay setting 421 * 422 */ 423union cvmx_asxx_gmii_rx_dat_set { 424 uint64_t u64; 425 struct cvmx_asxx_gmii_rx_dat_set_s { 426#ifdef __BIG_ENDIAN_BITFIELD 427 uint64_t reserved_5_63 : 59; 428 uint64_t setting : 5; /**< Setting to place on the RXD (GMII receive data) 429 delay lines. The intrinsic delay can range from 430 50ps to 80ps per tap. */ 431#else 432 uint64_t setting : 5; 433 uint64_t reserved_5_63 : 59; 434#endif 435 } s; 436 struct cvmx_asxx_gmii_rx_dat_set_s cn30xx; 437 struct cvmx_asxx_gmii_rx_dat_set_s cn31xx; 438 struct cvmx_asxx_gmii_rx_dat_set_s cn50xx; 439}; 440typedef union cvmx_asxx_gmii_rx_dat_set cvmx_asxx_gmii_rx_dat_set_t; 441 442/** 443 * cvmx_asx#_int_en 444 * 445 * ASX_INT_EN = Interrupt Enable 446 * 447 */ 448union cvmx_asxx_int_en { 449 uint64_t u64; 450 struct cvmx_asxx_int_en_s { 451#ifdef __BIG_ENDIAN_BITFIELD 452 uint64_t reserved_12_63 : 52; 453 uint64_t txpsh : 4; /**< TX FIFO overflow on RMGII port */ 454 uint64_t txpop : 4; /**< TX FIFO underflow on RMGII port */ 455 uint64_t ovrflw : 4; /**< RX FIFO overflow on RMGII port */ 456#else 457 uint64_t ovrflw : 4; 458 uint64_t txpop : 4; 459 uint64_t txpsh : 4; 460 uint64_t reserved_12_63 : 52; 461#endif 462 } s; 463 struct cvmx_asxx_int_en_cn30xx { 464#ifdef __BIG_ENDIAN_BITFIELD 465 uint64_t reserved_11_63 : 53; 466 uint64_t txpsh : 3; /**< TX FIFO overflow on RMGII port */ 467 uint64_t reserved_7_7 : 1; 468 uint64_t txpop : 3; /**< TX FIFO underflow on RMGII port */ 469 uint64_t reserved_3_3 : 1; 470 uint64_t ovrflw : 3; /**< RX FIFO overflow on RMGII port */ 471#else 472 uint64_t ovrflw : 3; 473 uint64_t reserved_3_3 : 1; 474 uint64_t txpop : 3; 475 uint64_t reserved_7_7 : 1; 476 uint64_t txpsh : 3; 477 uint64_t reserved_11_63 : 53; 478#endif 479 } cn30xx; 480 struct cvmx_asxx_int_en_cn30xx cn31xx; 481 struct cvmx_asxx_int_en_s cn38xx; 482 struct cvmx_asxx_int_en_s cn38xxp2; 483 struct cvmx_asxx_int_en_cn30xx cn50xx; 484 struct cvmx_asxx_int_en_s cn58xx; 485 struct cvmx_asxx_int_en_s cn58xxp1; 486}; 487typedef union cvmx_asxx_int_en cvmx_asxx_int_en_t; 488 489/** 490 * cvmx_asx#_int_reg 491 * 492 * ASX_INT_REG = Interrupt Register 493 * 494 */ 495union cvmx_asxx_int_reg { 496 uint64_t u64; 497 struct cvmx_asxx_int_reg_s { 498#ifdef __BIG_ENDIAN_BITFIELD 499 uint64_t reserved_12_63 : 52; 500 uint64_t txpsh : 4; /**< TX FIFO overflow on RMGII port */ 501 uint64_t txpop : 4; /**< TX FIFO underflow on RMGII port */ 502 uint64_t ovrflw : 4; /**< RX FIFO overflow on RMGII port */ 503#else 504 uint64_t ovrflw : 4; 505 uint64_t txpop : 4; 506 uint64_t txpsh : 4; 507 uint64_t reserved_12_63 : 52; 508#endif 509 } s; 510 struct cvmx_asxx_int_reg_cn30xx { 511#ifdef __BIG_ENDIAN_BITFIELD 512 uint64_t reserved_11_63 : 53; 513 uint64_t txpsh : 3; /**< TX FIFO overflow on RMGII port */ 514 uint64_t reserved_7_7 : 1; 515 uint64_t txpop : 3; /**< TX FIFO underflow on RMGII port */ 516 uint64_t reserved_3_3 : 1; 517 uint64_t ovrflw : 3; /**< RX FIFO overflow on RMGII port */ 518#else 519 uint64_t ovrflw : 3; 520 uint64_t reserved_3_3 : 1; 521 uint64_t txpop : 3; 522 uint64_t reserved_7_7 : 1; 523 uint64_t txpsh : 3; 524 uint64_t reserved_11_63 : 53; 525#endif 526 } cn30xx; 527 struct cvmx_asxx_int_reg_cn30xx cn31xx; 528 struct cvmx_asxx_int_reg_s cn38xx; 529 struct cvmx_asxx_int_reg_s cn38xxp2; 530 struct cvmx_asxx_int_reg_cn30xx cn50xx; 531 struct cvmx_asxx_int_reg_s cn58xx; 532 struct cvmx_asxx_int_reg_s cn58xxp1; 533}; 534typedef union cvmx_asxx_int_reg cvmx_asxx_int_reg_t; 535 536/** 537 * cvmx_asx#_mii_rx_dat_set 538 * 539 * ASX_MII_RX_DAT_SET = GMII Clock delay setting 540 * 541 */ 542union cvmx_asxx_mii_rx_dat_set { 543 uint64_t u64; 544 struct cvmx_asxx_mii_rx_dat_set_s { 545#ifdef __BIG_ENDIAN_BITFIELD 546 uint64_t reserved_5_63 : 59; 547 uint64_t setting : 5; /**< Setting to place on the RXD (MII receive data) 548 delay lines. The intrinsic delay can range from 549 50ps to 80ps per tap. */ 550#else 551 uint64_t setting : 5; 552 uint64_t reserved_5_63 : 59; 553#endif 554 } s; 555 struct cvmx_asxx_mii_rx_dat_set_s cn30xx; 556 struct cvmx_asxx_mii_rx_dat_set_s cn50xx; 557}; 558typedef union cvmx_asxx_mii_rx_dat_set cvmx_asxx_mii_rx_dat_set_t; 559 560/** 561 * cvmx_asx#_prt_loop 562 * 563 * ASX_PRT_LOOP = Internal Loopback mode - TX FIFO output goes into RX FIFO (and maybe pins) 564 * 565 */ 566union cvmx_asxx_prt_loop { 567 uint64_t u64; 568 struct cvmx_asxx_prt_loop_s { 569#ifdef __BIG_ENDIAN_BITFIELD 570 uint64_t reserved_8_63 : 56; 571 uint64_t ext_loop : 4; /**< External Loopback Enable 572 0 = No Loopback (TX FIFO is filled by RMGII) 573 1 = RX FIFO drives the TX FIFO 574 - GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex) 575 - GMX_PRT_CFG[SPEED] must be 1 (GigE speed) 576 - core clock > 250MHZ 577 - rxc must not deviate from the +-50ppm 578 - if txc>rxc, idle cycle may drop over time */ 579 uint64_t int_loop : 4; /**< Internal Loopback Enable 580 0 = No Loopback (RX FIFO is filled by RMGII pins) 581 1 = TX FIFO drives the RX FIFO 582 Note, in internal loop-back mode, the RGMII link 583 status is not used (since there is no real PHY). 584 Software cannot use the inband status. */ 585#else 586 uint64_t int_loop : 4; 587 uint64_t ext_loop : 4; 588 uint64_t reserved_8_63 : 56; 589#endif 590 } s; 591 struct cvmx_asxx_prt_loop_cn30xx { 592#ifdef __BIG_ENDIAN_BITFIELD 593 uint64_t reserved_7_63 : 57; 594 uint64_t ext_loop : 3; /**< External Loopback Enable 595 0 = No Loopback (TX FIFO is filled by RMGII) 596 1 = RX FIFO drives the TX FIFO 597 - GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex) 598 - GMX_PRT_CFG[SPEED] must be 1 (GigE speed) 599 - core clock > 250MHZ 600 - rxc must not deviate from the +-50ppm 601 - if txc>rxc, idle cycle may drop over time */ 602 uint64_t reserved_3_3 : 1; 603 uint64_t int_loop : 3; /**< Internal Loopback Enable 604 0 = No Loopback (RX FIFO is filled by RMGII pins) 605 1 = TX FIFO drives the RX FIFO 606 - GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex) 607 - GMX_PRT_CFG[SPEED] must be 1 (GigE speed) 608 - GMX_TX_CLK[CLK_CNT] must be 1 609 Note, in internal loop-back mode, the RGMII link 610 status is not used (since there is no real PHY). 611 Software cannot use the inband status. */ 612#else 613 uint64_t int_loop : 3; 614 uint64_t reserved_3_3 : 1; 615 uint64_t ext_loop : 3; 616 uint64_t reserved_7_63 : 57; 617#endif 618 } cn30xx; 619 struct cvmx_asxx_prt_loop_cn30xx cn31xx; 620 struct cvmx_asxx_prt_loop_s cn38xx; 621 struct cvmx_asxx_prt_loop_s cn38xxp2; 622 struct cvmx_asxx_prt_loop_cn30xx cn50xx; 623 struct cvmx_asxx_prt_loop_s cn58xx; 624 struct cvmx_asxx_prt_loop_s cn58xxp1; 625}; 626typedef union cvmx_asxx_prt_loop cvmx_asxx_prt_loop_t; 627 628/** 629 * cvmx_asx#_rld_bypass 630 * 631 * ASX_RLD_BYPASS 632 * 633 */ 634union cvmx_asxx_rld_bypass { 635 uint64_t u64; 636 struct cvmx_asxx_rld_bypass_s { 637#ifdef __BIG_ENDIAN_BITFIELD 638 uint64_t reserved_1_63 : 63; 639 uint64_t bypass : 1; /**< When set, the rld_dll setting is bypassed with 640 ASX_RLD_BYPASS_SETTING */ 641#else 642 uint64_t bypass : 1; 643 uint64_t reserved_1_63 : 63; 644#endif 645 } s; 646 struct cvmx_asxx_rld_bypass_s cn38xx; 647 struct cvmx_asxx_rld_bypass_s cn38xxp2; 648 struct cvmx_asxx_rld_bypass_s cn58xx; 649 struct cvmx_asxx_rld_bypass_s cn58xxp1; 650}; 651typedef union cvmx_asxx_rld_bypass cvmx_asxx_rld_bypass_t; 652 653/** 654 * cvmx_asx#_rld_bypass_setting 655 * 656 * ASX_RLD_BYPASS_SETTING 657 * 658 */ 659union cvmx_asxx_rld_bypass_setting { 660 uint64_t u64; 661 struct cvmx_asxx_rld_bypass_setting_s { 662#ifdef __BIG_ENDIAN_BITFIELD 663 uint64_t reserved_5_63 : 59; 664 uint64_t setting : 5; /**< The rld_dll setting bypass value */ 665#else 666 uint64_t setting : 5; 667 uint64_t reserved_5_63 : 59; 668#endif 669 } s; 670 struct cvmx_asxx_rld_bypass_setting_s cn38xx; 671 struct cvmx_asxx_rld_bypass_setting_s cn38xxp2; 672 struct cvmx_asxx_rld_bypass_setting_s cn58xx; 673 struct cvmx_asxx_rld_bypass_setting_s cn58xxp1; 674}; 675typedef union cvmx_asxx_rld_bypass_setting cvmx_asxx_rld_bypass_setting_t; 676 677/** 678 * cvmx_asx#_rld_comp 679 * 680 * ASX_RLD_COMP 681 * 682 */ 683union cvmx_asxx_rld_comp { 684 uint64_t u64; 685 struct cvmx_asxx_rld_comp_s { 686#ifdef __BIG_ENDIAN_BITFIELD 687 uint64_t reserved_9_63 : 55; 688 uint64_t pctl : 5; /**< PCTL Compensation Value 689 These bits reflect the computed compensation 690 values from the built-in compensation circuit. */ 691 uint64_t nctl : 4; /**< These bits reflect the computed compensation 692 values from the built-in compensation circuit. */ 693#else 694 uint64_t nctl : 4; 695 uint64_t pctl : 5; 696 uint64_t reserved_9_63 : 55; 697#endif 698 } s; 699 struct cvmx_asxx_rld_comp_cn38xx { 700#ifdef __BIG_ENDIAN_BITFIELD 701 uint64_t reserved_8_63 : 56; 702 uint64_t pctl : 4; /**< These bits reflect the computed compensation 703 values from the built-in compensation circuit. */ 704 uint64_t nctl : 4; /**< These bits reflect the computed compensation 705 values from the built-in compensation circuit. */ 706#else 707 uint64_t nctl : 4; 708 uint64_t pctl : 4; 709 uint64_t reserved_8_63 : 56; 710#endif 711 } cn38xx; 712 struct cvmx_asxx_rld_comp_cn38xx cn38xxp2; 713 struct cvmx_asxx_rld_comp_s cn58xx; 714 struct cvmx_asxx_rld_comp_s cn58xxp1; 715}; 716typedef union cvmx_asxx_rld_comp cvmx_asxx_rld_comp_t; 717 718/** 719 * cvmx_asx#_rld_data_drv 720 * 721 * ASX_RLD_DATA_DRV 722 * 723 */ 724union cvmx_asxx_rld_data_drv { 725 uint64_t u64; 726 struct cvmx_asxx_rld_data_drv_s { 727#ifdef __BIG_ENDIAN_BITFIELD 728 uint64_t reserved_8_63 : 56; 729 uint64_t pctl : 4; /**< These bits specify a driving strength (positive 730 integer) for the RLD I/Os when the built-in 731 compensation circuit is bypassed. */ 732 uint64_t nctl : 4; /**< These bits specify a driving strength (positive 733 integer) for the RLD I/Os when the built-in 734 compensation circuit is bypassed. */ 735#else 736 uint64_t nctl : 4; 737 uint64_t pctl : 4; 738 uint64_t reserved_8_63 : 56; 739#endif 740 } s; 741 struct cvmx_asxx_rld_data_drv_s cn38xx; 742 struct cvmx_asxx_rld_data_drv_s cn38xxp2; 743 struct cvmx_asxx_rld_data_drv_s cn58xx; 744 struct cvmx_asxx_rld_data_drv_s cn58xxp1; 745}; 746typedef union cvmx_asxx_rld_data_drv cvmx_asxx_rld_data_drv_t; 747 748/** 749 * cvmx_asx#_rld_fcram_mode 750 * 751 * ASX_RLD_FCRAM_MODE 752 * 753 */ 754union cvmx_asxx_rld_fcram_mode { 755 uint64_t u64; 756 struct cvmx_asxx_rld_fcram_mode_s { 757#ifdef __BIG_ENDIAN_BITFIELD 758 uint64_t reserved_1_63 : 63; 759 uint64_t mode : 1; /**< Memory Mode 760 - 0: RLDRAM 761 - 1: FCRAM */ 762#else 763 uint64_t mode : 1; 764 uint64_t reserved_1_63 : 63; 765#endif 766 } s; 767 struct cvmx_asxx_rld_fcram_mode_s cn38xx; 768 struct cvmx_asxx_rld_fcram_mode_s cn38xxp2; 769}; 770typedef union cvmx_asxx_rld_fcram_mode cvmx_asxx_rld_fcram_mode_t; 771 772/** 773 * cvmx_asx#_rld_nctl_strong 774 * 775 * ASX_RLD_NCTL_STRONG 776 * 777 */ 778union cvmx_asxx_rld_nctl_strong { 779 uint64_t u64; 780 struct cvmx_asxx_rld_nctl_strong_s { 781#ifdef __BIG_ENDIAN_BITFIELD 782 uint64_t reserved_5_63 : 59; 783 uint64_t nctl : 5; /**< Duke's drive control */ 784#else 785 uint64_t nctl : 5; 786 uint64_t reserved_5_63 : 59; 787#endif 788 } s; 789 struct cvmx_asxx_rld_nctl_strong_s cn38xx; 790 struct cvmx_asxx_rld_nctl_strong_s cn38xxp2; 791 struct cvmx_asxx_rld_nctl_strong_s cn58xx; 792 struct cvmx_asxx_rld_nctl_strong_s cn58xxp1; 793}; 794typedef union cvmx_asxx_rld_nctl_strong cvmx_asxx_rld_nctl_strong_t; 795 796/** 797 * cvmx_asx#_rld_nctl_weak 798 * 799 * ASX_RLD_NCTL_WEAK 800 * 801 */ 802union cvmx_asxx_rld_nctl_weak { 803 uint64_t u64; 804 struct cvmx_asxx_rld_nctl_weak_s { 805#ifdef __BIG_ENDIAN_BITFIELD 806 uint64_t reserved_5_63 : 59; 807 uint64_t nctl : 5; /**< UNUSED (not needed for CN58XX) */ 808#else 809 uint64_t nctl : 5; 810 uint64_t reserved_5_63 : 59; 811#endif 812 } s; 813 struct cvmx_asxx_rld_nctl_weak_s cn38xx; 814 struct cvmx_asxx_rld_nctl_weak_s cn38xxp2; 815 struct cvmx_asxx_rld_nctl_weak_s cn58xx; 816 struct cvmx_asxx_rld_nctl_weak_s cn58xxp1; 817}; 818typedef union cvmx_asxx_rld_nctl_weak cvmx_asxx_rld_nctl_weak_t; 819 820/** 821 * cvmx_asx#_rld_pctl_strong 822 * 823 * ASX_RLD_PCTL_STRONG 824 * 825 */ 826union cvmx_asxx_rld_pctl_strong { 827 uint64_t u64; 828 struct cvmx_asxx_rld_pctl_strong_s { 829#ifdef __BIG_ENDIAN_BITFIELD 830 uint64_t reserved_5_63 : 59; 831 uint64_t pctl : 5; /**< Duke's drive control */ 832#else 833 uint64_t pctl : 5; 834 uint64_t reserved_5_63 : 59; 835#endif 836 } s; 837 struct cvmx_asxx_rld_pctl_strong_s cn38xx; 838 struct cvmx_asxx_rld_pctl_strong_s cn38xxp2; 839 struct cvmx_asxx_rld_pctl_strong_s cn58xx; 840 struct cvmx_asxx_rld_pctl_strong_s cn58xxp1; 841}; 842typedef union cvmx_asxx_rld_pctl_strong cvmx_asxx_rld_pctl_strong_t; 843 844/** 845 * cvmx_asx#_rld_pctl_weak 846 * 847 * ASX_RLD_PCTL_WEAK 848 * 849 */ 850union cvmx_asxx_rld_pctl_weak { 851 uint64_t u64; 852 struct cvmx_asxx_rld_pctl_weak_s { 853#ifdef __BIG_ENDIAN_BITFIELD 854 uint64_t reserved_5_63 : 59; 855 uint64_t pctl : 5; /**< UNUSED (not needed for CN58XX) */ 856#else 857 uint64_t pctl : 5; 858 uint64_t reserved_5_63 : 59; 859#endif 860 } s; 861 struct cvmx_asxx_rld_pctl_weak_s cn38xx; 862 struct cvmx_asxx_rld_pctl_weak_s cn38xxp2; 863 struct cvmx_asxx_rld_pctl_weak_s cn58xx; 864 struct cvmx_asxx_rld_pctl_weak_s cn58xxp1; 865}; 866typedef union cvmx_asxx_rld_pctl_weak cvmx_asxx_rld_pctl_weak_t; 867 868/** 869 * cvmx_asx#_rld_setting 870 * 871 * ASX_RLD_SETTING 872 * 873 */ 874union cvmx_asxx_rld_setting { 875 uint64_t u64; 876 struct cvmx_asxx_rld_setting_s { 877#ifdef __BIG_ENDIAN_BITFIELD 878 uint64_t reserved_13_63 : 51; 879 uint64_t dfaset : 5; /**< RLD ClkGen DLL Setting(debug) */ 880 uint64_t dfalag : 1; /**< RLD ClkGen DLL Lag Error(debug) */ 881 uint64_t dfalead : 1; /**< RLD ClkGen DLL Lead Error(debug) */ 882 uint64_t dfalock : 1; /**< RLD ClkGen DLL Lock acquisition(debug) */ 883 uint64_t setting : 5; /**< RLDCK90 DLL Setting(debug) */ 884#else 885 uint64_t setting : 5; 886 uint64_t dfalock : 1; 887 uint64_t dfalead : 1; 888 uint64_t dfalag : 1; 889 uint64_t dfaset : 5; 890 uint64_t reserved_13_63 : 51; 891#endif 892 } s; 893 struct cvmx_asxx_rld_setting_cn38xx { 894#ifdef __BIG_ENDIAN_BITFIELD 895 uint64_t reserved_5_63 : 59; 896 uint64_t setting : 5; /**< This is the read-only true rld dll_setting. */ 897#else 898 uint64_t setting : 5; 899 uint64_t reserved_5_63 : 59; 900#endif 901 } cn38xx; 902 struct cvmx_asxx_rld_setting_cn38xx cn38xxp2; 903 struct cvmx_asxx_rld_setting_s cn58xx; 904 struct cvmx_asxx_rld_setting_s cn58xxp1; 905}; 906typedef union cvmx_asxx_rld_setting cvmx_asxx_rld_setting_t; 907 908/** 909 * cvmx_asx#_rx_clk_set# 910 * 911 * ASX_RX_CLK_SET = RGMII Clock delay setting 912 * 913 * 914 * Notes: 915 * Setting to place on the open-loop RXC (RGMII receive clk) 916 * delay line, which can delay the recieved clock. This 917 * can be used if the board and/or transmitting device 918 * has not otherwise delayed the clock. 919 * 920 * A value of SETTING=0 disables the delay line. The delay 921 * line should be disabled unless the transmitter or board 922 * does not delay the clock. 923 * 924 * Note that this delay line provides only a coarse control 925 * over the delay. Generally, it can only reliably provide 926 * a delay in the range 1.25-2.5ns, which may not be adequate 927 * for some system applications. 928 * 929 * The open loop delay line selects 930 * from among a series of tap positions. Each incremental 931 * tap position adds a delay of 50ps to 135ps per tap, depending 932 * on the chip, its temperature, and the voltage. 933 * To achieve from 1.25-2.5ns of delay on the recieved 934 * clock, a fixed value of SETTING=24 may work. 935 * For more precision, we recommend the following settings 936 * based on the chip voltage: 937 * 938 * VDD SETTING 939 * ----------------------------- 940 * 1.0 18 941 * 1.05 19 942 * 1.1 21 943 * 1.15 22 944 * 1.2 23 945 * 1.25 24 946 * 1.3 25 947 */ 948union cvmx_asxx_rx_clk_setx { 949 uint64_t u64; 950 struct cvmx_asxx_rx_clk_setx_s { 951#ifdef __BIG_ENDIAN_BITFIELD 952 uint64_t reserved_5_63 : 59; 953 uint64_t setting : 5; /**< Setting to place on the open-loop RXC delay line */ 954#else 955 uint64_t setting : 5; 956 uint64_t reserved_5_63 : 59; 957#endif 958 } s; 959 struct cvmx_asxx_rx_clk_setx_s cn30xx; 960 struct cvmx_asxx_rx_clk_setx_s cn31xx; 961 struct cvmx_asxx_rx_clk_setx_s cn38xx; 962 struct cvmx_asxx_rx_clk_setx_s cn38xxp2; 963 struct cvmx_asxx_rx_clk_setx_s cn50xx; 964 struct cvmx_asxx_rx_clk_setx_s cn58xx; 965 struct cvmx_asxx_rx_clk_setx_s cn58xxp1; 966}; 967typedef union cvmx_asxx_rx_clk_setx cvmx_asxx_rx_clk_setx_t; 968 969/** 970 * cvmx_asx#_rx_prt_en 971 * 972 * ASX_RX_PRT_EN = RGMII Port Enable 973 * 974 */ 975union cvmx_asxx_rx_prt_en { 976 uint64_t u64; 977 struct cvmx_asxx_rx_prt_en_s { 978#ifdef __BIG_ENDIAN_BITFIELD 979 uint64_t reserved_4_63 : 60; 980 uint64_t prt_en : 4; /**< Port enable. Must be set for Octane to receive 981 RMGII traffic. When this bit clear on a given 982 port, then the all RGMII cycles will appear as 983 inter-frame cycles. */ 984#else 985 uint64_t prt_en : 4; 986 uint64_t reserved_4_63 : 60; 987#endif 988 } s; 989 struct cvmx_asxx_rx_prt_en_cn30xx { 990#ifdef __BIG_ENDIAN_BITFIELD 991 uint64_t reserved_3_63 : 61; 992 uint64_t prt_en : 3; /**< Port enable. Must be set for Octane to receive 993 RMGII traffic. When this bit clear on a given 994 port, then the all RGMII cycles will appear as 995 inter-frame cycles. */ 996#else 997 uint64_t prt_en : 3; 998 uint64_t reserved_3_63 : 61; 999#endif 1000 } cn30xx; 1001 struct cvmx_asxx_rx_prt_en_cn30xx cn31xx; 1002 struct cvmx_asxx_rx_prt_en_s cn38xx; 1003 struct cvmx_asxx_rx_prt_en_s cn38xxp2; 1004 struct cvmx_asxx_rx_prt_en_cn30xx cn50xx; 1005 struct cvmx_asxx_rx_prt_en_s cn58xx; 1006 struct cvmx_asxx_rx_prt_en_s cn58xxp1; 1007}; 1008typedef union cvmx_asxx_rx_prt_en cvmx_asxx_rx_prt_en_t; 1009 1010/** 1011 * cvmx_asx#_rx_wol 1012 * 1013 * ASX_RX_WOL = RGMII RX Wake on LAN status register 1014 * 1015 */ 1016union cvmx_asxx_rx_wol { 1017 uint64_t u64; 1018 struct cvmx_asxx_rx_wol_s { 1019#ifdef __BIG_ENDIAN_BITFIELD 1020 uint64_t reserved_2_63 : 62; 1021 uint64_t status : 1; /**< Copy of PMCSR[15] - PME_status */ 1022 uint64_t enable : 1; /**< Copy of PMCSR[8] - PME_enable */ 1023#else 1024 uint64_t enable : 1; 1025 uint64_t status : 1; 1026 uint64_t reserved_2_63 : 62; 1027#endif 1028 } s; 1029 struct cvmx_asxx_rx_wol_s cn38xx; 1030 struct cvmx_asxx_rx_wol_s cn38xxp2; 1031}; 1032typedef union cvmx_asxx_rx_wol cvmx_asxx_rx_wol_t; 1033 1034/** 1035 * cvmx_asx#_rx_wol_msk 1036 * 1037 * ASX_RX_WOL_MSK = RGMII RX Wake on LAN byte mask 1038 * 1039 */ 1040union cvmx_asxx_rx_wol_msk { 1041 uint64_t u64; 1042 struct cvmx_asxx_rx_wol_msk_s { 1043#ifdef __BIG_ENDIAN_BITFIELD 1044 uint64_t msk : 64; /**< Bytes to include in the CRC signature */ 1045#else 1046 uint64_t msk : 64; 1047#endif 1048 } s; 1049 struct cvmx_asxx_rx_wol_msk_s cn38xx; 1050 struct cvmx_asxx_rx_wol_msk_s cn38xxp2; 1051}; 1052typedef union cvmx_asxx_rx_wol_msk cvmx_asxx_rx_wol_msk_t; 1053 1054/** 1055 * cvmx_asx#_rx_wol_powok 1056 * 1057 * ASX_RX_WOL_POWOK = RGMII RX Wake on LAN Power OK 1058 * 1059 */ 1060union cvmx_asxx_rx_wol_powok { 1061 uint64_t u64; 1062 struct cvmx_asxx_rx_wol_powok_s { 1063#ifdef __BIG_ENDIAN_BITFIELD 1064 uint64_t reserved_1_63 : 63; 1065 uint64_t powerok : 1; /**< Power OK */ 1066#else 1067 uint64_t powerok : 1; 1068 uint64_t reserved_1_63 : 63; 1069#endif 1070 } s; 1071 struct cvmx_asxx_rx_wol_powok_s cn38xx; 1072 struct cvmx_asxx_rx_wol_powok_s cn38xxp2; 1073}; 1074typedef union cvmx_asxx_rx_wol_powok cvmx_asxx_rx_wol_powok_t; 1075 1076/** 1077 * cvmx_asx#_rx_wol_sig 1078 * 1079 * ASX_RX_WOL_SIG = RGMII RX Wake on LAN CRC signature 1080 * 1081 */ 1082union cvmx_asxx_rx_wol_sig { 1083 uint64_t u64; 1084 struct cvmx_asxx_rx_wol_sig_s { 1085#ifdef __BIG_ENDIAN_BITFIELD 1086 uint64_t reserved_32_63 : 32; 1087 uint64_t sig : 32; /**< CRC signature */ 1088#else 1089 uint64_t sig : 32; 1090 uint64_t reserved_32_63 : 32; 1091#endif 1092 } s; 1093 struct cvmx_asxx_rx_wol_sig_s cn38xx; 1094 struct cvmx_asxx_rx_wol_sig_s cn38xxp2; 1095}; 1096typedef union cvmx_asxx_rx_wol_sig cvmx_asxx_rx_wol_sig_t; 1097 1098/** 1099 * cvmx_asx#_tx_clk_set# 1100 * 1101 * ASX_TX_CLK_SET = RGMII Clock delay setting 1102 * 1103 * 1104 * Notes: 1105 * Setting to place on the open-loop TXC (RGMII transmit clk) 1106 * delay line, which can delay the transmited clock. This 1107 * can be used if the board and/or transmitting device 1108 * has not otherwise delayed the clock. 1109 * 1110 * A value of SETTING=0 disables the delay line. The delay 1111 * line should be disabled unless the transmitter or board 1112 * does not delay the clock. 1113 * 1114 * Note that this delay line provides only a coarse control 1115 * over the delay. Generally, it can only reliably provide 1116 * a delay in the range 1.25-2.5ns, which may not be adequate 1117 * for some system applications. 1118 * 1119 * The open loop delay line selects 1120 * from among a series of tap positions. Each incremental 1121 * tap position adds a delay of 50ps to 135ps per tap, depending 1122 * on the chip, its temperature, and the voltage. 1123 * To achieve from 1.25-2.5ns of delay on the recieved 1124 * clock, a fixed value of SETTING=24 may work. 1125 * For more precision, we recommend the following settings 1126 * based on the chip voltage: 1127 * 1128 * VDD SETTING 1129 * ----------------------------- 1130 * 1.0 18 1131 * 1.05 19 1132 * 1.1 21 1133 * 1.15 22 1134 * 1.2 23 1135 * 1.25 24 1136 * 1.3 25 1137 */ 1138union cvmx_asxx_tx_clk_setx { 1139 uint64_t u64; 1140 struct cvmx_asxx_tx_clk_setx_s { 1141#ifdef __BIG_ENDIAN_BITFIELD 1142 uint64_t reserved_5_63 : 59; 1143 uint64_t setting : 5; /**< Setting to place on the open-loop TXC delay line */ 1144#else 1145 uint64_t setting : 5; 1146 uint64_t reserved_5_63 : 59; 1147#endif 1148 } s; 1149 struct cvmx_asxx_tx_clk_setx_s cn30xx; 1150 struct cvmx_asxx_tx_clk_setx_s cn31xx; 1151 struct cvmx_asxx_tx_clk_setx_s cn38xx; 1152 struct cvmx_asxx_tx_clk_setx_s cn38xxp2; 1153 struct cvmx_asxx_tx_clk_setx_s cn50xx; 1154 struct cvmx_asxx_tx_clk_setx_s cn58xx; 1155 struct cvmx_asxx_tx_clk_setx_s cn58xxp1; 1156}; 1157typedef union cvmx_asxx_tx_clk_setx cvmx_asxx_tx_clk_setx_t; 1158 1159/** 1160 * cvmx_asx#_tx_comp_byp 1161 * 1162 * ASX_TX_COMP_BYP = RGMII Clock delay setting 1163 * 1164 */ 1165union cvmx_asxx_tx_comp_byp { 1166 uint64_t u64; 1167 struct cvmx_asxx_tx_comp_byp_s { 1168#ifdef __BIG_ENDIAN_BITFIELD 1169 uint64_t reserved_0_63 : 64; 1170#else 1171 uint64_t reserved_0_63 : 64; 1172#endif 1173 } s; 1174 struct cvmx_asxx_tx_comp_byp_cn30xx { 1175#ifdef __BIG_ENDIAN_BITFIELD 1176 uint64_t reserved_9_63 : 55; 1177 uint64_t bypass : 1; /**< Compensation bypass */ 1178 uint64_t pctl : 4; /**< PCTL Compensation Value (see Duke) */ 1179 uint64_t nctl : 4; /**< NCTL Compensation Value (see Duke) */ 1180#else 1181 uint64_t nctl : 4; 1182 uint64_t pctl : 4; 1183 uint64_t bypass : 1; 1184 uint64_t reserved_9_63 : 55; 1185#endif 1186 } cn30xx; 1187 struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx; 1188 struct cvmx_asxx_tx_comp_byp_cn38xx { 1189#ifdef __BIG_ENDIAN_BITFIELD 1190 uint64_t reserved_8_63 : 56; 1191 uint64_t pctl : 4; /**< PCTL Compensation Value (see Duke) */ 1192 uint64_t nctl : 4; /**< NCTL Compensation Value (see Duke) */ 1193#else 1194 uint64_t nctl : 4; 1195 uint64_t pctl : 4; 1196 uint64_t reserved_8_63 : 56; 1197#endif 1198 } cn38xx; 1199 struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2; 1200 struct cvmx_asxx_tx_comp_byp_cn50xx { 1201#ifdef __BIG_ENDIAN_BITFIELD 1202 uint64_t reserved_17_63 : 47; 1203 uint64_t bypass : 1; /**< Compensation bypass */ 1204 uint64_t reserved_13_15 : 3; 1205 uint64_t pctl : 5; /**< PCTL Compensation Value (see Duke) */ 1206 uint64_t reserved_5_7 : 3; 1207 uint64_t nctl : 5; /**< NCTL Compensation Value (see Duke) */ 1208#else 1209 uint64_t nctl : 5; 1210 uint64_t reserved_5_7 : 3; 1211 uint64_t pctl : 5; 1212 uint64_t reserved_13_15 : 3; 1213 uint64_t bypass : 1; 1214 uint64_t reserved_17_63 : 47; 1215#endif 1216 } cn50xx; 1217 struct cvmx_asxx_tx_comp_byp_cn58xx { 1218#ifdef __BIG_ENDIAN_BITFIELD 1219 uint64_t reserved_13_63 : 51; 1220 uint64_t pctl : 5; /**< PCTL Compensation Value (see Duke) */ 1221 uint64_t reserved_5_7 : 3; 1222 uint64_t nctl : 5; /**< NCTL Compensation Value (see Duke) */ 1223#else 1224 uint64_t nctl : 5; 1225 uint64_t reserved_5_7 : 3; 1226 uint64_t pctl : 5; 1227 uint64_t reserved_13_63 : 51; 1228#endif 1229 } cn58xx; 1230 struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1; 1231}; 1232typedef union cvmx_asxx_tx_comp_byp cvmx_asxx_tx_comp_byp_t; 1233 1234/** 1235 * cvmx_asx#_tx_hi_water# 1236 * 1237 * ASX_TX_HI_WATER = RGMII TX FIFO Hi WaterMark 1238 * 1239 */ 1240union cvmx_asxx_tx_hi_waterx { 1241 uint64_t u64; 1242 struct cvmx_asxx_tx_hi_waterx_s { 1243#ifdef __BIG_ENDIAN_BITFIELD 1244 uint64_t reserved_4_63 : 60; 1245 uint64_t mark : 4; /**< TX FIFO HiWatermark to stall GMX 1246 Value of 0 maps to 16 1247 Reset value changed from 10 in pass1 1248 Pass1 settings (assuming 125 tclk) 1249 - 325-375: 12 1250 - 375-437: 11 1251 - 437-550: 10 1252 - 550-687: 9 */ 1253#else 1254 uint64_t mark : 4; 1255 uint64_t reserved_4_63 : 60; 1256#endif 1257 } s; 1258 struct cvmx_asxx_tx_hi_waterx_cn30xx { 1259#ifdef __BIG_ENDIAN_BITFIELD 1260 uint64_t reserved_3_63 : 61; 1261 uint64_t mark : 3; /**< TX FIFO HiWatermark to stall GMX 1262 Value 0 maps to 8. */ 1263#else 1264 uint64_t mark : 3; 1265 uint64_t reserved_3_63 : 61; 1266#endif 1267 } cn30xx; 1268 struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx; 1269 struct cvmx_asxx_tx_hi_waterx_s cn38xx; 1270 struct cvmx_asxx_tx_hi_waterx_s cn38xxp2; 1271 struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx; 1272 struct cvmx_asxx_tx_hi_waterx_s cn58xx; 1273 struct cvmx_asxx_tx_hi_waterx_s cn58xxp1; 1274}; 1275typedef union cvmx_asxx_tx_hi_waterx cvmx_asxx_tx_hi_waterx_t; 1276 1277/** 1278 * cvmx_asx#_tx_prt_en 1279 * 1280 * ASX_TX_PRT_EN = RGMII Port Enable 1281 * 1282 */ 1283union cvmx_asxx_tx_prt_en { 1284 uint64_t u64; 1285 struct cvmx_asxx_tx_prt_en_s { 1286#ifdef __BIG_ENDIAN_BITFIELD 1287 uint64_t reserved_4_63 : 60; 1288 uint64_t prt_en : 4; /**< Port enable. Must be set for Octane to send 1289 RMGII traffic. When this bit clear on a given 1290 port, then all RGMII cycles will appear as 1291 inter-frame cycles. */ 1292#else 1293 uint64_t prt_en : 4; 1294 uint64_t reserved_4_63 : 60; 1295#endif 1296 } s; 1297 struct cvmx_asxx_tx_prt_en_cn30xx { 1298#ifdef __BIG_ENDIAN_BITFIELD 1299 uint64_t reserved_3_63 : 61; 1300 uint64_t prt_en : 3; /**< Port enable. Must be set for Octane to send 1301 RMGII traffic. When this bit clear on a given 1302 port, then all RGMII cycles will appear as 1303 inter-frame cycles. */ 1304#else 1305 uint64_t prt_en : 3; 1306 uint64_t reserved_3_63 : 61; 1307#endif 1308 } cn30xx; 1309 struct cvmx_asxx_tx_prt_en_cn30xx cn31xx; 1310 struct cvmx_asxx_tx_prt_en_s cn38xx; 1311 struct cvmx_asxx_tx_prt_en_s cn38xxp2; 1312 struct cvmx_asxx_tx_prt_en_cn30xx cn50xx; 1313 struct cvmx_asxx_tx_prt_en_s cn58xx; 1314 struct cvmx_asxx_tx_prt_en_s cn58xxp1; 1315}; 1316typedef union cvmx_asxx_tx_prt_en cvmx_asxx_tx_prt_en_t; 1317 1318#endif 1319