Searched refs:__SYSREG (Results 1 - 25 of 28) sorted by relevance

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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mn10300/unit-asb2303/include/unit/
H A Dserial.h60 #define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 4, u8)
61 #define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8)
62 #define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 4, u8)
63 #define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 4, u8)
64 #define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 4, u8)
65 #define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 4, u8)
66 #define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8)
67 #define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8)
68 #define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8)
69 #define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRES
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H A Dleds.h19 #define ASB2303_GPIO0DEF __SYSREG(0xDB000000, u32)
20 #define ASB2303_7SEGLEDS __SYSREG(0xDB000008, u32)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mn10300/unit-asb2303/include/unit/
H A Dserial.h60 #define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 4, u8)
61 #define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8)
62 #define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 4, u8)
63 #define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 4, u8)
64 #define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 4, u8)
65 #define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 4, u8)
66 #define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8)
67 #define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8)
68 #define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8)
69 #define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRES
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H A Dleds.h19 #define ASB2303_GPIO0DEF __SYSREG(0xDB000000, u32)
20 #define ASB2303_7SEGLEDS __SYSREG(0xDB000008, u32)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mn10300/include/asm/
H A Drtc-regs.h18 #define RTSCR __SYSREG(0xd8600000, u8) /* RTC seconds count reg */
19 #define RTSAR __SYSREG(0xd8600001, u8) /* RTC seconds alarm reg */
20 #define RTMCR __SYSREG(0xd8600002, u8) /* RTC minutes count reg */
21 #define RTMAR __SYSREG(0xd8600003, u8) /* RTC minutes alarm reg */
22 #define RTHCR __SYSREG(0xd8600004, u8) /* RTC hours count reg */
23 #define RTHAR __SYSREG(0xd8600005, u8) /* RTC hours alarm reg */
24 #define RTDWCR __SYSREG(0xd8600006, u8) /* RTC day of the week count reg */
25 #define RTDMCR __SYSREG(0xd8600007, u8) /* RTC days count reg */
26 #define RTMTCR __SYSREG(0xd8600008, u8) /* RTC months count reg */
27 #define RTYCR __SYSREG(
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H A Dcache.h32 __SYSREG(0xc8400000 + (WAY) * L1_CACHE_WAYDISP + \
36 __SYSREG(0xc8400000 + 0 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
38 __SYSREG(0xc8400000 + 1 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
40 __SYSREG(0xc8400000 + 2 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
42 __SYSREG(0xc8400000 + 3 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
46 __SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32)
48 __SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32)
52 __SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32)
54 __SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32)
H A Dtimer-regs.h21 #define TMPSCNT __SYSREG(0xd4003071, u8) /* timer prescaler control */
26 #define TM0MD __SYSREG(0xd4003000, u8) /* timer 0 mode register */
38 #define TM1MD __SYSREG(0xd4003001, u8) /* timer 1 mode register */
50 #define TM2MD __SYSREG(0xd4003002, u8) /* timer 2 mode register */
62 #define TM3MD __SYSREG(0xd4003003, u8) /* timer 3 mode register */
75 #define TM01MD __SYSREG(0xd4003000, u16) /* timer 0:1 mode register */
77 #define TM0BR __SYSREG(0xd4003010, u8) /* timer 0 base register */
78 #define TM1BR __SYSREG(0xd4003011, u8) /* timer 1 base register */
79 #define TM2BR __SYSREG(0xd4003012, u8) /* timer 2 base register */
80 #define TM3BR __SYSREG(
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H A Dserial-regs.h21 #define SC0CTR __SYSREG(0xd4002000, u16) /* control reg */
61 #define SC0ICR __SYSREG(0xd4002004, u8) /* interrupt control reg */
68 #define SC0TXB __SYSREG(0xd4002008, u8) /* transmit buffer reg */
69 #define SC0RXB __SYSREG(0xd4002009, u8) /* receive buffer reg */
71 #define SC0STR __SYSREG(0xd400200c, u16) /* status reg */
89 #define SC1CTR __SYSREG(0xd4002010, u16) /* serial port 1 control */
90 #define SC1ICR __SYSREG(0xd4002014, u8) /* interrupt control reg */
91 #define SC1TXB __SYSREG(0xd4002018, u8) /* transmit buffer reg */
92 #define SC1RXB __SYSREG(0xd4002019, u8) /* receive buffer reg */
93 #define SC1STR __SYSREG(
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H A Dpio-regs.h20 #define P0MD __SYSREG(0xdb000000, u16) /* mode reg */
57 #define P0IN __SYSREG(0xdb000004, u8) /* in reg */
58 #define P0OUT __SYSREG(0xdb000008, u8) /* out reg */
60 #define P0TMIO __SYSREG(0xdb00000c, u8) /* TM pin I/O control reg */
79 #define P1MD __SYSREG(0xdb000100, u16) /* mode reg */
106 #define P1IN __SYSREG(0xdb000104, u8) /* in reg */
107 #define P1OUT __SYSREG(0xdb000108, u8) /* out reg */
108 #define P1TMIO __SYSREG(0xdb00010c, u8) /* TM pin I/O control reg */
121 #define P2MD __SYSREG(0xdb000200, u16) /* mode reg */
142 #define P2IN __SYSREG(
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H A Dcpu-regs.h32 #define __SYSREG(ADDR, TYPE) (*(volatile TYPE *)(ADDR)) macro
35 #define __SYSREG(ADDR, TYPE) ADDR
87 #define CPUP __SYSREG(0xc0000020, u16) /* CPU pipeline register */
94 #define CPUM __SYSREG(0xc0000040, u16) /* CPU mode register */
119 #define DCR __SYSREG(0xc0000030, u16) /* Debug control register */
122 #define IVAR0 __SYSREG(0xc0000000, u16) /* interrupt vector 0 */
123 #define IVAR1 __SYSREG(0xc0000004, u16) /* interrupt vector 1 */
124 #define IVAR2 __SYSREG(0xc0000008, u16) /* interrupt vector 2 */
125 #define IVAR3 __SYSREG(0xc000000c, u16) /* interrupt vector 3 */
126 #define IVAR4 __SYSREG(
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H A Dbusctl-regs.h20 #define BCCR __SYSREG(0xc0002000, u32) /* bus controller control reg */
50 #define BCBERR __SYSREG(0xc0002010, u32) /* bus error source reg */
76 #define SBBASE(X) __SYSREG(0xd8c00100 + (X) * 0x10, u32) /* SBC base addr regs */
81 #define SBCNTRL0(X) __SYSREG(0xd8c00200 + (X) * 0x10, u32) /* SBC bank ctrl0 regs */
89 #define SBCNTRL1(X) __SYSREG(0xd8c00204 + (X) * 0x10, u32) /* SBC bank ctrl1 regs */
97 #define SBCNTRL2(X) __SYSREG(0xd8c00208 + (X) * 0x10, u32) /* SBC bank ctrl2 regs */
119 #define SDBASE(X) __SYSREG(0xda000008 + (X) * 0x4, u32) /* MBC base addr regs */
125 #define SDRAMBUS __SYSREG(0xda000000, u32) /* bus mode control reg */
144 #define SDREFCNT __SYSREG(0xda000004, u32) /* refresh period reg */
147 #define SDSHDW __SYSREG(
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H A Ddmactl-regs.h19 #define DMxCTR(N) __SYSREG(0xd2000000 + ((N) * 0x100), u32) /* control reg */
66 #define DMxSRC(N) __SYSREG(0xd2000004 + ((N) * 0x100), u32) /* control reg */
68 #define DMxDST(N) __SYSREG(0xd2000008 + ((N) * 0x100), u32) /* src addr reg */
70 #define DMxSIZ(N) __SYSREG(0xd200000c + ((N) * 0x100), u32) /* dest addr reg */
73 #define DMxCYC(N) __SYSREG(0xd2000010 + ((N) * 0x100), u32) /* intermittent
H A Dreset-regs.h29 #define WDCTR __SYSREG(0xc0001002, u8) /* watchdog timer control reg */
39 #define RSTCTR __SYSREG(0xc0001004, u8) /* reset control reg */
H A Dintctl-regs.h19 #define GxICR(X) __SYSREG(0xd4000000 + (X) * 4, u16) /* group irq ctrl regs */
21 #define IAGR __SYSREG(0xd4000100, u16) /* intr acceptance group reg */
26 #define EXTMD __SYSREG(0xd4000200, u16) /* external pin intr spec reg */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mn10300/include/asm/
H A Drtc-regs.h18 #define RTSCR __SYSREG(0xd8600000, u8) /* RTC seconds count reg */
19 #define RTSAR __SYSREG(0xd8600001, u8) /* RTC seconds alarm reg */
20 #define RTMCR __SYSREG(0xd8600002, u8) /* RTC minutes count reg */
21 #define RTMAR __SYSREG(0xd8600003, u8) /* RTC minutes alarm reg */
22 #define RTHCR __SYSREG(0xd8600004, u8) /* RTC hours count reg */
23 #define RTHAR __SYSREG(0xd8600005, u8) /* RTC hours alarm reg */
24 #define RTDWCR __SYSREG(0xd8600006, u8) /* RTC day of the week count reg */
25 #define RTDMCR __SYSREG(0xd8600007, u8) /* RTC days count reg */
26 #define RTMTCR __SYSREG(0xd8600008, u8) /* RTC months count reg */
27 #define RTYCR __SYSREG(
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H A Dcache.h32 __SYSREG(0xc8400000 + (WAY) * L1_CACHE_WAYDISP + \
36 __SYSREG(0xc8400000 + 0 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
38 __SYSREG(0xc8400000 + 1 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
40 __SYSREG(0xc8400000 + 2 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
42 __SYSREG(0xc8400000 + 3 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
46 __SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32)
48 __SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32)
52 __SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32)
54 __SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32)
H A Dtimer-regs.h21 #define TMPSCNT __SYSREG(0xd4003071, u8) /* timer prescaler control */
26 #define TM0MD __SYSREG(0xd4003000, u8) /* timer 0 mode register */
38 #define TM1MD __SYSREG(0xd4003001, u8) /* timer 1 mode register */
50 #define TM2MD __SYSREG(0xd4003002, u8) /* timer 2 mode register */
62 #define TM3MD __SYSREG(0xd4003003, u8) /* timer 3 mode register */
75 #define TM01MD __SYSREG(0xd4003000, u16) /* timer 0:1 mode register */
77 #define TM0BR __SYSREG(0xd4003010, u8) /* timer 0 base register */
78 #define TM1BR __SYSREG(0xd4003011, u8) /* timer 1 base register */
79 #define TM2BR __SYSREG(0xd4003012, u8) /* timer 2 base register */
80 #define TM3BR __SYSREG(
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H A Dserial-regs.h21 #define SC0CTR __SYSREG(0xd4002000, u16) /* control reg */
61 #define SC0ICR __SYSREG(0xd4002004, u8) /* interrupt control reg */
68 #define SC0TXB __SYSREG(0xd4002008, u8) /* transmit buffer reg */
69 #define SC0RXB __SYSREG(0xd4002009, u8) /* receive buffer reg */
71 #define SC0STR __SYSREG(0xd400200c, u16) /* status reg */
89 #define SC1CTR __SYSREG(0xd4002010, u16) /* serial port 1 control */
90 #define SC1ICR __SYSREG(0xd4002014, u8) /* interrupt control reg */
91 #define SC1TXB __SYSREG(0xd4002018, u8) /* transmit buffer reg */
92 #define SC1RXB __SYSREG(0xd4002019, u8) /* receive buffer reg */
93 #define SC1STR __SYSREG(
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H A Dpio-regs.h20 #define P0MD __SYSREG(0xdb000000, u16) /* mode reg */
57 #define P0IN __SYSREG(0xdb000004, u8) /* in reg */
58 #define P0OUT __SYSREG(0xdb000008, u8) /* out reg */
60 #define P0TMIO __SYSREG(0xdb00000c, u8) /* TM pin I/O control reg */
79 #define P1MD __SYSREG(0xdb000100, u16) /* mode reg */
106 #define P1IN __SYSREG(0xdb000104, u8) /* in reg */
107 #define P1OUT __SYSREG(0xdb000108, u8) /* out reg */
108 #define P1TMIO __SYSREG(0xdb00010c, u8) /* TM pin I/O control reg */
121 #define P2MD __SYSREG(0xdb000200, u16) /* mode reg */
142 #define P2IN __SYSREG(
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H A Dcpu-regs.h32 #define __SYSREG(ADDR, TYPE) (*(volatile TYPE *)(ADDR)) macro
35 #define __SYSREG(ADDR, TYPE) ADDR
87 #define CPUP __SYSREG(0xc0000020, u16) /* CPU pipeline register */
94 #define CPUM __SYSREG(0xc0000040, u16) /* CPU mode register */
119 #define DCR __SYSREG(0xc0000030, u16) /* Debug control register */
122 #define IVAR0 __SYSREG(0xc0000000, u16) /* interrupt vector 0 */
123 #define IVAR1 __SYSREG(0xc0000004, u16) /* interrupt vector 1 */
124 #define IVAR2 __SYSREG(0xc0000008, u16) /* interrupt vector 2 */
125 #define IVAR3 __SYSREG(0xc000000c, u16) /* interrupt vector 3 */
126 #define IVAR4 __SYSREG(
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H A Dbusctl-regs.h20 #define BCCR __SYSREG(0xc0002000, u32) /* bus controller control reg */
50 #define BCBERR __SYSREG(0xc0002010, u32) /* bus error source reg */
76 #define SBBASE(X) __SYSREG(0xd8c00100 + (X) * 0x10, u32) /* SBC base addr regs */
81 #define SBCNTRL0(X) __SYSREG(0xd8c00200 + (X) * 0x10, u32) /* SBC bank ctrl0 regs */
89 #define SBCNTRL1(X) __SYSREG(0xd8c00204 + (X) * 0x10, u32) /* SBC bank ctrl1 regs */
97 #define SBCNTRL2(X) __SYSREG(0xd8c00208 + (X) * 0x10, u32) /* SBC bank ctrl2 regs */
119 #define SDBASE(X) __SYSREG(0xda000008 + (X) * 0x4, u32) /* MBC base addr regs */
125 #define SDRAMBUS __SYSREG(0xda000000, u32) /* bus mode control reg */
144 #define SDREFCNT __SYSREG(0xda000004, u32) /* refresh period reg */
147 #define SDSHDW __SYSREG(
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H A Ddmactl-regs.h19 #define DMxCTR(N) __SYSREG(0xd2000000 + ((N) * 0x100), u32) /* control reg */
66 #define DMxSRC(N) __SYSREG(0xd2000004 + ((N) * 0x100), u32) /* control reg */
68 #define DMxDST(N) __SYSREG(0xd2000008 + ((N) * 0x100), u32) /* src addr reg */
70 #define DMxSIZ(N) __SYSREG(0xd200000c + ((N) * 0x100), u32) /* dest addr reg */
73 #define DMxCYC(N) __SYSREG(0xd2000010 + ((N) * 0x100), u32) /* intermittent
H A Dreset-regs.h29 #define WDCTR __SYSREG(0xc0001002, u8) /* watchdog timer control reg */
39 #define RSTCTR __SYSREG(0xc0001004, u8) /* reset control reg */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mn10300/unit-asb2305/include/unit/
H A Dserial.h19 #define ASB2305_DEBUG_MCR __SYSREG(0xA6FB0000 + UART_MCR * 2, u8)
51 #define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 4, u8)
52 #define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8)
53 #define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 4, u8)
54 #define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 4, u8)
55 #define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 4, u8)
56 #define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 4, u8)
57 #define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8)
58 #define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8)
59 #define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRES
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mn10300/unit-asb2305/include/unit/
H A Dserial.h19 #define ASB2305_DEBUG_MCR __SYSREG(0xA6FB0000 + UART_MCR * 2, u8)
51 #define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 4, u8)
52 #define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8)
53 #define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 4, u8)
54 #define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 4, u8)
55 #define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 4, u8)
56 #define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 4, u8)
57 #define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8)
58 #define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8)
59 #define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRES
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