Lines Matching refs:__SYSREG
32 #define __SYSREG(ADDR, TYPE) (*(volatile TYPE *)(ADDR))
35 #define __SYSREG(ADDR, TYPE) ADDR
87 #define CPUP __SYSREG(0xc0000020, u16) /* CPU pipeline register */
94 #define CPUM __SYSREG(0xc0000040, u16) /* CPU mode register */
119 #define DCR __SYSREG(0xc0000030, u16) /* Debug control register */
122 #define IVAR0 __SYSREG(0xc0000000, u16) /* interrupt vector 0 */
123 #define IVAR1 __SYSREG(0xc0000004, u16) /* interrupt vector 1 */
124 #define IVAR2 __SYSREG(0xc0000008, u16) /* interrupt vector 2 */
125 #define IVAR3 __SYSREG(0xc000000c, u16) /* interrupt vector 3 */
126 #define IVAR4 __SYSREG(0xc0000010, u16) /* interrupt vector 4 */
127 #define IVAR5 __SYSREG(0xc0000014, u16) /* interrupt vector 5 */
128 #define IVAR6 __SYSREG(0xc0000018, u16) /* interrupt vector 6 */
130 #define TBR __SYSREG(0xc0000024, u32) /* Trap table base */
134 #define DEAR __SYSREG(0xc0000038, u32) /* Data access exception address */
136 #define sISR __SYSREG(0xc0000044, u32) /* Supervisor interrupt status */
169 #define CHCTR __SYSREG(0xc0000070, u16) /* cache control */
184 #define MMUCTR __SYSREG(0xc0000090, u32) /* MMU control register */
207 #define PIDR __SYSREG(0xc0000094, u16) /* PID register */
210 #define PTBR __SYSREG(0xc0000098, unsigned long) /* Page table base register */
212 #define IPTEL __SYSREG(0xc00000a0, u32) /* instruction TLB entry */
213 #define DPTEL __SYSREG(0xc00000b0, u32) /* data TLB entry */
242 #define IPTEU __SYSREG(0xc00000a4, u32) /* instruction TLB virtual addr */
243 #define DPTEU __SYSREG(0xc00000b4, u32) /* data TLB virtual addr */
247 #define IPTEL2 __SYSREG(0xc00000a8, u32) /* instruction TLB entry */
248 #define DPTEL2 __SYSREG(0xc00000b8, u32) /* data TLB entry */