Lines Matching refs:__SYSREG
21 #define TMPSCNT __SYSREG(0xd4003071, u8) /* timer prescaler control */
26 #define TM0MD __SYSREG(0xd4003000, u8) /* timer 0 mode register */
38 #define TM1MD __SYSREG(0xd4003001, u8) /* timer 1 mode register */
50 #define TM2MD __SYSREG(0xd4003002, u8) /* timer 2 mode register */
62 #define TM3MD __SYSREG(0xd4003003, u8) /* timer 3 mode register */
75 #define TM01MD __SYSREG(0xd4003000, u16) /* timer 0:1 mode register */
77 #define TM0BR __SYSREG(0xd4003010, u8) /* timer 0 base register */
78 #define TM1BR __SYSREG(0xd4003011, u8) /* timer 1 base register */
79 #define TM2BR __SYSREG(0xd4003012, u8) /* timer 2 base register */
80 #define TM3BR __SYSREG(0xd4003013, u8) /* timer 3 base register */
81 #define TM01BR __SYSREG(0xd4003010, u16) /* timer 0:1 base register */
100 #define TM4MD __SYSREG(0xd4003080, u8) /* timer 4 mode register */
112 #define TM5MD __SYSREG(0xd4003082, u8) /* timer 5 mode register */
125 #define TM7MD __SYSREG(0xd4003086, u8) /* timer 7 mode register */
137 #define TM8MD __SYSREG(0xd4003088, u8) /* timer 8 mode register */
150 #define TM9MD __SYSREG(0xd400308a, u8) /* timer 9 mode register */
163 #define TM10MD __SYSREG(0xd400308c, u8) /* timer 10 mode register */
176 #define TM11MD __SYSREG(0xd400308e, u8) /* timer 11 mode register */
189 #define TM4BR __SYSREG(0xd4003090, u16) /* timer 4 base register */
190 #define TM5BR __SYSREG(0xd4003092, u16) /* timer 5 base register */
191 #define TM7BR __SYSREG(0xd4003096, u16) /* timer 7 base register */
192 #define TM8BR __SYSREG(0xd4003098, u16) /* timer 8 base register */
193 #define TM9BR __SYSREG(0xd400309a, u16) /* timer 9 base register */
194 #define TM10BR __SYSREG(0xd400309c, u16) /* timer 10 base register */
195 #define TM11BR __SYSREG(0xd400309e, u16) /* timer 11 base register */
196 #define TM45BR __SYSREG(0xd4003090, u32) /* timer 4:5 base register */
198 #define TM4BC __SYSREG(0xd40030a0, u16) /* timer 4 binary counter */
199 #define TM5BC __SYSREG(0xd40030a2, u16) /* timer 5 binary counter */
200 #define TM45BC __SYSREG(0xd40030a0, u32) /* timer 4:5 binary counter */
202 #define TM7BC __SYSREG(0xd40030a6, u16) /* timer 7 binary counter */
203 #define TM8BC __SYSREG(0xd40030a8, u16) /* timer 8 binary counter */
204 #define TM9BC __SYSREG(0xd40030aa, u16) /* timer 9 binary counter */
205 #define TM10BC __SYSREG(0xd40030ac, u16) /* timer 10 binary counter */
206 #define TM11BC __SYSREG(0xd40030ae, u16) /* timer 11 binary counter */
225 #define TM6MD __SYSREG(0xd4003084, u16) /* timer6 mode register */
246 #define TM6MDA __SYSREG(0xd40030b4, u8) /* timer6 cmp/cap A mode reg */
263 #define TM6MDB __SYSREG(0xd40030b5, u8) /* timer6 cmp/cap B mode reg */
279 #define TM6CA __SYSREG(0xd40030c4, u16) /* timer6 cmp/capture reg A */
280 #define TM6CB __SYSREG(0xd40030d4, u16) /* timer6 cmp/capture reg B */
281 #define TM6BC __SYSREG(0xd40030a4, u16) /* timer6 binary counter */