Lines Matching refs:__SYSREG
21 #define SC0CTR __SYSREG(0xd4002000, u16) /* control reg */
61 #define SC0ICR __SYSREG(0xd4002004, u8) /* interrupt control reg */
68 #define SC0TXB __SYSREG(0xd4002008, u8) /* transmit buffer reg */
69 #define SC0RXB __SYSREG(0xd4002009, u8) /* receive buffer reg */
71 #define SC0STR __SYSREG(0xd400200c, u16) /* status reg */
89 #define SC1CTR __SYSREG(0xd4002010, u16) /* serial port 1 control */
90 #define SC1ICR __SYSREG(0xd4002014, u8) /* interrupt control reg */
91 #define SC1TXB __SYSREG(0xd4002018, u8) /* transmit buffer reg */
92 #define SC1RXB __SYSREG(0xd4002019, u8) /* receive buffer reg */
93 #define SC1STR __SYSREG(0xd400201c, u16) /* status reg */
102 #define SC2CTR __SYSREG(0xd4002020, u16) /* control reg */
131 #define SC2ICR __SYSREG(0xd4002024, u8) /* interrupt control reg */
137 #define SC2TXB __SYSREG(0xd4002018, u8) /* transmit buffer reg */
138 #define SC2RXB __SYSREG(0xd4002019, u8) /* receive buffer reg */
139 #define SC2STR __SYSREG(0xd400201c, u8) /* status reg */
149 #define SC2TIM __SYSREG(0xd400202d, u8) /* status reg */