Searched refs:divider (Results 76 - 100 of 147) sorted by last modified time

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/linux-master/drivers/clk/bcm/
H A Dclk-bcm2835.c494 /* Number of integer bits in the divider */
496 /* Number of fractional bits in the divider */
804 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); local
805 struct bcm2835_cprman *cprman = divider->cprman;
806 const struct bcm2835_pll_divider_data *data = divider->data;
825 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); local
826 struct bcm2835_cprman *cprman = divider->cprman;
827 const struct bcm2835_pll_divider_data *data = divider->data;
841 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); local
842 struct bcm2835_cprman *cprman = divider
861 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); local
883 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); local
1376 struct bcm2835_pll_divider *divider; local
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/linux-master/drivers/clk/baikal-t1/
H A Dclk-ccu-div.c76 .divider = _divider \
95 .divider = _divider \
106 unsigned int divider; member in union:ccu_div_info::__anon91
374 init.divider = info->divider;
379 init.divider = info->divider;
385 pr_err("Couldn't register divider '%s' hw\n",
439 pr_err("Couldn't register divider '%s' reset controller\n",
H A Dccu-div.h26 * @CCU_DIV_BASIC: Basic divider clock required by the kernel as early as
28 * @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.
30 * @CCU_DIV_SKIP_ONE_TO_THREE: For some reason divider can't be within [1,3].
43 * @CCU_DIV_VAR: Clocks gate with variable divider.
44 * @CCU_DIV_GATE: Clocks gate with fixed divider.
45 * @CCU_DIV_BUF: Clock gate with no divider.
46 * @CCU_DIV_FIXED: Ungateable clock with fixed divider.
63 * @type: CCU divider type (variable, fixed with and without gate).
65 * @divider: Divider fixed value.
79 unsigned int divider; member in union:ccu_div_init_data::__anon8
105 unsigned int divider; member in union:ccu_div::__anon9
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H A Dccu-div.c78 unsigned long divider)
85 nd = ccu_div_lock_delay_ns(parent_rate, divider);
211 unsigned long divider; local
215 divider = ccu_div_get(div->mask, val);
217 return ccu_div_calc_freq(parent_rate, divider);
224 unsigned long divider; local
226 divider = parent_rate / rate;
227 return clamp_t(unsigned long, divider, CCU_DIV_CLKDIV_MIN,
235 unsigned long divider; local
237 divider
76 ccu_div_var_update_clkdiv(struct ccu_div *div, unsigned long parent_rate, unsigned long divider) argument
251 unsigned long flags, divider; local
285 unsigned long flags, divider; local
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/linux-master/drivers/cpufreq/
H A Darmada-37xx-cpufreq.c69 * divider, a VDD level, etc...
100 u8 divider[LOAD_LEVEL_NR]; member in struct:armada_37xx_dvfs
109 /* {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} }, */
110 {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
111 {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} },
112 {.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} },
133 struct regmap *clk_base, u8 *divider)
166 * Set cpu divider based on the pre-computed array in
169 val |= divider[load_lvl] << ARMADA_37XX_NB_TBG_DIV_OFF;
173 /* Set VDD divider whic
132 armada37xx_cpufreq_dvfs_setup(struct regmap *base, struct regmap *clk_base, u8 *divider) argument
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/linux-master/drivers/soundwire/
H A Dcadence_master.c1330 int divider; local
1332 /* Set clock divider */
1333 divider = (prop->mclk_freq / prop->max_clk_freq) - 1;
1336 CDNS_MCP_CLK_MCLKD_MASK, divider);
1338 CDNS_MCP_CLK_MCLKD_MASK, divider);
1418 int divider; local
1425 divider = prop->mclk_freq * SDW_DOUBLE_RATE_FACTOR /
1427 divider--; /* divider is 1/(N+1) */
1434 cdns_updatel(cdns, mcp_clkctrl_off, CDNS_MCP_CLK_MCLKD_MASK, divider);
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/linux-master/drivers/iio/chemical/
H A Dsgp40.c104 u32 factorial, divider, xmax; local
120 divider = 0;
125 y += (xp >> divider) / factorial;
126 divider += power;
130 divider -= power;
/linux-master/drivers/watchdog/
H A Dnic7018_wdt.c53 u8 divider; member in struct:nic7018_config
95 outb(counter << 4 | config->divider,
/linux-master/drivers/clk/ux500/
H A Dclk-prcmu.c29 u8 divider; member in struct:clk_prcmu_clkout
302 return prcmu_config_clkout(clk->clkout_id, clk->source, clk->divider);
322 return (parent_rate / clk->divider);
355 u8 source, u8 divider)
383 clk->divider = divider;
352 clk_reg_prcmu_clkout(const char *name, const char * const *parent_names, int num_parents, u8 source, u8 divider) argument
/linux-master/drivers/clk/tegra/
H A Dclk-periph.c41 struct clk_hw *div_hw = &periph->divider.hw;
53 struct clk_hw *div_hw = &periph->divider.hw;
71 struct clk_hw *div_hw = &periph->divider.hw;
122 struct clk_hw *div_hw = &periph->divider.hw;
200 periph->divider.reg = div ? (clk_base + offset) : NULL;
210 periph->divider.hw.clk = div ? clk : NULL;
/linux-master/drivers/clk/nuvoton/
H A DMakefile3 obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1-divider.o
/linux-master/drivers/clk/
H A Dclk-cdce706.c84 struct cdce706_hw_data divider[6]; member in struct:cdce706_dev_data
284 "%s, divider: %d, div: %u\n",
354 "%s, divider: %d, div: %lu\n",
367 "%s, divider: %d, div: %u\n",
567 for (i = 0; i < ARRAY_SIZE(cdce->divider); ++i) {
573 cdce->divider[i].parent =
580 cdce->divider[i].div = val & CDCE706_DIVIDER_DIVIDER_MASK;
583 cdce->divider[i].parent, cdce->divider[i].div);
586 ret = cdce706_register_hw(cdce, cdce->divider,
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H A Dclk-axi-clkgen.c193 static void axi_clkgen_calc_clk_params(unsigned int divider, argument
199 if (divider == 1) {
205 params->high = divider / 2;
206 params->edge = divider % 2;
207 params->low = divider - params->high;
212 params->high = divider / 2;
213 params->edge = divider % 2;
224 (divider == 2 && frac_divider == 1))
H A Dclk-divider.c7 * Adjustable divider clock implementation
20 * DOC: basic adjustable divider clock that cannot gate
29 static inline u32 clk_div_readl(struct clk_divider *divider) argument
31 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
32 return ioread32be(divider->reg);
34 return readl(divider->reg);
37 static inline void clk_div_writel(struct clk_divider *divider, u32 val) argument
39 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
40 iowrite32be(val, divider->reg);
42 writel(val, divider
152 struct clk_divider *divider = to_clk_divider(hw); local
431 struct clk_divider *divider = to_clk_divider(hw); local
452 struct clk_divider *divider = to_clk_divider(hw); local
490 struct clk_divider *divider = to_clk_divider(hw); local
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H A Dclk-xgene.c429 void __iomem *divider_reg; /* CSR for divider */
430 u32 reg_divider_offset; /* Offset to divider register */
431 u32 reg_divider_shift; /* Bit shift to divider field */
432 u32 reg_divider_width; /* Width of the bit to divider field */
562 u32 divider; local
569 /* Let's compute the divider */
572 divider_save = divider = parent_rate / rate; /* Rounded down */
573 divider &= (1 << pclk->param.reg_divider_width) - 1;
574 divider <<= pclk->param.reg_divider_shift;
576 /* Set new divider */
601 u32 divider; local
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/linux-master/drivers/clk/berlin/
H A Dberlin2-div.c20 * input pll and divider. The virtual structure as it is used in Marvell
35 * (C) programmable clock divider controlled by <Select[1:n]>
36 * (D) constant div-by-3 clock divider
37 * (E) programmable clock divider bypass controlled by <Switch>
181 u32 divsw, div3sw, divider = 1; local
193 divider = 3;
194 /* divider can be bypassed with DIV_SWITCH == 0 */
196 divider = 1;
197 /* clock divider determined by DIV_SELECT */
203 divider
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/linux-master/drivers/clk/imx/
H A Dclk-composite-93.c109 struct clk_divider *divider = to_clk_divider(hw); local
115 value = divider_get_val(rate, parent_rate, divider->table, divider->width, divider->flags);
119 if (divider->lock)
120 spin_lock_irqsave(divider->lock, flags);
122 val = readl(divider->reg);
123 val &= ~(clk_div_mask(divider->width) << divider->shift);
124 val |= (u32)value << divider
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/linux-master/sound/soc/spear/
H A Dspdif_out.c94 u32 divider, ctrl; local
97 divider = DIV_ROUND_CLOSEST(clk_get_rate(host->clk), (rate * 128));
101 ctrl |= (divider << SPDIF_DIVIDER_SHIFT) & SPDIF_DIVIDER_MASK;
/linux-master/drivers/gpu/drm/radeon/
H A Dradeon_legacy_crtc.c754 int divider; member in struct:__anon1219
822 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
823 if (post_div->divider == post_divider)
827 if (!post_div->divider)
929 This appears to related to the PLL divider registers (fail to lock?).
975 /* R300 uses ref_div_acc field as real ref divider */
/linux-master/lib/zstd/compress/
H A Dzstd_compress.c1400 U32 const divider = (cParams->minMatch==3) ? 3 : 4; local
1401 size_t const maxNbSeq = blockSize / divider;
1780 U32 const divider = (params->cParams.minMatch==3) ? 3 : 4; local
1781 size_t const maxNbSeq = blockSize / divider;
/linux-master/drivers/clk/x86/
H A Dclk-cgu.c125 struct lgm_clk_divider *divider = to_lgm_clk_divider(hw); local
128 val = lgm_get_clk_val(divider->membase, divider->reg,
129 divider->shift, divider->width);
131 return divider_recalc_rate(hw, parent_rate, val, divider->table,
132 divider->flags, divider->width);
139 struct lgm_clk_divider *divider = to_lgm_clk_divider(hw); local
141 return divider_round_rate(hw, rate, prate, divider
149 struct lgm_clk_divider *divider = to_lgm_clk_divider(hw); local
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/linux-master/drivers/clk/ti/
H A Dclk-dra7-atl.c49 u32 divider; /* Cached divider value */ member in struct:dra7_atl_desc
85 cdesc->divider - 1);
120 return parent_rate / cdesc->divider;
126 unsigned divider; local
128 divider = (*parent_rate + rate / 2) / rate;
129 if (divider > DRA7_ATL_DIVIDER_MASK + 1)
130 divider = DRA7_ATL_DIVIDER_MASK + 1;
132 return *parent_rate / divider;
139 u32 divider; local
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/linux-master/drivers/clk/rockchip/
H A DMakefile11 clk-rockchip-y += clk-half-divider.o
/linux-master/drivers/clk/mvebu/
H A Ddove-divider.c3 * Marvell Dove PMU Core PLL divider driver
15 #include "dove-divider.h"
53 unsigned int divider; local
59 divider = val & ~(~0 << dc->div_bit_size);
62 divider = dc->divider_table[divider];
64 return divider;
70 unsigned int divider, max; local
72 divider = DIV_ROUND_CLOSEST(parent_rate, rate);
78 if (divider
102 unsigned int divider = dove_get_divider(dc); local
116 int divider; local
135 int divider; local
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/linux-master/drivers/media/pci/cx23885/
H A Dcx23888-ir.c163 * Note the largest clock divider value of 0xffff corresponds to:
184 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) argument
186 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16);
189 static inline unsigned int clock_divider_to_freq(unsigned int divider, argument
193 (divider + 1) * rollovers);
234 static u32 clock_divider_to_resolution(u16 divider) argument
241 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
245 static u64 pulse_width_count_to_ns(u16 count, u16 divider) argument
254 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
261 static unsigned int pulse_width_count_to_us(u16 count, u16 divider) argument
411 txclk_tx_s_carrier(struct cx23885_dev *dev, unsigned int freq, u16 *divider) argument
420 rxclk_rx_s_carrier(struct cx23885_dev *dev, unsigned int freq, u16 *divider) argument
429 txclk_tx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns, u16 *divider) argument
442 rxclk_rx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns, u16 *divider) argument
634 u16 divider = (u16) atomic_read(&state->rxclk_divider); local
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