pci/cx23885/cx23888-ir.c

163  * Note the largest clock divider value of 0xffff corresponds to:
184 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
186 	return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16);
189 static inline unsigned int clock_divider_to_freq(unsigned int divider,
193 				 (divider + 1) * rollovers);
234 static u32 clock_divider_to_resolution(u16 divider)
241 	return DIV_ROUND_CLOSEST((1 << 2)  * ((u32) divider + 1) * 1000,
245 static u64 pulse_width_count_to_ns(u16 count, u16 divider)
254 	n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
261 static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
270 	n = (((u64) count << 2) | 0x3) * (divider + 1);    /* cycles      */
281  * significant part and (up to) 16 bit clock divider count as a modulus.
282  * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
413 				       u16 *divider)
415 	*divider = carrier_freq_to_clock_divider(freq);
416 	cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
417 	return clock_divider_to_carrier_freq(*divider);
422 				       u16 *divider)
424 	*divider = carrier_freq_to_clock_divider(freq);
425 	cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
426 	return clock_divider_to_carrier_freq(*divider);
430 				      u16 *divider)
437 	*divider = pulse_clocks_to_clock_divider(pulse_clocks);
438 	cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
439 	return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
443 				      u16 *divider)
450 	*divider = pulse_clocks_to_clock_divider(pulse_clocks);
451 	cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
452 	return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
634 	u16 divider = (u16) atomic_read(&state->rxclk_divider);
666 				  (u16)(p->hw_fifo_data & FIFO_RXTX), divider) / 1000;