/linux-master/arch/arm64/kvm/vgic/ |
H A D | vgic-v2.c | 194 /* The GICv2 LR only holds five bits of priority. */ 195 val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
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H A D | vgic-v3.c | 184 val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
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H A D | vgic-v4.c | 112 vpe->sgi_config[irq->intid].priority = irq->priority; 453 .properties = ((irq->priority & 0xfc) |
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H A D | vgic.c | 229 * (and therefore take priority) since we cannot reliably trap on deactivation 232 * Otherwise things should be sorted by the priority field and the GIC 233 * hardware support will take care of preemption of priority groups etc. 269 /* Both pending and enabled, sort by priority */ 270 ret = irqa->priority - irqb->priority; 800 * lower priority. In that case, we need to filter out 804 if (multi_sgi && irq->priority > prio) { 813 prio = irq->priority; 962 irq->priority < vmc [all...] |
/linux-master/arch/loongarch/include/asm/ |
H A D | cpu-info.h | 88 .priority = pri \
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/linux-master/arch/loongarch/kvm/ |
H A D | interrupt.c | 26 static int kvm_irq_deliver(struct kvm_vcpu *vcpu, unsigned int priority) argument 30 clear_bit(priority, &vcpu->arch.irq_pending); 31 if (priority < EXCCODE_INT_NUM) 32 irq = priority_to_irq[priority]; 34 switch (priority) { 53 static int kvm_irq_clear(struct kvm_vcpu *vcpu, unsigned int priority) argument 57 clear_bit(priority, &vcpu->arch.irq_clear); 58 if (priority < EXCCODE_INT_NUM) 59 irq = priority_to_irq[priority]; 61 switch (priority) { 82 unsigned int priority; local [all...] |
/linux-master/arch/mips/cavium-octeon/executive/ |
H A D | cvmx-pko.c | 172 const uint64_t priority = 8; local 175 &priority); 315 * @priority: Array of priority levels for each queue. Values are 319 * on the fly while the pko is enabled. A priority of 9 320 * indicates that static priority should be used. If static 321 * priority is used all queues with static priority must be 323 * queues have higher priority than higher numbered queues. 328 const uint64_t priority[]) 326 cvmx_pko_config_port(uint64_t port, uint64_t base_queue, uint64_t num_queues, const uint64_t priority[]) argument [all...] |
/linux-master/arch/mips/include/asm/ |
H A D | cop2.h | 55 .priority = pri \
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H A D | cpu-info.h | 140 .priority = pri \
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H A D | kvm_host.h | 745 int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority, 747 int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
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H A D | traps.h | 36 .priority = pri \
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/linux-master/arch/mips/include/asm/octeon/ |
H A D | cvmx-pko.h | 304 * @priority: Array of priority levels for each queue. Values are 312 const uint64_t priority[]);
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H A D | cvmx-pow.h | 1862 * an associated priority value. 1865 * @priority: Vector of 8 priorities, one per POW Input Queue (0-7). 1866 * Highest priority is 0 and lowest is 7. A priority value 1874 const uint8_t priority[]) 1881 grp_msk.s.qos0_pri = priority[0]; 1882 grp_msk.s.qos1_pri = priority[1]; 1883 grp_msk.s.qos2_pri = priority[2]; 1884 grp_msk.s.qos3_pri = priority[3]; 1885 grp_msk.s.qos4_pri = priority[ 1873 cvmx_pow_set_priority(uint64_t core_num, const uint8_t priority[]) argument [all...] |
/linux-master/arch/mips/kvm/ |
H A D | interrupt.c | 28 unsigned int priority; local 33 priority = __ffs(*pending_clr); 34 while (priority <= MIPS_EXC_MAX) { 35 kvm_mips_callbacks->irq_clear(vcpu, priority, cause); 37 priority = find_next_bit(pending_clr, 39 priority + 1); 42 priority = __ffs(*pending); 43 while (priority <= MIPS_EXC_MAX) { 44 kvm_mips_callbacks->irq_deliver(vcpu, priority, cause); 46 priority [all...] |
H A D | vz.c | 203 static void kvm_vz_queue_irq(struct kvm_vcpu *vcpu, unsigned int priority) argument 205 set_bit(priority, &vcpu->arch.pending_exceptions); 206 clear_bit(priority, &vcpu->arch.pending_exceptions_clr); 209 static void kvm_vz_dequeue_irq(struct kvm_vcpu *vcpu, unsigned int priority) argument 211 clear_bit(priority, &vcpu->arch.pending_exceptions); 212 set_bit(priority, &vcpu->arch.pending_exceptions_clr); 257 static int kvm_vz_irq_deliver_cb(struct kvm_vcpu *vcpu, unsigned int priority, argument 260 u32 irq = (priority < MIPS_EXC_MAX) ? 261 kvm_priority_to_irq[priority] : 0; 263 switch (priority) { 286 kvm_vz_irq_clear_cb(struct kvm_vcpu *vcpu, unsigned int priority, u32 cause) argument [all...] |
/linux-master/arch/parisc/kernel/ |
H A D | kgdb.c | 50 .priority = -INT_MAX,
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H A D | pdc_chassis.c | 100 .priority = INT_MAX, 123 .priority = INT_MAX,
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/linux-master/arch/powerpc/include/asm/ |
H A D | epapr_hcalls.h | 131 * @priority: interrupt priority 137 uint32_t config, unsigned int priority, uint32_t destination) 148 r5 = priority; 163 * @priority: returned interrupt priority 169 uint32_t *config, unsigned int *priority, uint32_t *destination) 186 *priority = r5; 251 * definition, this is also the highest-priority interrupt. 136 ev_int_set_config(unsigned int interrupt, uint32_t config, unsigned int priority, uint32_t destination) argument 168 ev_int_get_config(unsigned int interrupt, uint32_t *config, unsigned int *priority, uint32_t *destination) argument
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H A D | kvm_ppc.h | 237 u32 priority); 239 u32 *priority); 722 u32 priority); 724 u32 *priority); 760 u32 priority) { return -1; } 762 u32 *priority) { return -1; } 759 kvmppc_xive_set_xive(struct kvm *kvm, u32 irq, u32 server, u32 priority) argument 761 kvmppc_xive_get_xive(struct kvm *kvm, u32 irq, u32 *server, u32 *priority) argument
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H A D | opal.h | 77 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority); 78 int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
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H A D | ppc_asm.h | 164 /* Macros to adjust thread priority for hardware multithreading */ 165 #define HMT_VERY_LOW or 31,31,31 # very low priority 167 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority 169 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
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/linux-master/arch/powerpc/kernel/ |
H A D | setup-common.c | 780 .priority = INT_MAX, /* run early, to notify the firmware ASAP */ 789 .priority = INT_MIN, /* may not return; must be done last */
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/linux-master/arch/powerpc/kvm/ |
H A D | book3s.c | 297 unsigned int priority) 303 switch (priority) { 359 printk(KERN_ERR "KVM: Unknown interrupt: 0x%x\n", priority); 372 static bool clear_irqprio(struct kvm_vcpu *vcpu, unsigned int priority) argument 374 switch (priority) { 398 unsigned int priority; local 404 priority = __ffs(*pending); 405 while (priority < BOOK3S_IRQPRIO_MAX) { 406 if (kvmppc_book3s_irqprio_deliver(vcpu, priority) && 407 clear_irqprio(vcpu, priority)) { 296 kvmppc_book3s_irqprio_deliver(struct kvm_vcpu *vcpu, unsigned int priority) argument [all...] |
H A D | book3s_hv_rm_xics.c | 239 static bool icp_rm_try_to_deliver(struct kvmppc_icp *icp, u32 irq, u8 priority, argument 251 success = new_state.cppr > priority && 252 new_state.mfrr > priority && 253 new_state.pending_pri > priority; 262 new_state.pending_pri = priority; 345 if (state->priority == MASKED) { 366 if (icp_rm_try_to_deliver(icp, new_irq, state->priority, &reject)) { 506 * pending priority 639 * The processor is raising its priority, this can result
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H A D | book3s_rtas.c | 21 u32 irq, server, priority; local 31 priority = be32_to_cpu(args->args[2]); 34 rc = kvmppc_xive_set_xive(vcpu->kvm, irq, server, priority); 36 rc = kvmppc_xics_set_xive(vcpu->kvm, irq, server, priority); 45 u32 irq, server, priority; local 55 server = priority = 0; 57 rc = kvmppc_xive_get_xive(vcpu->kvm, irq, &server, &priority); 59 rc = kvmppc_xics_get_xive(vcpu->kvm, irq, &server, &priority); 66 args->rets[2] = cpu_to_be32(priority);
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