Searched refs:lanes (Results 51 - 75 of 277) sorted by relevance

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/linux-master/drivers/phy/rockchip/
H A Dphy-rockchip-inno-csidphy.c206 dev_dbg(priv->dev, "lanes %d - data_rate_mbps %llu\n",
207 config->lanes, data_rate_mbps);
247 val = FIELD_PREP(CSIDPHY_CTRL_LANE_ENABLE_MASK, GENMASK(priv->config.lanes - 1, 0)) |
272 for (i = 0; i < priv->config.lanes; i++)
280 for (i = 0; i < priv->config.lanes; i++)
286 GENMASK(priv->config.lanes - 1, 0));
296 /* disable all lanes */
/linux-master/drivers/staging/media/imx/
H A Dimx6-mipi-csi2.c113 * 2. Configure MIPI Camera Sensor to put all Tx lanes in LP-11 state.
121 * clock lanes of the D-PHY are in LP-11 state.
145 static void csi2_set_lanes(struct csi2_dev *csi2, unsigned int lanes) argument
147 writel(lanes - 1, csi2->base + CSI2_N_LANES);
254 /* Waits for low-power LP-11 state on data and clock lanes. */
255 static void csi2_dphy_wait_stopstate(struct csi2_dev *csi2, unsigned int lanes) argument
260 mask = PHY_STOPSTATECLK | (((1 << lanes) - 1) << PHY_STOPSTATEDATA_BIT);
304 static int csi2_get_active_lanes(struct csi2_dev *csi2, unsigned int *lanes) argument
309 *lanes = csi2->data_lanes;
331 "Unsupported mbus config: too many data lanes
343 unsigned int lanes; local
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/linux-master/drivers/gpu/drm/renesas/rcar-du/
H A Drzg2l_mipi_dsi.c45 unsigned int lanes; member in struct:rzg2l_mipi_dsi
274 * vclk * bpp = hsclk * 8 * lanes
278 * lanes: number of data lanes
283 hsfreq = (mode->clock * bpp * 8) / (8 * dsi->lanes);
295 /* Enable Data lanes and Clock lanes */
296 txsetr = TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLEN;
304 * - data lanes: maximum 4 lanes
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H A Drcar_mipi_dsi.c75 unsigned int lanes; member in struct:rcar_mipi_dsi
281 if (dsi->lanes <= 1) {
287 if (dsi->lanes <= 2) {
293 if (dsi->lanes <= 3) {
398 / (2 * dsi->lanes);
631 vclkset |= VCLKSET_COLOR_RGB | VCLKSET_LANE(dsi->lanes - 1);
905 if (device->lanes > dsi->num_data_lanes)
908 dsi->lanes = device->lanes;
952 dev_err(dsi->dev, "missing or invalid data-lanes propert
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/linux-master/drivers/media/platform/renesas/
H A Drcar-csi2.c621 unsigned short lanes; member in struct:rcar_csi2
680 unsigned int lanes)
684 /* Wait for the clock and data lanes to enter LP-11 state. */
686 const u32 lane_mask = (1 << lanes) - 1;
730 unsigned int lanes)
755 do_div(mbps, lanes * 1000000);
765 unsigned int *lanes)
770 *lanes = priv->lanes;
799 if (mbus_config.bus.mipi_csi2.num_data_lanes > priv->lanes) {
679 rcsi2_wait_phy_start(struct rcar_csi2 *priv, unsigned int lanes) argument
729 rcsi2_calc_mbps(struct rcar_csi2 *priv, unsigned int bpp, unsigned int lanes) argument
764 rcsi2_get_active_lanes(struct rcar_csi2 *priv, unsigned int *lanes) argument
815 unsigned int lanes; local
1055 unsigned int lanes; local
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/linux-master/drivers/media/platform/cadence/
H A Dcdns-csi2rx.c93 u8 lanes[CSI2RX_LANES_MAX]; member in struct:csi2rx_priv
223 reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, csi2rx->lanes[i]);
224 set_bit(csi2rx->lanes[i], &lanes_used);
228 * Even the unused lanes need to be mapped. In order to avoid
229 * to map twice to the same physical lane, keep the lanes used
230 * in the previous loop, and only map unused physical lanes to
231 * the rest of our logical lanes.
246 /* Enable DPHY clk and data lanes. */
250 reg |= CSI2RX_DPHY_DL_EN(csi2rx->lanes[i] - 1);
251 reg |= CSI2RX_DPHY_DL_RST(csi2rx->lanes[
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/linux-master/drivers/staging/media/atomisp/pci/
H A Datomisp_gmin_platform.c192 pdata.subdevs[i].lanes = gs->csi_lanes;
1068 static int camera_sensor_csi_alloc(struct v4l2_subdev *sd, u32 port, u32 lanes, argument
1079 csi->num_lanes = lanes;
1086 "camera pdata: port: %d lanes: %d order: %8.8x\n",
1087 port, lanes, bayer_order);
1115 int atomisp_register_sensor_no_gmin(struct v4l2_subdev *subdev, u32 lanes, argument
1136 lanes = gmin_get_var_int(&client->dev, false, "CsiLanes", lanes);
1148 ret = camera_sensor_csi_alloc(subdev, port, lanes, format, bayer_order);
1154 pdata.subdevs[i].lanes
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H A Datomisp_v4l2.c693 u8 lanes[N_MIPI_PORT_ID]; member in struct:__anon564
747 isp->sensor_lanes[j] != portconfigs[i].lanes[j])
765 | (portconfigs[i].lanes[0] ? 0 : (1 << MRFLD_PORT1_ENABLE_SHIFT))
766 | (portconfigs[i].lanes[1] ? 0 : (1 << MRFLD_PORT2_ENABLE_SHIFT))
767 | (portconfigs[i].lanes[2] ? 0 : (1 << MRFLD_PORT3_ENABLE_SHIFT))
768 | (((1 << portconfigs[i].lanes[0]) - 1) << MRFLD_PORT1_LANES_SHIFT)
769 | (((1 << portconfigs[i].lanes[1]) - 1) << MRFLD_PORT2_LANES_SHIFT)
770 | (((1 << portconfigs[i].lanes[2]) - 1) << port3_lanes_shift);
776 __func__, portconfigs[i].lanes[0], portconfigs[i].lanes[
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/linux-master/drivers/gpu/drm/mcde/
H A Dmcde_dsi.c175 if (mdsi->lanes < 1 || mdsi->lanes > 2) {
176 DRM_ERROR("dsi device params invalid, 1 or 2 lanes supported\n");
180 dev_info(d->dev, "attached DSI device with %d lanes\n", mdsi->lanes);
606 /* parallel transactions in all lanes */
607 bpl *= d->mdsi->lanes;
652 if (d->mdsi->lanes == 2 && (hsa & 0x01) && (hfp & 0x01)
655 line_duration = DIV_ROUND_CLOSEST(line_duration, d->mdsi->lanes);
722 d->mdsi->lanes);
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/linux-master/drivers/gpu/drm/panel/
H A Dpanel-himax-hx8394.c80 unsigned int lanes; member in struct:hx8394_panel_desc
202 .lanes = 4,
335 .lanes = 4,
508 dsi->lanes = ctx->desc->lanes;
539 mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes);
H A Dpanel-samsung-s6e63m0-dsi.c97 dsi->lanes = 2;
H A Dpanel-innolux-p079zca.c40 unsigned int lanes; member in struct:panel_desc
230 .lanes = 4,
378 .lanes = 4,
492 dsi->lanes = desc->lanes;
/linux-master/drivers/phy/tegra/
H A Dxusb.h29 * lanes
162 const struct tegra_xusb_lane_soc *lanes; member in struct:tegra_xusb_pad_soc
172 struct phy **lanes; member in struct:tegra_xusb_pad
455 struct list_head lanes; member in struct:tegra_xusb_padctl
/linux-master/drivers/gpu/drm/mediatek/
H A Dmtk_dsi.c211 unsigned int lanes; member in struct:mtk_dsi
374 /* Number of DSI lanes (max 4 lanes), each bit enables one DSI lane. */
375 for (i = 0; i < dsi->lanes; i++)
472 data_phy_cycles_byte = data_phy_cycles * dsi->lanes + delta;
487 (dsi->lanes == 4)) {
489 roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
491 roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
493 roundup(horizontal_backporch_byte, dsi->lanes) - 2;
495 (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpower_state.h91 unsigned int lanes; member in struct:PP_StatePcieBlock
/linux-master/include/drm/bridge/
H A Dsamsung-dsim.h102 u32 lanes; member in struct:samsung_dsim
/linux-master/include/linux/
H A Dnubus.h59 unsigned char lanes; member in struct:nubus_board
/linux-master/drivers/media/platform/qcom/camss/
H A Dcamss.h141 unsigned int lanes);
/linux-master/drivers/gpu/drm/bridge/cadence/
H A Dcdns-dsi-core.c526 unsigned int lanes = output->dev->lanes; local
541 if (dsi_htotal % lanes)
542 adj_dsi_htotal += lanes - (dsi_htotal % lanes);
549 if (do_div(dlane_bps, lanes * dpi_htotal))
570 unsigned int nlanes = output->dev->lanes;
714 DPHY_D_RSTB(output->dev->lanes) | DPHY_C_RSTB,
730 for (i = 1; i < output->dev->lanes; i++)
747 for (i = 0; i < output->dev->lanes;
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/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dgm200.c38 const u32 shift = sor->func->dp->lanes[ln] * 8;
59 .lanes = { 0, 1, 2, 3 },
/linux-master/drivers/net/ethernet/netronome/nfp/nfpcore/
H A Dnfp_nsp.h179 * @ports.lanes: number of channels
197 * @ports.port_lanes: total number of lanes on the port (sum of lanes of all
213 unsigned int lanes; member in struct:nfp_eth_table::nfp_eth_table_port
282 int __nfp_eth_set_split(struct nfp_nsp *nsp, unsigned int lanes);
H A Dnfp_nsp_eth.c146 dst->lanes = FIELD_GET(NSP_ETH_PORT_LANES, port);
153 dst->speed = dst->lanes * rate;
210 table->ports[i].port_lanes += table->ports[j].lanes;
429 * Enable or disable PHY module (this usually means setting the TX lanes
726 * by number of lanes this subport is spanning (i.e. 10000 for 40G, 25000 for
752 * @lanes: Desired lanes per port
754 * Set number of lanes in the port.
759 int __nfp_eth_set_split(struct nfp_nsp *nsp, unsigned int lanes) argument
762 lanes, NSP_ETH_CTRL_SET_LANE
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/linux-master/drivers/gpu/drm/bridge/imx/
H A Dimx93-mipi-dsi.c470 u32 lanes, u32 format)
483 lanes, &phy_cfg->mipi_dphy);
521 unsigned long mode_flags, u32 lanes, u32 format)
528 ret = imx93_dsi_get_phy_configure_opts(dsi, mode, &phy_cfg, lanes,
546 unsigned long mode_flags, u32 lanes, u32 format)
559 ret = imx93_dsi_validate_phy(dsi, mode, mode_flags, lanes, format);
678 unsigned long mode_flags, u32 lanes, u32 format,
686 ret = imx93_dsi_get_phy_configure_opts(dsi, mode, &phy_cfg, lanes,
467 imx93_dsi_get_phy_configure_opts(struct imx93_dsi *dsi, const struct drm_display_mode *mode, union phy_configure_opts *phy_cfg, u32 lanes, u32 format) argument
520 imx93_dsi_validate_phy(struct imx93_dsi *dsi, const struct drm_display_mode *mode, unsigned long mode_flags, u32 lanes, u32 format) argument
545 imx93_dsi_mode_valid(void *priv_data, const struct drm_display_mode *mode, unsigned long mode_flags, u32 lanes, u32 format) argument
677 imx93_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, unsigned long mode_flags, u32 lanes, u32 format, unsigned int *lane_mbps) argument
/linux-master/drivers/nubus/
H A Dnubus.c231 dir->mask = board->lanes;
241 dir->mask = fres->board->lanes;
253 dir->mask = board->lanes;
767 board->lanes = bytelanes;
786 board->lanes);
/linux-master/drivers/pci/controller/
H A Dpci-xgene.c310 u32 *lanes, u32 *speed)
320 *lanes = val32 >> 26;
566 u32 val, lanes = 0, speed = 0; local
583 xgene_pcie_linkup(port, &lanes, &speed);
587 dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1);
309 xgene_pcie_linkup(struct xgene_pcie *port, u32 *lanes, u32 *speed) argument

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