Searched refs:divider (Results 51 - 75 of 147) sorted by relevance

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/linux-master/drivers/clk/bcm/
H A Dclk-bcm2835.c494 /* Number of integer bits in the divider */
496 /* Number of fractional bits in the divider */
804 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); local
805 struct bcm2835_cprman *cprman = divider->cprman;
806 const struct bcm2835_pll_divider_data *data = divider->data;
825 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); local
826 struct bcm2835_cprman *cprman = divider->cprman;
827 const struct bcm2835_pll_divider_data *data = divider->data;
841 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); local
842 struct bcm2835_cprman *cprman = divider
861 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); local
883 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); local
1376 struct bcm2835_pll_divider *divider; local
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/linux-master/drivers/clk/ti/
H A DMakefile5 clk-common = dpll.o composite.o divider.o gate.o \
/linux-master/drivers/clk/ux500/
H A Dclk.h66 u8 source, u8 divider);
H A Du8500_of_clk.c77 u32 id, source, divider; local
85 divider = clkspec->args[2];
103 if (divider == 0 || divider > 63) {
104 pr_err("%s: invalid divider %d\n", __func__, divider);
108 pr_debug("registering clkout%d with source %d and divider %d\n",
109 id + 1, source, divider);
114 source, divider);
/linux-master/kernel/sched/
H A Dpelt.c259 u32 divider = get_pelt_divider(sa); local
264 sa->load_avg = div_u64(load * sa->load_sum, divider);
265 sa->runnable_avg = div_u64(sa->runnable_sum, divider);
266 WRITE_ONCE(sa->util_avg, sa->util_sum / divider);
H A Dpelt.h135 u32 divider = ((LOAD_AVG_MAX - 1024) << SCHED_CAPACITY_SHIFT) - LOAD_AVG_MAX; local
149 if (util_sum >= divider)
/linux-master/drivers/spi/
H A Dspi-xcomm.c79 unsigned int divider; local
81 divider = DIV_ROUND_UP(SPI_XCOMM_CLOCK, t->speed_hz);
82 if (divider >= 64)
84 else if (divider >= 16)
H A Dspi-orion.c160 /* best integer divider: */
161 unsigned divider = DIV_ROUND_UP(tclk_hz, speed); local
164 if (divider < 16) {
165 /* This is the easy case, divider is less than 16 */
166 spr = divider;
172 * Find the highest bit set in divider. This and the
177 sppr = fls(divider) - 4;
180 * As SPR only has 4 bits, we have to round divider up
184 divider = (divider
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/linux-master/drivers/iio/frequency/
H A Dadmv4420.c97 u32 divider; member in struct:admv4420_reference_block
216 return (tmp / (st->ref_block.divider * divide_by_2));
228 for (st->ref_block.divider = 1; st->ref_block.divider < MAX_R_DIVIDER;
229 st->ref_block.divider++) {
314 FIELD_GET(0xFF, st->ref_block.divider));
319 FIELD_GET(0xFF00, st->ref_block.divider));
/linux-master/drivers/clk/baikal-t1/
H A Dclk-ccu-div.c76 .divider = _divider \
95 .divider = _divider \
106 unsigned int divider; member in union:ccu_div_info::__anon91
374 init.divider = info->divider;
379 init.divider = info->divider;
385 pr_err("Couldn't register divider '%s' hw\n",
439 pr_err("Couldn't register divider '%s' reset controller\n",
/linux-master/drivers/iio/chemical/
H A Dsgp40.c104 u32 factorial, divider, xmax; local
120 divider = 0;
125 y += (xp >> divider) / factorial;
126 divider += power;
130 divider -= power;
/linux-master/drivers/clk/nxp/
H A Dclk-lpc32xx.c253 * divider register does not contain information about selected rate.
657 * and post-divider must be 4, this slightly simplifies calculation of
658 * USB divider, USB PLL N and M parameters.
663 /* USB divider clock */
674 /* Check if valid USB divider and USB PLL parameters exists */
946 struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw); local
949 regmap_read(clk_regmap, divider->reg, &val);
951 val >>= divider->shift;
952 val &= div_mask(divider->width);
954 return divider_recalc_rate(hw, parent_rate, val, divider
961 struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw); local
981 struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw); local
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/linux-master/drivers/clk/
H A Dclk-xgene.c429 void __iomem *divider_reg; /* CSR for divider */
430 u32 reg_divider_offset; /* Offset to divider register */
431 u32 reg_divider_shift; /* Bit shift to divider field */
432 u32 reg_divider_width; /* Width of the bit to divider field */
562 u32 divider; local
569 /* Let's compute the divider */
572 divider_save = divider = parent_rate / rate; /* Rounded down */
573 divider &= (1 << pclk->param.reg_divider_width) - 1;
574 divider <<= pclk->param.reg_divider_shift;
576 /* Set new divider */
601 u32 divider; local
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H A Dclk-cdce706.c84 struct cdce706_hw_data divider[6]; member in struct:cdce706_dev_data
284 "%s, divider: %d, div: %u\n",
354 "%s, divider: %d, div: %lu\n",
367 "%s, divider: %d, div: %u\n",
567 for (i = 0; i < ARRAY_SIZE(cdce->divider); ++i) {
573 cdce->divider[i].parent =
580 cdce->divider[i].div = val & CDCE706_DIVIDER_DIVIDER_MASK;
583 cdce->divider[i].parent, cdce->divider[i].div);
586 ret = cdce706_register_hw(cdce, cdce->divider,
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H A Dclk-axi-clkgen.c193 static void axi_clkgen_calc_clk_params(unsigned int divider, argument
199 if (divider == 1) {
205 params->high = divider / 2;
206 params->edge = divider % 2;
207 params->low = divider - params->high;
212 params->high = divider / 2;
213 params->edge = divider % 2;
224 (divider == 2 && frac_divider == 1))
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c73 uint32_t dentist_get_did_from_divider(int divider) argument
78 if (divider < DENTIST_DIVIDER_RANGE_2_START) {
79 if (divider < DENTIST_DIVIDER_RANGE_1_START)
83 + (divider - DENTIST_DIVIDER_RANGE_1_START)
85 } else if (divider < DENTIST_DIVIDER_RANGE_3_START) {
87 + (divider - DENTIST_DIVIDER_RANGE_2_START)
89 } else if (divider < DENTIST_DIVIDER_RANGE_4_START) {
91 + (divider - DENTIST_DIVIDER_RANGE_3_START)
95 + (divider - DENTIST_DIVIDER_RANGE_4_START)
150 /* When changing divider t
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/linux-master/drivers/media/dvb-frontends/
H A Dstv6110x.c111 u32 rDiv, divider; local
144 divider = (frequency * R_DIV(rDivOpt) * pVal) / REFCLOCK_kHz;
145 divider = (divider + 5) / 10;
148 STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_N_DIV_11_8, MSB(divider));
149 STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG0], TNG0_N_DIV_7_0, LSB(divider));
235 /* setup divider */
/linux-master/drivers/iio/adc/
H A Dstm32-dfsdm-core.c96 unsigned int spi_clk_out_div; /* SPI clkout divider value */
227 unsigned long clk_freq, divider; local
269 divider = div_u64_rem(clk_freq, spi_freq, &rem);
270 /* Round up divider when ckout isn't precise, not to exceed spi_freq */
272 divider++;
274 /* programmable divider is in range of [2:256] */
275 if (divider < 2 || divider > 256) {
280 /* SPI clock output divider is: divider
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/linux-master/drivers/clk/rockchip/
H A DMakefile11 clk-rockchip-y += clk-half-divider.o
/linux-master/drivers/iio/imu/inv_mpu6050/
H A Dinv_mpu_aux.c49 d = st->chip_config.divider;
59 regmap_write(st->map, st->reg->sample_rate_div, st->chip_config.divider);
H A Dinv_mpu_iio.h111 * @divider: chip sample rate divider (sample rate divider - 1)
126 u8 divider; member in struct:inv_mpu6050_chip_config
378 /* return the frequency divider (chip sample rate divider + 1) */
380 ((st)->chip_config.divider + 1)
381 /* chip sample rate divider to fifo rate */
384 #define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider) \
385 (INV_MPU6050_INTERNAL_FREQ_HZ / ((divider)
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/linux-master/drivers/mfd/
H A Dsm501.c392 int divider; member in struct:sm501_clock
411 int divider; local
416 try divider 5 for panel only.*/
418 for (divider = 1; divider <= max_div; divider += 2) {
422 diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq;
431 clock->divider = divider;
476 return clock->mclk / (clock->divider << cloc
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/linux-master/drivers/i2c/busses/
H A Di2c-mpc.c105 u16 divider; member in struct:mpc_i2c_divider
158 * 1. Set up the frequency divider and sampling rate.
244 u32 divider; local
253 /* Determine divider value */
254 divider = mpc5xxx_fwnode_get_bus_frequency(fwnode) / clock;
265 if (div->divider >= divider)
269 *real_clk = mpc5xxx_fwnode_get_bus_frequency(fwnode) / div->divider;
431 u32 divider; local
440 divider
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/linux-master/drivers/hwmon/
H A Dmlxreg-fan.c45 * RPM = 15000000 * 100 / ((Regval + samples) * divider).
103 * @divider: divider value for tachometer RPM calculation;
113 int divider; member in struct:mlxreg_fan
164 *val = MLXREG_FAN_GET_RPM(regval, fan->divider,
436 * Set divider value according to the capability register, in case it
442 fan->divider = regval * MLXREG_FAN_TACHO_DIV_MIN;
456 fan->divider = MLXREG_FAN_TACHO_DIV_DEF;
519 fan->divider = data->bit;
/linux-master/drivers/clk/sunxi/
H A Dclk-sunxi.c301 /* calculate pre-divider if parent is pll6 */
331 /* apply pre-divider first if parent is pll6 */
335 /* clk divider */
721 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
802 pr_err("%s: failed to register divider clock %s: %ld\n",
879 * itself. The remaining refer to fixed or configurable divider
954 struct clk_divider *divider; local
1059 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
1060 if (!divider)
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