#
58fdf74d |
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20-Jan-2021 |
Lee Jones <lee.jones@linaro.org> |
clk: sunxi: clk-sunxi: Demote a bunch of non-conformant kernel-doc headers Fixes the following W=1 kernel build warning(s): drivers/clk/sunxi/clk-sunxi.c:34: warning: Function parameter or member 'req' not described in 'sun4i_get_pll1_factors' drivers/clk/sunxi/clk-sunxi.c:81: warning: Function parameter or member 'req' not described in 'sun6i_a31_get_pll1_factors' drivers/clk/sunxi/clk-sunxi.c:158: warning: Function parameter or member 'req' not described in 'sun8i_a23_get_pll1_factors' drivers/clk/sunxi/clk-sunxi.c:202: warning: Function parameter or member 'req' not described in 'sun4i_get_pll5_factors' drivers/clk/sunxi/clk-sunxi.c:229: warning: Function parameter or member 'req' not described in 'sun6i_a31_get_pll6_factors' drivers/clk/sunxi/clk-sunxi.c:250: warning: Function parameter or member 'req' not described in 'sun5i_a13_get_ahb_factors' drivers/clk/sunxi/clk-sunxi.c:289: warning: Function parameter or member 'req' not described in 'sun6i_get_ahb1_factors' drivers/clk/sunxi/clk-sunxi.c:328: warning: Function parameter or member 'req' not described in 'sun6i_ahb1_recalc' drivers/clk/sunxi/clk-sunxi.c:346: warning: Function parameter or member 'req' not described in 'sun4i_get_apb1_factors' drivers/clk/sunxi/clk-sunxi.c:385: warning: Function parameter or member 'req' not described in 'sun7i_a20_get_out_factors' drivers/clk/sunxi/clk-sunxi.c:415: warning: cannot understand function prototype: 'const struct clk_factors_config sun4i_pll1_config = ' drivers/clk/sunxi/clk-sunxi.c:724: warning: cannot understand function prototype: 'struct div_data ' drivers/clk/sunxi/clk-sunxi.c:945: warning: Function parameter or member 'node' not described in 'sunxi_divs_clk_setup' drivers/clk/sunxi/clk-sunxi.c:945: warning: Function parameter or member 'data' not described in 'sunxi_divs_clk_setup' Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Maxime Ripard <mripard@kernel.org> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Jernej Skrabec <jernej.skrabec@siol.net> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210120093040.1719407-15-lee.jones@linaro.org
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#
ee25d974 |
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17-Mar-2020 |
Rikard Falkeborn <rikard.falkeborn@gmail.com> |
clk: sunxi: Fix incorrect usage of round_down() round_down() can only round to powers of 2. If round_down() is asked to round to something that is not a power of 2, incorrect results are produced. The incorrect results can be both too large and too small. Instead, use rounddown() which can round to any number. Fixes: 6a721db180a2 ("clk: sunxi: Add A31 clocks support") Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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#
afdc74ed |
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22-Oct-2019 |
Nathan Chancellor <nathan@kernel.org> |
clk: sunxi: Fix operator precedence in sunxi_divs_clk_setup r375326 in Clang exposes an issue with operator precedence in sunxi_div_clk_setup: drivers/clk/sunxi/clk-sunxi.c:1083:30: warning: operator '?:' has lower precedence than '|'; '|' will be evaluated first [-Wbitwise-conditional-parentheses] data->div[i].critical ? ~~~~~~~~~~~~~~~~~~~~~ ^ drivers/clk/sunxi/clk-sunxi.c:1083:30: note: place parentheses around the '|' expression to silence this warning data->div[i].critical ? ^ ) drivers/clk/sunxi/clk-sunxi.c:1083:30: note: place parentheses around the '?:' expression to evaluate it first data->div[i].critical ? ^ ( 1 warning generated. It appears that the intention was for ?: to be evaluated first so that CLK_IS_CRITICAL could be added to clkflags if the critical boolean was set; right now, | is being evaluated first. Add parentheses around the ?: block to have it be evaluated first. Fixes: 9919d44ff297 ("clk: sunxi: Use CLK_IS_CRITICAL flag for critical clks") Link: https://github.com/ClangBuiltLinux/linux/issues/745 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Maxime Ripard <mripard@kernel.org>
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#
c942fddf |
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27-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 Based on 3 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version [author] [kishon] [vijay] [abraham] [i] [kishon]@[ti] [com] this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version [author] [graeme] [gregory] [gg]@[slimlogic] [co] [uk] [author] [kishon] [vijay] [abraham] [i] [kishon]@[ti] [com] [based] [on] [twl6030]_[usb] [c] [author] [hema] [hk] [hemahk]@[ti] [com] this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 1105 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.202006027@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
fcdf445f |
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27-May-2019 |
Gen Zhang <blackgod016574@gmail.com> |
clk-sunxi: fix a missing-check bug in sunxi_divs_clk_setup() In sunxi_divs_clk_setup(), 'derived_name' is allocated by kstrndup(). It returns NULL when fails. 'derived_name' should be checked. Signed-off-by: Gen Zhang <blackgod016574@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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#
62e59c4e |
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18-Apr-2019 |
Stephen Boyd <sboyd@kernel.org> |
clk: Remove io.h from clk-provider.h Now that we've gotten rid of clk_readl() we can remove io.h from the clk-provider header and push out the io.h include to any code that isn't already including the io.h header but using things like readl/writel, etc. Found with this grep: git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \ xargs git grep -l \ -e '\<__iowrite32_copy\>' --or \ -e '\<__ioread32_copy\>' --or \ -e '\<__iowrite64_copy\>' --or \ -e '\<ioremap_page_range\>' --or \ -e '\<ioremap_huge_init\>' --or \ -e '\<arch_ioremap_pud_supported\>' --or \ -e '\<arch_ioremap_pmd_supported\>' --or \ -e '\<devm_ioport_map\>' --or \ -e '\<devm_ioport_unmap\>' --or \ -e '\<IOMEM_ERR_PTR\>' --or \ -e '\<devm_ioremap\>' --or \ -e '\<devm_ioremap_nocache\>' --or \ -e '\<devm_ioremap_wc\>' --or \ -e '\<devm_iounmap\>' --or \ -e '\<devm_ioremap_release\>' --or \ -e '\<devm_memremap\>' --or \ -e '\<devm_memunmap\>' --or \ -e '\<__devm_memremap_pages\>' --or \ -e '\<pci_remap_cfgspace\>' --or \ -e '\<arch_has_dev_port\>' --or \ -e '\<arch_phys_wc_add\>' --or \ -e '\<arch_phys_wc_del\>' --or \ -e '\<memremap\>' --or \ -e '\<memunmap\>' --or \ -e '\<arch_io_reserve_memtype_wc\>' --or \ -e '\<arch_io_free_memtype_wc\>' --or \ -e '\<__io_aw\>' --or \ -e '\<__io_pbw\>' --or \ -e '\<__io_paw\>' --or \ -e '\<__io_pbr\>' --or \ -e '\<__io_par\>' --or \ -e '\<__raw_readb\>' --or \ -e '\<__raw_readw\>' --or \ -e '\<__raw_readl\>' --or \ -e '\<__raw_readq\>' --or \ -e '\<__raw_writeb\>' --or \ -e '\<__raw_writew\>' --or \ -e '\<__raw_writel\>' --or \ -e '\<__raw_writeq\>' --or \ -e '\<readb\>' --or \ -e '\<readw\>' --or \ -e '\<readl\>' --or \ -e '\<readq\>' --or \ -e '\<writeb\>' --or \ -e '\<writew\>' --or \ -e '\<writel\>' --or \ -e '\<writeq\>' --or \ -e '\<readb_relaxed\>' --or \ -e '\<readw_relaxed\>' --or \ -e '\<readl_relaxed\>' --or \ -e '\<readq_relaxed\>' --or \ -e '\<writeb_relaxed\>' --or \ -e '\<writew_relaxed\>' --or \ -e '\<writel_relaxed\>' --or \ -e '\<writeq_relaxed\>' --or \ -e '\<readsb\>' --or \ -e '\<readsw\>' --or \ -e '\<readsl\>' --or \ -e '\<readsq\>' --or \ -e '\<writesb\>' --or \ -e '\<writesw\>' --or \ -e '\<writesl\>' --or \ -e '\<writesq\>' --or \ -e '\<inb\>' --or \ -e '\<inw\>' --or \ -e '\<inl\>' --or \ -e '\<outb\>' --or \ -e '\<outw\>' --or \ -e '\<outl\>' --or \ -e '\<inb_p\>' --or \ -e '\<inw_p\>' --or \ -e '\<inl_p\>' --or \ -e '\<outb_p\>' --or \ -e '\<outw_p\>' --or \ -e '\<outl_p\>' --or \ -e '\<insb\>' --or \ -e '\<insw\>' --or \ -e '\<insl\>' --or \ -e '\<outsb\>' --or \ -e '\<outsw\>' --or \ -e '\<outsl\>' --or \ -e '\<insb_p\>' --or \ -e '\<insw_p\>' --or \ -e '\<insl_p\>' --or \ -e '\<outsb_p\>' --or \ -e '\<outsw_p\>' --or \ -e '\<outsl_p\>' --or \ -e '\<ioread8\>' --or \ -e '\<ioread16\>' --or \ -e '\<ioread32\>' --or \ -e '\<ioread64\>' --or \ -e '\<iowrite8\>' --or \ -e '\<iowrite16\>' --or \ -e '\<iowrite32\>' --or \ -e '\<iowrite64\>' --or \ -e '\<ioread16be\>' --or \ -e '\<ioread32be\>' --or \ -e '\<ioread64be\>' --or \ -e '\<iowrite16be\>' --or \ -e '\<iowrite32be\>' --or \ -e '\<iowrite64be\>' --or \ -e '\<ioread8_rep\>' --or \ -e '\<ioread16_rep\>' --or \ -e '\<ioread32_rep\>' --or \ -e '\<ioread64_rep\>' --or \ -e '\<iowrite8_rep\>' --or \ -e '\<iowrite16_rep\>' --or \ -e '\<iowrite32_rep\>' --or \ -e '\<iowrite64_rep\>' --or \ -e '\<__io_virt\>' --or \ -e '\<pci_iounmap\>' --or \ -e '\<virt_to_phys\>' --or \ -e '\<phys_to_virt\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap\>' --or \ -e '\<__ioremap\>' --or \ -e '\<iounmap\>' --or \ -e '\<ioremap\>' --or \ -e '\<ioremap_nocache\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wt\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<xlate_dev_kmem_ptr\>' --or \ -e '\<xlate_dev_mem_ptr\>' --or \ -e '\<unxlate_dev_mem_ptr\>' --or \ -e '\<virt_to_bus\>' --or \ -e '\<bus_to_virt\>' --or \ -e '\<memset_io\>' --or \ -e '\<memcpy_fromio\>' --or \ -e '\<memcpy_toio\>' I also reordered a couple includes when they weren't alphabetical and removed clk.h from kona, replacing it with clk-provider.h because that driver doesn't use clk consumer APIs. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Cc: Chris Zankel <chris@zankel.net> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: John Crispin <john@phrozen.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
e665f029 |
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28-Aug-2018 |
Rob Herring <robh@kernel.org> |
clk: Convert to using %pOFn instead of device_node.name In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier. Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-omap@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
9919d44f |
|
02-Jan-2018 |
Stephen Boyd <sboyd@codeaurora.org> |
clk: sunxi: Use CLK_IS_CRITICAL flag for critical clks We'd like to privatize __clk_get(), but the sunxi clk driver is calling this function to keep a reference held on the clk and call clk_prepare_enable() on it. We support this design in the clk core now with the CLK_IS_CRITICAL flag, so let's just use that instead. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
16673931 |
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18-Jul-2017 |
Rob Herring <robh@kernel.org> |
clk: Convert to using %pOF instead of full_name Now that we have a custom printf format specifier, convert users of full_name to use %pOF instead. This is preparation to remove storing of the full path string for each node. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-tegra@vger.kernel.org Cc: linux-omap@vger.kernel.org Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
ac95330b |
|
03-Nov-2016 |
Stéphan Rafin <stephan@soliotek.com> |
clk: sunxi: Fix M factor computation for APB1 commit cfa636886033 ("clk: sunxi: factors: Consolidate get_factors parameters into a struct") introduced a regression for m factor computation in sun4i_get_apb1_factors function. The old code reassigned the "parent_rate" parameter to the targeted divisor value and was buggy for the returned frequency but not for the computed factors. Now, returned frequency is good but m factor is incorrectly computed (its max value 31 is always set resulting in a significantly slower frequency than the requested one...) This patch simply restores the original proper computation for m while keeping the good changes for returned rate. Fixes: cfa636886033 ("clk: sunxi: factors: Consolidate get_factors parameters into a struct") Signed-off-by: Stéphan Rafin <stephan@soliotek.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
ff2bb893 |
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18-Mar-2016 |
Jens Kuske <jenskuske@gmail.com> |
clk: sunxi: Let divs clocks read the base factor clock name from devicetree Currently, the sunxi clock driver gets the name for the base factor clock of divs clocks from the name field in factors_data. This prevents reusing of the factor clock for clocks with same properties, but different name. This commit makes the divs setup function try to get a name from clock-output-names in the devicetree. It also removes the name field where possible and merges the sun4i PLL5 and PLL6 clocks. [Andre: Make temporary name allocation dynamic.] Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
5ed400dd |
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30-Mar-2016 |
Jean-Francois Moine <moinejf@free.fr> |
clk: sunxi: Add sun6i/8i display support Add the clock type which is used by the sun6i/8i families for video display. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
d331328d |
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16-Feb-2016 |
Andre Przywara <andre.przywara@arm.com> |
clk: sunxi: Improve divs_clk error handling and reporting We catch errors in the base clock registration, failure to ioremap and failures in the final of_clk_add_provider() call. Also we unmap the registers when we need to rollback. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
b26803eb |
|
16-Feb-2016 |
Andre Przywara <andre.przywara@arm.com> |
clk: sunxi: improve divider_clk error handling and reporting We now report a failing ioremap, failing output names parsing, failures in table registration and in the final step. Also there was a bug where clk_register_divider_table() would return an ERR_PTR value instead of NULL, which we were checking for. We now implement proper rollback in case of an error. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
72360b91 |
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16-Feb-2016 |
Andre Przywara <andre.przywara@arm.com> |
clk: sunxi: improve mux_clk error handling and reporting We now catch and report a failing ioremap, also a failure in the final step of the clock registration is now handled and reported. Also warnings are turned into errors. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
b0b6413f |
|
02-Feb-2016 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Remove clk_register_clkdev calls Now that our protection code doesn't use the global name lookup anymore, we can remove the clkdev registrations. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
3a4d9af4 |
|
02-Feb-2016 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Remove old probe and protection code Now that we don't have any user left for the old registration code, we can remove it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
c0872308 |
|
02-Feb-2016 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: convert current clocks registration to CLK_OF_DECLARE The current clock registration and protection code has a few drawbacks, the two main ones being that we create a lot of orphans clock in the registration phase, which will be troublesome when we will start being less relaxed about them. The protection code also relies on clkdev, which we don't really use but for this particular case. Fix both at the same time by moving everyone to the CLK_OF_DECLARE that will probe our clock tree in the right and thus avoid orphans, and by protecting directly the clock returned by our registration function. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
5b5226d1 |
|
02-Feb-2016 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Make clocks setup functions take const pointer All the data structure that we pass to the clocks setup functions are declared const, while our setup functions expects a regular pointer. This was hidden by the fact that we cast a void * pointer back to these structures, which made it go unnoticed. Fix the functions prototype. Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
96f185ac |
|
02-Feb-2016 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Make clocks setup functions return their clock The clocks registration code in clk-sunxi was most of the time not returning the struct clk (or struct clk array) that was registered, preventing the users of such functions to manipulate it, for example to protect it. Make them return it so that we can start using it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
d221b7a8 |
|
01-Feb-2016 |
Andre Przywara <andre.przywara@arm.com> |
clk: sunxi: improve error reporting for the mux clock clk_register_mux returns a pointer wrapped error value in case of failure, so a simple NULL check is not sufficient to catch errors. Fix that and elaborate on the failure reason on the way. The whole function does not return any error value, so silently failing may leave users scratching their heads because the kernel does not provide any clues on what's wrong. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
a78bb355 |
|
25-Jan-2016 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: rewrite sun6i-a31-ahb1-clk using factors clk with custom recalc The factors clk implementation has been extended to support custom recalc callbacks to support clocks that use one factor for certain parents only, like a pre-divider. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
cfa63688 |
|
25-Jan-2016 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: factors: Consolidate get_factors parameters into a struct The .get_factors callback of factors_clk has 6 parameters. To extend factors_clk in any way that requires adding parameters to .get_factors would make that list even longer, not to mention changing all the function declarations. Do this once now and consolidate all the parameters into a struct. Also drop the space before function pointer arguments, since checkpatch complains. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
b3e919e0 |
|
25-Jan-2016 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: factors: Make struct clk_factors_config table const struct clk_factors_config contains shifts/widths for the factors of the factors clk. This is used to read out the factors from the register value. In no case is it written to, so make it const. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
ab6e23a4 |
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04-Dec-2015 |
Jens Kuske <jenskuske@gmail.com> |
clk: sunxi: Add H3 clocks support The H3 clock control unit is similar to the those of other sun8i family members like the A23. It adds a new bus gates clock similar to the simple gates, but with a different parent clock for each single gate. Some of the gates use the new AHB2 clock as parent, whose clock source is muxable between AHB1 and PLL6/2. The documentation isn't totally clear about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it is mostly based on Allwinner kernel source code. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
bef6229f |
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09-Jun-2015 |
Maxime Ripard <mripard@kernel.org> |
ARM: sunxi: Add R8 support The R8 is a new Allwinner SoC based on the A13. While both are very similar, there's still a few differences. Introduce a new compatible to deal with them. In order to have a consistent naming, instead of mentioning the Allwinner A series as the machine name, switch to sun4i/sun5i like what is done for the other families. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
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#
1b14afa6 |
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30-Jul-2015 |
Stephen Boyd <sboyd@codeaurora.org> |
clk: sunxi: Convert to clk_hw based provider APIs We're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs. Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: "Emilio López" <emilio@elopez.com.ar> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
98d8a60e |
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29-Jun-2015 |
Stephen Boyd <sboyd@codeaurora.org> |
clk: Convert __clk_get_flags() to clk_hw_get_flags() Mostly converted with the following snippet: @@ struct clk_hw *E; @@ -__clk_get_flags(E->clk) +clk_hw_get_flags(E) Acked-by: Tero Kristo <t-kristo@ti.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Daniel Thompson <daniel.thompson@linaro.org> Cc: Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
497295af |
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25-Jun-2015 |
Stephen Boyd <sboyd@codeaurora.org> |
clk: Replace __clk_get_num_parents with clk_hw_get_num_parents() Mostly converted with the following semantic patch: @@ struct clk_hw *E; @@ -__clk_get_num_parents(E->clk) +clk_hw_get_num_parents(E) Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Chao Xie <chao.xie@marvell.com> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: "Emilio López" <emilio@elopez.com.ar> Acked-by: Tero Kristo <t-kristo@ti.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
ee38b269 |
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31-Jul-2015 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Add a simple gates driver The gates were handled with a common piece of framework that was registering all gates array, that was not using the CLK_OF_DECLARE logic, and was not using clock-indices but some private masks that were pretty much equivalent. Move this code in a new driver that handles all the gates array and solves both these issues. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> [sboyd@codeaurora.org: Include clk.h for consumer API usage] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
8a53fb2b |
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06-Jul-2015 |
Dinh Nguyen <dinguyen@opensource.altera.com> |
clk: sunxi: make use of of_clk_parent_fill helper function Use of_clk_parent_fill to fill in the parent clock names' array. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: "Emilio López" <emilio@elopez.com.ar> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
57d866e6 |
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09-Jul-2015 |
Boris Brezillon <bbrezillon@kernel.org> |
clk: fix some determine_rate implementations Some determine_rate implementations are not returning an error when they failed to adapt the rate according to the rate request. Fix them so that they return an error instead of silently returning 0. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Jonathan Corbet <corbet@lwn.net> CC: Tony Lindgren <tony@atomide.com> CC: Ralf Baechle <ralf@linux-mips.org> CC: "Emilio López" <emilio@elopez.com.ar> CC: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Tero Kristo <t-kristo@ti.com> CC: Peter De Schrijver <pdeschrijver@nvidia.com> CC: Prashant Gaikwad <pgaikwad@nvidia.com> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Thierry Reding <thierry.reding@gmail.com> CC: Alexandre Courbot <gnurou@gmail.com> CC: linux-doc@vger.kernel.org CC: linux-kernel@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org CC: linux-omap@vger.kernel.org CC: linux-mips@linux-mips.org CC: linux-tegra@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
0817b62c |
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07-Jul-2015 |
Boris Brezillon <bbrezillon@kernel.org> |
clk: change clk_ops' ->determine_rate() prototype Clock rates are stored in an unsigned long field, but ->determine_rate() (which returns a rounded rate from a requested one) returns a long value (errors are reported using negative error codes), which can lead to long overflow if the clock rate exceed 2Ghz. Change ->determine_rate() prototype to return 0 or an error code, and pass a pointer to a clk_rate_request structure containing the expected target rate and the rate constraints imposed by clk users. The clk_rate_request structure might be extended in the future to contain other kind of constraints like the rounding policy, the maximum clock inaccuracy or other things that are not yet supported by the CCF (power consumption constraints ?). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Jonathan Corbet <corbet@lwn.net> CC: Tony Lindgren <tony@atomide.com> CC: Ralf Baechle <ralf@linux-mips.org> CC: "Emilio López" <emilio@elopez.com.ar> CC: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Tero Kristo <t-kristo@ti.com> CC: Peter De Schrijver <pdeschrijver@nvidia.com> CC: Prashant Gaikwad <pgaikwad@nvidia.com> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Thierry Reding <thierry.reding@gmail.com> CC: Alexandre Courbot <gnurou@gmail.com> CC: linux-doc@vger.kernel.org CC: linux-kernel@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org CC: linux-omap@vger.kernel.org CC: linux-mips@linux-mips.org CC: linux-tegra@vger.kernel.org [sboyd@codeaurora.org: Fix parent dereference problem in __clk_determine_rate()] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Romain Perier <romain.perier@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> [sboyd@codeaurora.org: Folded in fix from Heiko for fixed-rate clocks without parents or a rate determining op] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
9dfefe8c |
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19-Jun-2015 |
Stephen Boyd <sboyd@codeaurora.org> |
clk: sunxi: Include clk.h and remove unused clkdev.h includes This clock provider uses the consumer API, so include clk.h explicitly. Also remove clkdev.h in files that aren't using it and include slab.h when clkdev.h was being used to implicitly include it. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
159870d2 |
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30-May-2015 |
Vishnu Patekar <vishnupatekar0510@gmail.com> |
ARM: sunxi: Add Machine support for A33 Add machine support for the Allwinner A33 quad core cortex-a7 based SoC, which is similar to the A23 SoC. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Chen-Yu Tsai <wens@csie.org>
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#
5ac382c3 |
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02-May-2015 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Fix of_io_request_and_map error check of_io_request_and map returns an error pointer, but the current code assumes that on error the returned pointer will be NULL. Obviously, that makes the check completely useless. Change the test to actually check for the proper error code. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org
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#
f1017969 |
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24-Mar-2015 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6 The pll6 has a /4 output that is used as an input to the ahb mux clock. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
934fe5f4 |
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24-Mar-2015 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: Make divs clocks specify which output is the base factor clock The current sunxi clock driver has the base factor clock of divs clocks as the last clock output of the clock node. This makes it rather difficult to add new outputs, such as fixed dividers, which were previously unknown. This patch makes the divs clocks data structure specify which output is the factor clock, and updates all current divs clocks accordingly. We can then add new outputs after the factor clocks, at least not breaking backward compatibility with regards to the devicetree bindings. Also replace kzalloc with kcalloc in sunxi_divs_clk_setup(). Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
b712a623 |
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19-Mar-2015 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: Register divs clocks before factor clocks We want to reparent AHB clock to PLL6 on sun5i/sun7i using the assigned clocks properties. AHB is a factor clock, while PLL6 is a divs clock. Register divs clocks before factor clocks so reparenting works. This is only needed because we do the reparenting on the clock provider. The proper way to fix this is to split out all the old sunxi clocks into separate CLK_OF_DECLARE statements, like we are doing for sun9i. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
946fd40f |
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19-Mar-2015 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: Add "cpu" to list of protected clocks for sun5i Now that the ahb clock on sun5i/sun7i is muxable, ahb is no longer guaranteed to be a child of the cpu clock. Add the cpu clock to the list of protected clocks so it doesn't get disabled. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
9f243097 |
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19-Mar-2015 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: Add muxable ahb factors clock for sun5i and sun7i The AHB clock on sun5i and sun7i are muxable divider clocks. Use a factors clock to support them. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
6089ef19 |
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27-Jan-2015 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: Move USB clocks to separate file The USB clocks originally shared code with the gates clocks, but had additional reset controllers. Move these to a separate file. This will allow us to add new support for slightly different USB clocks, such as on the A80, without affecting gates clocks, and also facilitate the migration of gates clocks to a generic solution. This also cleans up the USB clocks code slightly, such as adding newlines, getting rid of the unused clkdev call, using a simple u32 instead of BITMAP for the clock masks, using BIT() macro to declare the clock bitmasks, and using of_io_request_and_map() to get the I/O address. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
1c8e6004 |
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22-Jan-2015 |
Tomeu Vizoso <tomeu.vizoso@collabora.com> |
clk: Add rate constraints to clocks Adds a way for clock consumers to set maximum and minimum rates. This can be used for thermal drivers to set minimum rates, or by misc. drivers to set maximum rates to assure a minimum performance level. Changes the signature of the determine_rate callback by adding the parameters min_rate and max_rate. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [sboyd@codeaurora.org: set req_rate in __clk_init] Signed-off-by: Michael Turquette <mturquette@linaro.org> [mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate migrated clk-private.h changes to clk.c]
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#
76820fcf |
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23-Jan-2015 |
Hans de Goede <hdegoede@redhat.com> |
sunxi: clk: Set sun6i-pll1 n_start = 1 For all pll-s on sun6i n == 0 means use a multiplier of 1, rather then 0 as it means on sun4i / sun5i / sun7i. n_start = 1 is already correctly set for sun6i pll6, but was missing for pll1, this commit fixes this. Cc: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
a7d19057 |
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11-Jul-2014 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Remove custom phase function Now that we don't have any user left for our custom phase function, we can safely remove this hack from the code. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Chen-Yu Tsai <wens@csie.org>
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#
3ec72fab |
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05-Jan-2015 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: Propagate rate changes to parent for mux clocks The cpu clock on sunxi machines is just a mux clock, which is normally fed by the main PLL, but can be muxed to the main or low power oscillator. Make the mux clock propagate rate changes to its parent, so we can change the clock rate of the PLL, and thus actually implement rate changing on the cpu clock. This patch also removes the no reparenting limit. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
b0f2faa5 |
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17-Dec-2014 |
Hans de Goede <hdegoede@redhat.com> |
ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxi So far the A31s is 100% compatible with the A31, still lets do the same as what we've done for the A13 / A10s and give it its own compatible string, in case we need to differentiate later. Signed-off-by: Hans de Goede <hdegoede@redhat.com> [Maxime: Removed unusude CPU_OF_DECLARE_METHOD] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
7c74c220 |
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23-Nov-2014 |
Hans de Goede <hdegoede@redhat.com> |
clk: sunxi: Give sunxi_factors_register a registers parameter Before this commit sunxi_factors_register uses of_iomap(node, 0) to get the clk registers. The sun6i prcm has factor clocks, for which we want to use sunxi_factors_register, but of_iomap(node, 0) does not work for the prcm factor clocks, because the prcm uses the mfd framework, so the registers are not part of the dt-node, instead they are added to the platform_device, as platform_device resources. This commit makes getting the registers the callers duty, so that sunxi_factors_register can be used with mfd instantiated platform device too. While at it also add error checking to the of_iomap calls. This commit also drops the __init function from sunxi_factors_register since platform driver probe functions are not __init. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
7954dfae |
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26-Nov-2014 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider This patch unifies the sun6i AHB1 clock, originally supported with separate mux and divider clks. It also adds support for the pre-divider on the PLL6 input, thus allowing the clock to be muxed to PLL6 with proper clock rate calculation. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
75bd2ec1 |
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24-Nov-2014 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: Remove ahb1_sdram from sun6i/sun8i protected clocks list The ahb1_sdram clock gate is only used for accessing the sdram controller's registers over the bus. It is not used for actually clock the controller or the dram, hence it does not need to be protected. This also gets rid of the problem when the protected ahb1_sdram gate is prepared/enabled while it is still an orphan, and the operation is not propagated to the correct parent. This was confirmed on my A23 tablet and my A31 Hummingbird. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
95e94c1f |
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12-Nov-2014 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output Some clock modules on the A31 use PLL6x2 as one of their inputs. This patch changes the PLL6 implementation for A31 to a divs clock, i.e. clock with multiple outputs that have different dividers. The first output will be the normal PLL6 output, and the second will be PLL6x2. This patch fixes the PLL6 N factor in the clock driver, and removes any /2 dividers in the PLL6 factors clock part. The N factor counts from 1 to 32, mapping to values 0 to 31, as shown in the A31 manual. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
13d52f61 |
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12-Nov-2014 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: Specify number of child clocks for divs clocks Currently sunxi_divs_clk_setup assumes the number of child clocks to be the same as the number of clock-output-names, and a maximum of SUNXI_DIVS_MAX_QTY child clocks. On sun6i, PLL6 only has 1 child clock, but the parent would be used as well, thereby also having it's own clock-output-names entry. This results in an extra bogus clock being registered. This patch adds an entry for the number of child clocks alongside the data structures for them. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
eaa2e980 |
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05-Nov-2014 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: Removed unused/incorrect sun6i-a31-apb2-clk driver This driver does not match the hardware, which is actually compatible to sun4i-a10-apb1-clk. Since we've switch to the correct one, drop this driver. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
93746e70 |
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05-Nov-2014 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: unify APB1 clock This commit unifies the APB1 mux with the APB1 clock, using the new factors infrastructure. Signed-off-by: Emilio López <emilio@elopez.com.ar> [wens@csie.org: Add mux mask bits] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
0b0f0802 |
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20-Oct-2014 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: Add support for bus clock gates on Allwinner A80 SoC This adds the gate clocks for AHB/APB busses on the A80 SoC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
e94f8cb3 |
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20-Oct-2014 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: make factors clock mux mask configurable Some of the factors-style clocks on the A80 have different widths for the mux values in the registers. Add a .muxmask field to clk_factors_config to make it configurable. Passing a bitmask instead of a width parameter will allow reuse in case we support table-based muxes in the future. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
eaa18f5d |
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10-Jul-2014 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Move mbus to mod0 file Move the MBUS clock to the module clocks file. It's pretty trivial, but still requires to enable the clocks to make sure it won't get disabled. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
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#
992a56e4 |
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10-Jul-2014 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Move mod0 clock to a file of its own Since we know have the ability to declare factors clock outside of clk-sunxi, create a new mod0 driver to deal with the mod0 clocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
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#
03e29bbf |
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10-Jul-2014 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Introduce mbus compatible Even though the mbus clock is a regular module clock, given its nature, it needs to be enabled all the time. Introduce a new compatible, to differentiate it from the other module clocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
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#
601da9d0 |
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04-Jul-2014 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: factors: Invert the probing logic Until now, the factors clock probing was done directly by sunxi_init_clocks, with the factors registration being called directly with the clocks data passed as an argument. This approch has shown its limits when we added more clocks, since we couldn't really split code with such a logic in smaller files, and led to a huge file having all the clocks. Introduce an intermediate probing function, so that factor clocks will be able to directly be called by CLK_OF_DECLARE, which will in turn ease the split into several files. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
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#
cfe4c93b |
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06-Sep-2014 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: add correct divider table for sun4i-apb0 clock The sun4i-apb0 clock, as found on all platforms using it, is a power-of-two-based divider clock, with a special divider of 2 for value 0. This was causing the clock framework to incorrectly calculate the clock rate for apb1 and related modules on sun6i and sun8i. On sun[4/5/7]i, u-boot SPL configures the divider with value 1 for /2 divider, so no suprises there. This patch adds a proper divider table for it, so the correct clock rate can be calculated. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
89a9456d |
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27-Jul-2014 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: add __iomem markings to MMIO pointers This commit adds __iomem thoughout the sunxi clock driver, in places where it was ommited. This cleans most of the sparse warnings we are getting here. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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#
515c1a4b |
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26-Jun-2014 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: Add A23 clocks support The clock control unit on the A23 is similar to the one found on the A31. The AHB1, APB1, APB2 gates on the A23 are almost identical to the ones on the A31, but some outputs are missing. The main CPU PLL (PLL1) however is like that on older Allwinner SoCs, such as the A10 or A20, but the N factor starts from 1 instead of 0. This patch adds support for PLL1 and all the basic clock muxes and gates. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
ea5671bf |
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26-Jun-2014 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: Add support for table-based divider clocks A few of the clock modules have odd dividers, such as the 2 lowest dividers being the same (2), or have the same divider when the highest bit is set. This patch adds support for optional divider tables, so the clock framework will know about the odd values. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
70eab199 |
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26-Jun-2014 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: move "ahb_sdram" to protected clock list With sunxi_gates clocks registered with clkdev, we can use the protected clocks list to enable the "ahb_sdram" clock, instead of looking for it and adding CLK_IGNORE_UNUSED inline in the clock setup code. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
d14e4705 |
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26-Jun-2014 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: register clock gates with clkdev The new important clock protect code requires the clocks be registered with clkdev. This was missing for sunxi_gates type clocks. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
efb3184c |
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09-May-2014 |
Maxime Ripard <mripard@kernel.org> |
clk: sun6i: Protect SDRAM gating bit Prevent the SDRAM controller from being gated by force-enabling it in the machine code. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
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#
2df73f40 |
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09-May-2014 |
Maxime Ripard <mripard@kernel.org> |
clk: sun6i: Protect CPU clock Right now, AHB is an indirect child clock of the CPU clock. If that happens to change, since the CPU clock has no other consumers declared in Linux, it would be shut down, which is not really a good idea. Prevent this by forcing it enabled. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
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#
134a6690 |
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09-May-2014 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Rework clock protection code Since we start to have a lot of clocks to protect, some of them in a few SoCs only, it becomes difficult to handle the clock protection without having to add per machine exceptions. Add per-SoC data to tell which clock to leave enabled. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
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#
59cb10e3 |
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09-May-2014 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Move the GMAC clock to a file of its own Since we have a folder of our own, we can actually make use of it by splitting the huge clock file into several sub drivers. The gmac clock is pretty easy to deal with, since it's pretty much isolated and doesn't have any dependency on the other clocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
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#
ff01df28 |
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09-May-2014 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Move the 24M oscillator to a file of its own Since we have a folder of our own, we can actually make use of it by splitting the huge clock file into several sub drivers. The main oscillator is pretty easy to deal with, since it's pretty much isolated. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
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#
2c6fba10 |
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09-May-2014 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Remove calls to clk_put Callers of clk_put must disable the clock first. This also means that as long as the clock is enabled the driver should hold a reference to that clock. Hence, the call to clk_put here are bogus and should be removed. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
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#
e0e7943c |
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13-May-2014 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Implement A31 USB clock The A31 USB clock slightly differ from its older counterparts, mostly because it has a different gate for each PHY, while the older one had a single gate for all the phy. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
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#
83221923 |
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12-May-2014 |
Rob Herring <robh@kernel.org> |
clk: sunxi: fix function type for CLK_OF_DECLARE Adding function type checking to CLK_OF_DECLARE found a type mismatch with sunxi_init_clocks. The function takes a single struct device_node parameter. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Mike Turquette <mturquette@linaro.org> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
cb7d5f42 |
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12-May-2014 |
Rob Herring <robh@kernel.org> |
clk: sunxi: avoid double DT matching Use for_each_matching_node_and_match instead of for_each_matching_node plus of_match_node to avoid searching the DT twice for each node. The sunxi DT scanning code should really be re-worked rather than have its own private matching infrastructure. It is working around needing a function pointer and a data pointer for each compatible match. Signed-off-by: Rob Herring <robh@kernel.org> Cc: "Emilio López" <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
a97181ad |
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12-May-2014 |
Hans de Goede <hdegoede@redhat.com> |
clk: sunxi: Fixup clk_sunxi_mmc_phase_control to take a clk rather then a hw_clk __clk_get_hw is supposed to be used by clk providers, not clk consumers. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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#
95713978 |
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02-May-2014 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: Implement MMC phase control HdG: add header exporting clk_sunxi_mmc_phase_control Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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#
9ce71ca1 |
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19-Mar-2014 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: fix thinko in comment This should read MOD0 and not MMC; MMC is just one example of a MOD0 clock. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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#
22260139 |
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19-Mar-2014 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: fix some calculations Some divisor calculations were misrounded, causing higher than requested rates on some clocks. Fix them up using DIV_ROUND_UP, and replace one homebrew instance of it as well with the right macro. Reported-by: Boris BREZILLON <b.brezillon.dev@gmail.com> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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#
5a8ddf26 |
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19-Mar-2014 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: fix A20 PLL4 calculation Allwinner actually reworked the PLL4 on A20; now it's compatible with the sun4i PLL5/6 design previous to any divisions, as well as to the new PLL8 in sun7i. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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#
fd1b22f6 |
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06-Feb-2014 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Add new clock compatibles The Allwinner A10 compatibles were following a slightly different compatible patterns than the rest of the SoCs for historical reasons. Add compatibles matching the other pattern to the clock driver for consistency, and keep the older one for backward compatibility. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
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#
e4c6d6c1 |
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10-Feb-2014 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: Add Allwinner A20/A31 GMAC clock unit The Allwinner A20/A31 clock module controls the transmit clock source and interface type of the GMAC ethernet controller. Model this as a single clock for GMAC drivers to use. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
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#
92ef67c5 |
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05-Feb-2014 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Add support for PLL6 on the A31 The A31 has a slightly different PLL6 clock. Add support for this new clock in our driver. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
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#
5abdbf2f |
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07-Feb-2014 |
Roman Byshko <rbyshko@gmail.com> |
clk: sunxi: Add USB clock register defintions Add register definitions for the usb-clk register found on sun4i, sun5i and sun7i SoCs. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
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#
cfb0086d |
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07-Feb-2014 |
Hans de Goede <hdegoede@redhat.com> |
clk: sunxi: Add support for USB clock-register reset bits The usb-clk register is special in that it not only contains clk gate bits, but also has a few reset bits. This commit adds support for this by allowing gates type sunxi clks to also register a reset controller. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
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#
97e36b3c |
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02-Feb-2014 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: get divs parent clock name from parent factor clock Divs clocks consist of a parent factor clock with multiple outputs, and seperate clocks for each output. Get the name of the parent clock from the parent factor clock, instead of the DT node name. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
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#
667f542d |
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02-Feb-2014 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: add names for pll5, pll6 parent clocks to factors_data Some factor clocks, such as the parent clock of pll5 and pll6, have multiple output names. Add the corresponding names to factors_data tied to compatible string. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
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#
f64111eb |
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02-Feb-2014 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: add clock-output-names dt property support sunxi clock drivers use dt node name as clock name, but clock nodes should be named clk@X, so the names would be the same. Let the drivers read clock names from dt clock-output-names property. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
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#
d1933689 |
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24-Jan-2014 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: fix overflow when setting up divided factors Currently, we are allocating space for two pointers, when we actually may need to store three of them (two divisors plus the original clock). Fix this, and change sizeof(type) to sizeof(*var) to keep checkpatch.pl happy. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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#
6f863417 |
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24-Dec-2013 |
Chen-Yu Tsai <wens@csie.org> |
clk: sunxi: Allwinner A20 output clock support This patch adds support for the external clock outputs on the Allwinner A20 SoC. The clock outputs are similar to "module 0" type clocks, with different offsets and widths for clock factors. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Emilio López <emilio@elopez.com.ar>
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#
76192dc8 |
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22-Dec-2013 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: support better factor DT nodes The DT nodes should look like abc_clk: clk@deadbeef { ... clock-output-names = "abc"; } But our old DT nodes look like abc: abc@deadbeef { ... } So, let's support both formats, until we can transition everything to the new, correct one. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org>
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#
7551769a |
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22-Dec-2013 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: mod0 support This commit implements support for the "module 0" type of clocks, as used by MMC, IR, NAND, SATA and other components. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org>
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#
d584c133 |
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22-Dec-2013 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: add PLL5 and PLL6 support This commit implements PLL5 and PLL6 support on the sunxi clock driver. These PLLs use a similar factor clock, but differ on their outputs. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org>
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#
5f4e0be3 |
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22-Dec-2013 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: make factors_clk_setup return the clock it registers We will be needing this to register a factor clock as parent with leaf divisors on a single call. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org>
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d838ff33 |
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22-Dec-2013 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: add gating support to PLL1 This commit adds gating support to PLL1 on the clock driver. This makes the PLL1 implementation fully compatible with PLL4 as well. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org>
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#
edaf3fb5 |
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22-Dec-2013 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: clean the magic number of mux parents This was pointed out during the review of the factor patches. Let's indicate what does that magic 5 mean. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org>
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40a5dcba |
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22-Dec-2013 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: register factors clocks behind composite This commit reworks factors clock registration to be done behind a composite clock. This allows us to additionally add a gate, mux or divisors, as it will be needed by some future PLLs. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org>
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#
e71c69fc |
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18-Oct-2013 |
Victor N. Ramos Mello <victornrm@gmail.com> |
drivers: clk: sunxi: Fix memory leakage in clk-sunxi.c Fix a possible memory leak in sun4i_osc_clk_setup(). Moved clock-frequency check to save superfluous allocation. Signed-off-by: Victor N. Ramos Mello <victornrm@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
8e6a4c40 |
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20-Sep-2013 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: protect core clocks from accidental shutdown Some important clocks may get disabled as a side effect of another clock being disabled, because they have no consumers. This patch implements a mechanism so those clocks can be claimed by the driver and therefore remain enabled at all times. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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#
be080451 |
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06-Sep-2013 |
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> |
clk: sunxi: declare OF clock provider Common clock framework allows to register clock providers to get called on of_clk_init() by using CLK_OF_DECLARE. This converts sunxi clock providers to make use of it and get rid of the mach specific clk init call. As sunxi has a bunch of independent clk provider nodes, we hook current clock init to board compatible to make it called once. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org>
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#
52be7cc8 |
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12-Aug-2013 |
Sachin Kamat <sachin.kamat@linaro.org> |
clk: sunxi: Fix incorrect placement of __initconst __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Cc: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: refreshed patch based on sunxi changes]
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#
1ec5502e |
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04-Aug-2013 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: fix initialization of basic clocks With the recent move towards CLK_OF_DECLARE(...), the driver stopped initializing osc32k, which is compatible "fixed-clock". This is because we never called of_clk_init(NULL). Fix this by moving the only other simple clock (osc24M) to use CLK_OF_DECLARE(...) and call of_clk_init(NULL) to initialize both of them. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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#
1fb2e4aa |
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25-Jul-2013 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Add Allwinner A20 gates The Allwinner A20 is almost identical to the earlier A10 SoC from Allwinner on many aspects, including the clocks tree. However, since the A20 has some additionnal IPs compared to the A10, the clock tree isn't exactly the same, especially when it comes to the gated clocks available. We thus need to register different clock gates for the A20. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Emilio López <emilio@elopez.com.ar>
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#
6a721db1 |
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23-Jul-2013 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Add A31 clocks support The A31 has a mostly different clock set compared to the other older SoCs currently supported in the Allwinner clock driver. Add support for the basic useful clocks. The other ones will come in eventually. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Emilio López <emilio@elopez.com.ar>
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#
70855bb5 |
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23-Jul-2013 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Allow to specify the divider width from the dividers data The divider width used to be hardcoded. Some A31 dividers are no longer with the hardcoded width, so we need to make it specific to each divider and set it in the dividers data. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Emilio López <emilio@elopez.com.ar>
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#
81ba6c5e |
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22-Jul-2013 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Rename the structure to prepare the addition of sun6i Rename all the generic-named structure to sun4i to avoid confusion when we will introduce the sun6i (A31) clocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Emilio López <emilio@elopez.com.ar>
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#
431807f0 |
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22-Jul-2013 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: fix initialization of basic clocks With the recent move towards CLK_OF_DECLARE(...), the driver stopped initializing osc32k, which is compatible "fixed-clock". This is because we never called of_clk_init(NULL). Fix this by moving the only other simple clock (osc24M) to use CLK_OF_DECLARE(...) and call of_clk_init(NULL) to initialize both of them. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Mike Turquette <mturquette@linaro.org>
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#
2371dd88 |
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16-Jul-2013 |
Maxime Ripard <mripard@kernel.org> |
clk: sunxi: Add A10s gates The Allwinner A10s has a slightly different gates set than the A10 and A13, so add these gates to the clk driver. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Emilio López <emilio@elopez.com.ar> Reviewed-by: Emilio López <emilio@elopez.com.ar>
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#
819c1de3 |
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28-Jul-2013 |
James Hogan <jhogan@kernel.org> |
clk: add CLK_SET_RATE_NO_REPARENT flag Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes being reparented during clk_set_rate. To avoid breaking existing platforms, all callers of clk_register_mux() are adjusted to pass the new flag. Platform maintainers are encouraged to remove the flag if they wish to allow mux reparenting on set_rate. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Chao Xie <xiechao.mail@gmail.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Andrew Chew <achew@nvidia.com> Cc: Doug Anderson <dianders@chromium.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Tomasz Figa <t.figa@samsung.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: spear-devel@list.st.com Cc: linux-tegra@vger.kernel.org Tested-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> [tegra] Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi] Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq] Signed-off-by: Mike Turquette <mturquette@linaro.org>
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ee85e9bd |
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12-Jul-2013 |
Axel Lin <axel.lin@ingics.com> |
clk: sunxi: Fix checking return value of clk_register_[composite|factors] clk_register_composite() and clk_register_factors() return ERR_PTR on error. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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61fd58dc |
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17-May-2013 |
Giacomo A. Catenazzi <cate@cateee.net> |
clk: sunxi: "cpu_data" is defined in header files of some architectures In some architectures, the #define cpu_data is not a "macro-function", so the compiler will substitute the identifier with probably something wrong. Signed-off-by: Giacomo A. Catenazzi <cate@cateee.net> Signed-off-by: Emilio López <emilio@elopez.com.ar> [emilio@elopez.com.ar: use cpu_mux_data instead of this_cpu_data] Signed-off-by: Mike Turquette <mturquette@linaro.org>
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4f985b4c |
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30-Apr-2013 |
Maxime Ripard <mripard@kernel.org> |
clk: sun5i: Add compatibles for Allwinner A13 The A13 has a lot less clocks than the one found in the Allwinner A10. Add these stripped down clocks to the clock driver and in the documentation. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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38e4aa00 |
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10-Apr-2013 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: Unify oscillator clock This commit uses the new fixed-rate support on the composite clock to unify osc24M_fixed and osc24M clocks, so it matches the actual hardware. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: replace clk_register_gatable_osc with a call to clk_register_composite]
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918d7f6f |
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27-Mar-2013 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: drop an unnecesary kmalloc clk_register will copy this information, so we can just use a normal array and do one less dynamic allocation. Signed-off-by: Emilio López <emilio@elopez.com.ar> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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5a4fe9b5 |
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27-Mar-2013 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: drop CLK_IGNORE_UNUSED This flag was in place to prevent important clocks from getting gated while they had no users. Now that the UART driver supports clocks properly, we can drop this. Signed-off-by: Emilio López <emilio@elopez.com.ar> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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13569a70 |
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27-Mar-2013 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates This patchset adds DT support for all the AXI, AHB, APB0 and APB1 gates present on sunxi SoCs. Signed-off-by: Emilio López <emilio@elopez.com.ar> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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e3276998 |
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26-Mar-2013 |
Emilio López <emilio@elopez.com.ar> |
clk: sunxi: rename compatible strings During the introduction of the Allwinner SoC platforms, sunxi was initially meant as a generic name for all the variants of the Allwinner SoC. It was ok at the time of the support of only the A10 and A13 that look pretty much the same; but it's beginning to be troublesome with the future addition of the Allwinner A31 (sun6i) that is quite different, and would introduce some weird logic, where sunxi would actually mean in some case sun4i and sun5i but without sun6i... Moreover, it makes the compatible strings naming scheme not consistent with other architectures, where usually for this kind of compability, we just use the oldest SoC name that has this IP, so let's do just this. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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e874a669 |
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25-Feb-2013 |
Emilio López <emilio@elopez.com.ar> |
clk: arm: sunxi: Add a new clock driver for sunxi SOCs This commit implements the base CPU clocks for sunxi devices. It has been tested using a slightly modified cpufreq driver from the linux-sunxi 3.0 tree. Additionally, document the new bindings introduced by this patch. Idling: / # cat /sys/kernel/debug/clk/clk_summary clock enable_cnt prepare_cnt rate --------------------------------------------------------------------- osc32k 0 0 32768 osc24M_fixed 0 0 24000000 osc24M 0 0 24000000 apb1_mux 0 0 24000000 apb1 0 0 24000000 pll1 0 0 60000000 cpu 0 0 60000000 axi 0 0 60000000 ahb 0 0 60000000 apb0 0 0 30000000 dummy 0 0 0 After "yes >/dev/null &": / # cat /sys/kernel/debug/clk/clk_summary clock enable_cnt prepare_cnt rate --------------------------------------------------------------------- osc32k 0 0 32768 osc24M_fixed 0 0 24000000 osc24M 0 0 24000000 apb1_mux 0 0 24000000 apb1 0 0 24000000 pll1 0 0 1008000000 cpu 0 0 1008000000 axi 0 0 336000000 ahb 0 0 168000000 apb0 0 0 84000000 dummy 0 0 0 Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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