160777Sobrien// SPDX-License-Identifier: GPL-2.0-only 260777Sobrien/* 3130575Sobrien * Clock definitions for u8500 platform. 4130575Sobrien * 560777Sobrien * Copyright (C) 2012 ST-Ericsson SA 6130575Sobrien * Author: Ulf Hansson <ulf.hansson@linaro.org> 7130575Sobrien */ 8130575Sobrien 960777Sobrien#include <linux/of.h> 10130575Sobrien#include <linux/of_address.h> 11130575Sobrien#include <linux/clk-provider.h> 1260777Sobrien#include <linux/mfd/dbx500-prcmu.h> 13130575Sobrien 1460777Sobrien#include "clk.h" 1560777Sobrien#include "prcc.h" 16130575Sobrien#include "reset-prcc.h" 1760777Sobrien 1860777Sobrienstatic struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; 19130575Sobrienstatic struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER]; 2077324Sobrienstatic struct clk_hw *clkout_clk[2]; 2160777Sobrien 22130575Sobrien#define PRCC_SHOW(clk, base, bit) \ 2360777Sobrien clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] 2460777Sobrien#define PRCC_PCLK_STORE(clk, base, bit) \ 25130575Sobrien prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk 2660777Sobrien#define PRCC_KCLK_STORE(clk, base, bit) \ 2760777Sobrien prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk 28130575Sobrien 2977324Sobrienstatic struct clk *ux500_twocell_get(struct of_phandle_args *clkspec, 3077324Sobrien void *data) 31130575Sobrien{ 3260777Sobrien struct clk **clk_data = data; 3360777Sobrien unsigned int base, bit; 34130575Sobrien 3560777Sobrien if (clkspec->args_count != 2) 3660777Sobrien return ERR_PTR(-EINVAL); 37130575Sobrien 38130575Sobrien base = clkspec->args[0]; 39130575Sobrien bit = clkspec->args[1]; 40130575Sobrien 4160777Sobrien if (base != 1 && base != 2 && base != 3 && base != 5 && base != 6) { 4260777Sobrien pr_err("%s: invalid PRCC base %d\n", __func__, base); 43218822Sdim return ERR_PTR(-EINVAL); 44218822Sdim } 45218822Sdim 46218822Sdim return PRCC_SHOW(clk_data, base, bit); 47218822Sdim} 48218822Sdim 49218822Sdimstatic struct clk_hw_onecell_data u8500_prcmu_hw_clks = { 50218822Sdim .hws = { 51218822Sdim /* 52218822Sdim * This assignment makes sure the dynamic array 53218822Sdim * gets the right size. 54218822Sdim */ 55218822Sdim [PRCMU_NUM_CLKS] = NULL, 56218822Sdim }, 57218822Sdim .num = PRCMU_NUM_CLKS, 58218822Sdim}; 59218822Sdim 60218822Sdim/* Essentially names for the first PRCMU_CLKSRC_* defines */ 61218822Sdimstatic const char * const u8500_clkout_parents[] = { 62218822Sdim "clk38m_to_clkgen", 63218822Sdim "aclk", 64218822Sdim /* Just called "sysclk" in documentation */ 65218822Sdim "ab8500_sysclk", 66218822Sdim "lcdclk", 67218822Sdim "sdmmcclk", 68218822Sdim "tvclk", 69218822Sdim "timclk", 70218822Sdim /* CLK009 is not implemented, add it if you need it */ 71218822Sdim "clk009", 72218822Sdim}; 73218822Sdim 74218822Sdimstatic struct clk_hw *ux500_clkout_get(struct of_phandle_args *clkspec, 75218822Sdim void *data) 76218822Sdim{ 77218822Sdim u32 id, source, divider; 78218822Sdim struct clk_hw *clkout; 79218822Sdim 80218822Sdim if (clkspec->args_count != 3) 81218822Sdim return ERR_PTR(-EINVAL); 82218822Sdim 83218822Sdim id = clkspec->args[0]; 84218822Sdim source = clkspec->args[1]; 85218822Sdim divider = clkspec->args[2]; 86218822Sdim 87218822Sdim if (id > 1) { 88218822Sdim pr_err("%s: invalid clkout ID %d\n", __func__, id); 89218822Sdim return ERR_PTR(-EINVAL); 90218822Sdim } 91218822Sdim 92218822Sdim if (clkout_clk[id]) { 93218822Sdim pr_info("%s: clkout%d already registered, not reconfiguring\n", 94130575Sobrien __func__, id + 1); 95130575Sobrien return clkout_clk[id]; 96130575Sobrien } 97130575Sobrien 9889879Sobrien if (source > 7) { 9989879Sobrien pr_err("%s: invalid source ID %d\n", __func__, source); 100130575Sobrien return ERR_PTR(-EINVAL); 101130575Sobrien } 102130575Sobrien 103130575Sobrien if (divider == 0 || divider > 63) { 10460777Sobrien pr_err("%s: invalid divider %d\n", __func__, divider); 10560777Sobrien return ERR_PTR(-EINVAL); 106130575Sobrien } 10760777Sobrien 10860777Sobrien pr_debug("registering clkout%d with source %d and divider %d\n", 109130575Sobrien id + 1, source, divider); 11060777Sobrien 11160777Sobrien clkout = clk_reg_prcmu_clkout(id ? "clkout2" : "clkout1", 112130575Sobrien u8500_clkout_parents, 113130575Sobrien ARRAY_SIZE(u8500_clkout_parents), 114130575Sobrien source, divider); 115130575Sobrien if (IS_ERR(clkout)) { 11660777Sobrien pr_err("failed to register clkout%d\n", id + 1); 11760777Sobrien return ERR_CAST(clkout); 118130575Sobrien } 11960777Sobrien 12060777Sobrien clkout_clk[id] = clkout; 121130575Sobrien 122107503Sobrien return clkout; 12360777Sobrien} 124130575Sobrien 125130575Sobrienstatic void u8500_clk_init(struct device_node *np) 126130575Sobrien{ 127130575Sobrien struct prcmu_fw_version *fw_version; 128130575Sobrien struct device_node *child = NULL; 129130575Sobrien const char *sgaclk_parent = NULL; 130130575Sobrien struct clk *clk, *rtc_clk, *twd_clk; 131130575Sobrien u32 bases[CLKRST_MAX]; 132130575Sobrien struct u8500_prcc_reset *rstc; 133130575Sobrien int i; 134130575Sobrien 135130575Sobrien /* 136130575Sobrien * We allocate the reset controller here so that we can fill in the 13760777Sobrien * base addresses properly and pass to the reset controller init 13860777Sobrien * function later on. 139130575Sobrien */ 14060777Sobrien rstc = kzalloc(sizeof(*rstc), GFP_KERNEL); 14160777Sobrien if (!rstc) 142130575Sobrien return; 14360777Sobrien 14460777Sobrien for (i = 0; i < ARRAY_SIZE(bases); i++) { 145130575Sobrien struct resource r; 14660777Sobrien 14760777Sobrien if (of_address_to_resource(np, i, &r)) 148130575Sobrien /* Not much choice but to continue */ 149130575Sobrien pr_err("failed to get CLKRST %d base address\n", 150130575Sobrien i + 1); 151130575Sobrien bases[i] = r.start; 152130575Sobrien rstc->phy_base[i] = r.start; 153130575Sobrien } 154130575Sobrien 15560777Sobrien /* Clock sources */ 15660777Sobrien u8500_prcmu_hw_clks.hws[PRCMU_PLLSOC0] = 157130575Sobrien clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, 15860777Sobrien CLK_IGNORE_UNUSED); 15960777Sobrien 160130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_PLLSOC1] = 161130575Sobrien clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1, 162130575Sobrien CLK_IGNORE_UNUSED); 163130575Sobrien 16460777Sobrien u8500_prcmu_hw_clks.hws[PRCMU_PLLDDR] = 16560777Sobrien clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR, 166130575Sobrien CLK_IGNORE_UNUSED); 16760777Sobrien 16860777Sobrien /* 169130575Sobrien * Read-only clocks that only return their current rate, only used 170130575Sobrien * as parents to other clocks and not visible in the device tree. 171130575Sobrien * clk38m_to_clkgen is the same as the SYSCLK, i.e. the root clock. 172130575Sobrien */ 173130575Sobrien clk_reg_prcmu_rate("clk38m_to_clkgen", NULL, PRCMU_SYSCLK, 174130575Sobrien CLK_IGNORE_UNUSED); 175130575Sobrien clk_reg_prcmu_rate("aclk", NULL, PRCMU_ACLK, 17660777Sobrien CLK_IGNORE_UNUSED); 17760777Sobrien 178130575Sobrien /* TODO: add CLK009 if needed */ 17960777Sobrien 18060777Sobrien rtc_clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL", 181130575Sobrien CLK_IGNORE_UNUSED, 182130575Sobrien 32768); 183130575Sobrien 184130575Sobrien /* PRCMU clocks */ 18560777Sobrien fw_version = prcmu_get_fw_version(); 18660777Sobrien if (fw_version != NULL) { 187130575Sobrien switch (fw_version->project) { 18860777Sobrien case PRCMU_FW_PROJECT_U8500_C2: 18960777Sobrien case PRCMU_FW_PROJECT_U8500_SSG1: 190130575Sobrien case PRCMU_FW_PROJECT_U8520: 19160777Sobrien case PRCMU_FW_PROJECT_U8420: 19260777Sobrien case PRCMU_FW_PROJECT_U8420_SYSCLK: 193130575Sobrien case PRCMU_FW_PROJECT_U8500_SSG2: 19460777Sobrien sgaclk_parent = "soc0_pll"; 19560777Sobrien break; 196130575Sobrien default: 19760777Sobrien break; 19860777Sobrien } 199130575Sobrien } 200130575Sobrien 201130575Sobrien if (sgaclk_parent) 202130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_SGACLK] = 203130575Sobrien clk_reg_prcmu_gate("sgclk", sgaclk_parent, 204130575Sobrien PRCMU_SGACLK, 0); 205218822Sdim else 206218822Sdim u8500_prcmu_hw_clks.hws[PRCMU_SGACLK] = 207218822Sdim clk_reg_prcmu_gate("sgclk", NULL, PRCMU_SGACLK, 0); 208130575Sobrien 209130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_UARTCLK] = 210130575Sobrien clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, 0); 211130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_MSP02CLK] = 212130575Sobrien clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, 0); 213130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_MSP1CLK] = 214130575Sobrien clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, 0); 215218822Sdim u8500_prcmu_hw_clks.hws[PRCMU_I2CCLK] = 216130575Sobrien clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, 0); 217130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_SLIMCLK] = 21860777Sobrien clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, 0); 21960777Sobrien u8500_prcmu_hw_clks.hws[PRCMU_PER1CLK] = 220130575Sobrien clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, 0); 22160777Sobrien u8500_prcmu_hw_clks.hws[PRCMU_PER2CLK] = 22260777Sobrien clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, 0); 223130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_PER3CLK] = 22460777Sobrien clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, 0); 22560777Sobrien u8500_prcmu_hw_clks.hws[PRCMU_PER5CLK] = 226130575Sobrien clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, 0); 22760777Sobrien u8500_prcmu_hw_clks.hws[PRCMU_PER6CLK] = 22860777Sobrien clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, 0); 229130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_PER7CLK] = 230130575Sobrien clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, 0); 231130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_LCDCLK] = 232130575Sobrien clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0, 233130575Sobrien CLK_SET_RATE_GATE); 234130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_BMLCLK] = 235130575Sobrien clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, 0); 23660777Sobrien u8500_prcmu_hw_clks.hws[PRCMU_HSITXCLK] = 23760777Sobrien clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0, 238218822Sdim CLK_SET_RATE_GATE); 239218822Sdim u8500_prcmu_hw_clks.hws[PRCMU_HSIRXCLK] = 240218822Sdim clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0, 241130575Sobrien CLK_SET_RATE_GATE); 24260777Sobrien u8500_prcmu_hw_clks.hws[PRCMU_HDMICLK] = 24360777Sobrien clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0, 244130575Sobrien CLK_SET_RATE_GATE); 24560777Sobrien u8500_prcmu_hw_clks.hws[PRCMU_APEATCLK] = 24660777Sobrien clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, 0); 247130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_APETRACECLK] = 24860777Sobrien clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0, 24960777Sobrien CLK_SET_RATE_GATE); 250130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_MCDECLK] = 25160777Sobrien clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, 0); 25260777Sobrien u8500_prcmu_hw_clks.hws[PRCMU_IPI2CCLK] = 253130575Sobrien clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, 0); 25460777Sobrien u8500_prcmu_hw_clks.hws[PRCMU_DSIALTCLK] = 25560777Sobrien clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, 0); 256130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_DMACLK] = 25760777Sobrien clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, 0); 25860777Sobrien u8500_prcmu_hw_clks.hws[PRCMU_B2R2CLK] = 259218822Sdim clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, 0); 260218822Sdim u8500_prcmu_hw_clks.hws[PRCMU_TVCLK] = 261218822Sdim clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0, 262130575Sobrien CLK_SET_RATE_GATE); 26360777Sobrien u8500_prcmu_hw_clks.hws[PRCMU_SSPCLK] = 26460777Sobrien clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, 0); 265130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_RNGCLK] = 266130575Sobrien clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, 0); 267130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_UICCCLK] = 268130575Sobrien clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, 0); 269130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_TIMCLK] = 270130575Sobrien clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0); 271130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_SYSCLK] = 272130575Sobrien clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, 0); 273130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_SDMMCCLK] = 274130575Sobrien clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, 275130575Sobrien PRCMU_SDMMCCLK, 100000000, 276130575Sobrien CLK_SET_RATE_GATE); 277130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_PLLDSI] = 278130575Sobrien clk_reg_prcmu_scalable("dsi_pll", "hdmiclk", 279130575Sobrien PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE); 280130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_DSI0CLK] = 281130575Sobrien clk_reg_prcmu_scalable("dsi0clk", "dsi_pll", 282130575Sobrien PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE); 283130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_DSI1CLK] = 284130575Sobrien clk_reg_prcmu_scalable("dsi1clk", "dsi_pll", 285130575Sobrien PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE); 286130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_DSI0ESCCLK] = 287130575Sobrien clk_reg_prcmu_scalable("dsi0escclk", "tvclk", 288130575Sobrien PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE); 289130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_DSI1ESCCLK] = 290130575Sobrien clk_reg_prcmu_scalable("dsi1escclk", "tvclk", 291130575Sobrien PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE); 292130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_DSI2ESCCLK] = 293130575Sobrien clk_reg_prcmu_scalable("dsi2escclk", "tvclk", 294130575Sobrien PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE); 295130575Sobrien u8500_prcmu_hw_clks.hws[PRCMU_ARMSS] = 296130575Sobrien clk_reg_prcmu_scalable_rate("armss", NULL, 297130575Sobrien PRCMU_ARMSS, 0, CLK_IGNORE_UNUSED); 298130575Sobrien 299130575Sobrien twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss", 300130575Sobrien CLK_IGNORE_UNUSED, 1, 2); 301130575Sobrien 302130575Sobrien /* PRCC P-clocks */ 303130575Sobrien clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX], 304130575Sobrien BIT(0), 0); 305130575Sobrien PRCC_PCLK_STORE(clk, 1, 0); 306130575Sobrien 307130575Sobrien clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX], 308130575Sobrien BIT(1), 0); 309130575Sobrien PRCC_PCLK_STORE(clk, 1, 1); 310130575Sobrien 311130575Sobrien clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX], 312130575Sobrien BIT(2), 0); 313130575Sobrien PRCC_PCLK_STORE(clk, 1, 2); 314130575Sobrien 315130575Sobrien clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX], 316130575Sobrien BIT(3), 0); 317130575Sobrien PRCC_PCLK_STORE(clk, 1, 3); 318130575Sobrien 319130575Sobrien clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX], 320130575Sobrien BIT(4), 0); 321130575Sobrien PRCC_PCLK_STORE(clk, 1, 4); 322130575Sobrien 323130575Sobrien clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX], 324130575Sobrien BIT(5), 0); 325130575Sobrien PRCC_PCLK_STORE(clk, 1, 5); 32660777Sobrien 32760777Sobrien clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX], 328130575Sobrien BIT(6), 0); 329130575Sobrien PRCC_PCLK_STORE(clk, 1, 6); 330130575Sobrien 331130575Sobrien clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX], 33260777Sobrien BIT(7), 0); 33360777Sobrien PRCC_PCLK_STORE(clk, 1, 7); 334130575Sobrien 335130575Sobrien clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX], 336130575Sobrien BIT(8), 0); 337130575Sobrien PRCC_PCLK_STORE(clk, 1, 8); 338130575Sobrien 339130575Sobrien clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX], 340130575Sobrien BIT(9), 0); 34160777Sobrien PRCC_PCLK_STORE(clk, 1, 9); 34260777Sobrien 343130575Sobrien clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX], 344130575Sobrien BIT(10), 0); 345130575Sobrien PRCC_PCLK_STORE(clk, 1, 10); 346130575Sobrien 347130575Sobrien clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX], 348130575Sobrien BIT(11), 0); 349130575Sobrien PRCC_PCLK_STORE(clk, 1, 11); 35060777Sobrien 35160777Sobrien clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX], 352130575Sobrien BIT(0), 0); 35360777Sobrien PRCC_PCLK_STORE(clk, 2, 0); 35460777Sobrien 355130575Sobrien clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX], 356130575Sobrien BIT(1), 0); 357130575Sobrien PRCC_PCLK_STORE(clk, 2, 1); 358130575Sobrien 35960777Sobrien clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX], 36060777Sobrien BIT(2), 0); 361218822Sdim PRCC_PCLK_STORE(clk, 2, 2); 362218822Sdim 363218822Sdim clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX], 364218822Sdim BIT(3), 0); 365218822Sdim PRCC_PCLK_STORE(clk, 2, 3); 366218822Sdim 367130575Sobrien clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX], 36860777Sobrien BIT(4), 0); 36960777Sobrien PRCC_PCLK_STORE(clk, 2, 4); 370130575Sobrien 371130575Sobrien clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX], 37289879Sobrien BIT(5), 0); 373130575Sobrien PRCC_PCLK_STORE(clk, 2, 5); 374130575Sobrien 37577324Sobrien clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX], 376130575Sobrien BIT(6), 0); 377130575Sobrien PRCC_PCLK_STORE(clk, 2, 6); 37877324Sobrien 379130575Sobrien clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX], 380130575Sobrien BIT(7), 0); 38160777Sobrien PRCC_PCLK_STORE(clk, 2, 7); 382218822Sdim 383218822Sdim clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX], 38460777Sobrien BIT(8), 0); 385130575Sobrien PRCC_PCLK_STORE(clk, 2, 8); 386130575Sobrien 38760777Sobrien clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX], 388130575Sobrien BIT(9), 0); 389130575Sobrien PRCC_PCLK_STORE(clk, 2, 9); 39060777Sobrien 391130575Sobrien clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX], 392130575Sobrien BIT(10), 0); 39377324Sobrien PRCC_PCLK_STORE(clk, 2, 10); 394130575Sobrien 395130575Sobrien clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX], 39660777Sobrien BIT(11), 0); 397130575Sobrien PRCC_PCLK_STORE(clk, 2, 11); 398130575Sobrien 39960777Sobrien clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX], 400130575Sobrien BIT(12), 0); 401130575Sobrien PRCC_PCLK_STORE(clk, 2, 12); 40260777Sobrien 403130575Sobrien clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX], 404130575Sobrien BIT(0), 0); 40560777Sobrien PRCC_PCLK_STORE(clk, 3, 0); 406130575Sobrien 407130575Sobrien clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX], 40877324Sobrien BIT(1), 0); 409218822Sdim PRCC_PCLK_STORE(clk, 3, 1); 410218822Sdim 411218822Sdim clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX], 412130575Sobrien BIT(2), 0); 413130575Sobrien PRCC_PCLK_STORE(clk, 3, 2); 414130575Sobrien 415130575Sobrien clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX], 416130575Sobrien BIT(3), 0); 41777324Sobrien PRCC_PCLK_STORE(clk, 3, 3); 418130575Sobrien 419130575Sobrien clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX], 42077324Sobrien BIT(4), 0); 421130575Sobrien PRCC_PCLK_STORE(clk, 3, 4); 422130575Sobrien 42389879Sobrien clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX], 424218822Sdim BIT(5), 0); 425218822Sdim PRCC_PCLK_STORE(clk, 3, 5); 426218822Sdim 427218822Sdim clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX], 428218822Sdim BIT(6), 0); 429218822Sdim PRCC_PCLK_STORE(clk, 3, 6); 430218822Sdim 431130575Sobrien clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX], 43277324Sobrien BIT(7), 0); 433130575Sobrien PRCC_PCLK_STORE(clk, 3, 7); 434130575Sobrien 43577324Sobrien clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX], 436218822Sdim BIT(8), 0); 437218822Sdim PRCC_PCLK_STORE(clk, 3, 8); 438218822Sdim 439130575Sobrien clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX], 440218822Sdim BIT(0), 0); 44177324Sobrien PRCC_PCLK_STORE(clk, 5, 0); 442130575Sobrien 443130575Sobrien clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX], 44489879Sobrien BIT(1), 0); 445130575Sobrien PRCC_PCLK_STORE(clk, 5, 1); 446130575Sobrien 44789879Sobrien clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX], 448130575Sobrien BIT(0), 0); 449130575Sobrien PRCC_PCLK_STORE(clk, 6, 0); 450 451 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX], 452 BIT(1), 0); 453 PRCC_PCLK_STORE(clk, 6, 1); 454 455 clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX], 456 BIT(2), 0); 457 PRCC_PCLK_STORE(clk, 6, 2); 458 459 clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX], 460 BIT(3), 0); 461 PRCC_PCLK_STORE(clk, 6, 3); 462 463 clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX], 464 BIT(4), 0); 465 PRCC_PCLK_STORE(clk, 6, 4); 466 467 clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX], 468 BIT(5), 0); 469 PRCC_PCLK_STORE(clk, 6, 5); 470 471 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX], 472 BIT(6), 0); 473 PRCC_PCLK_STORE(clk, 6, 6); 474 475 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX], 476 BIT(7), 0); 477 PRCC_PCLK_STORE(clk, 6, 7); 478 479 /* PRCC K-clocks 480 * 481 * FIXME: Some drivers requires PERPIH[n| to be automatically enabled 482 * by enabling just the K-clock, even if it is not a valid parent to 483 * the K-clock. Until drivers get fixed we might need some kind of 484 * "parent muxed join". 485 */ 486 487 /* Periph1 */ 488 clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk", 489 bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE); 490 PRCC_KCLK_STORE(clk, 1, 0); 491 492 clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk", 493 bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE); 494 PRCC_KCLK_STORE(clk, 1, 1); 495 496 clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk", 497 bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE); 498 PRCC_KCLK_STORE(clk, 1, 2); 499 500 clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk", 501 bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE); 502 PRCC_KCLK_STORE(clk, 1, 3); 503 504 clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk", 505 bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE); 506 PRCC_KCLK_STORE(clk, 1, 4); 507 508 clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk", 509 bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE); 510 PRCC_KCLK_STORE(clk, 1, 5); 511 512 clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk", 513 bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE); 514 PRCC_KCLK_STORE(clk, 1, 6); 515 516 clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk", 517 bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE); 518 PRCC_KCLK_STORE(clk, 1, 8); 519 520 clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk", 521 bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE); 522 PRCC_KCLK_STORE(clk, 1, 9); 523 524 clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk", 525 bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE); 526 PRCC_KCLK_STORE(clk, 1, 10); 527 528 /* Periph2 */ 529 clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk", 530 bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE); 531 PRCC_KCLK_STORE(clk, 2, 0); 532 533 clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk", 534 bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE); 535 PRCC_KCLK_STORE(clk, 2, 2); 536 537 clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk", 538 bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE); 539 PRCC_KCLK_STORE(clk, 2, 3); 540 541 clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk", 542 bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE); 543 PRCC_KCLK_STORE(clk, 2, 4); 544 545 clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk", 546 bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE); 547 PRCC_KCLK_STORE(clk, 2, 5); 548 549 /* Note that rate is received from parent. */ 550 clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk", 551 bases[CLKRST2_INDEX], BIT(6), 552 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); 553 PRCC_KCLK_STORE(clk, 2, 6); 554 555 clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk", 556 bases[CLKRST2_INDEX], BIT(7), 557 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); 558 PRCC_KCLK_STORE(clk, 2, 7); 559 560 /* Periph3 */ 561 clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk", 562 bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE); 563 PRCC_KCLK_STORE(clk, 3, 1); 564 565 clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk", 566 bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE); 567 PRCC_KCLK_STORE(clk, 3, 2); 568 569 clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk", 570 bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE); 571 PRCC_KCLK_STORE(clk, 3, 3); 572 573 clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk", 574 bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE); 575 PRCC_KCLK_STORE(clk, 3, 4); 576 577 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k", 578 bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE); 579 PRCC_KCLK_STORE(clk, 3, 5); 580 581 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk", 582 bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE); 583 PRCC_KCLK_STORE(clk, 3, 6); 584 585 clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk", 586 bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE); 587 PRCC_KCLK_STORE(clk, 3, 7); 588 589 /* Periph6 */ 590 clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk", 591 bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE); 592 PRCC_KCLK_STORE(clk, 6, 0); 593 594 for_each_child_of_node(np, child) { 595 if (of_node_name_eq(child, "prcmu-clock")) 596 of_clk_add_hw_provider(child, of_clk_hw_onecell_get, 597 &u8500_prcmu_hw_clks); 598 599 if (of_node_name_eq(child, "clkout-clock")) 600 of_clk_add_hw_provider(child, ux500_clkout_get, NULL); 601 602 if (of_node_name_eq(child, "prcc-periph-clock")) 603 of_clk_add_provider(child, ux500_twocell_get, prcc_pclk); 604 605 if (of_node_name_eq(child, "prcc-kernel-clock")) 606 of_clk_add_provider(child, ux500_twocell_get, prcc_kclk); 607 608 if (of_node_name_eq(child, "rtc32k-clock")) 609 of_clk_add_provider(child, of_clk_src_simple_get, rtc_clk); 610 611 if (of_node_name_eq(child, "smp-twd-clock")) 612 of_clk_add_provider(child, of_clk_src_simple_get, twd_clk); 613 614 if (of_node_name_eq(child, "prcc-reset-controller")) 615 u8500_prcc_reset_init(child, rstc); 616 } 617} 618CLK_OF_DECLARE(u8500_clks, "stericsson,u8500-clks", u8500_clk_init); 619