Searched refs:clock (Results 51 - 75 of 1865) sorted by relevance

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/linux-master/arch/mips/include/asm/
H A Dtime.h68 unsigned int clock)
70 clockevents_calc_mult_shift(cd, clock, 4);
67 clockevent_set_clock(struct clock_event_device *cd, unsigned int clock) argument
/linux-master/arch/mips/loongson2ef/lemote-2f/
H A DMakefile6 obj-y += clock.o machtype.o irq.o reset.o dma.o ec_kb3310b.o
/linux-master/arch/riscv/kernel/vdso/
H A Dvgettimeofday.c13 int __vdso_clock_gettime(clockid_t clock, struct __kernel_timespec *ts) argument
15 return __cvdso_clock_gettime(clock, ts);
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_dpll.c194 * We calculate clock using (register_value + 2) for N/M1/M2, so here
267 * clock and actual rate limits are more relaxed, so checking
283 * clock and actual rate limits are more relaxed, so checking
307 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
308 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
309 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
310 * The helpers' return value is the rate of the clock tha
315 pnv_calc_dpll_params(int refclk, struct dpll *clock) argument
333 i9xx_calc_dpll_params(int refclk, struct dpll *clock) argument
346 vlv_calc_dpll_params(int refclk, struct dpll *clock) argument
359 chv_calc_dpll_params(int refclk, struct dpll *clock) argument
396 struct dpll clock; local
487 struct dpll clock; local
515 struct dpll clock; local
546 intel_pll_is_valid(struct drm_i915_private *dev_priv, const struct intel_limit *limit, const struct dpll *clock) argument
623 struct dpll clock; local
681 struct dpll clock; local
737 struct dpll clock; local
832 struct dpll clock; local
891 struct dpll clock; local
961 i9xx_update_pll_dividers(struct intel_crtc_state *crtc_state, const struct dpll *clock, const struct dpll *reduced_clock) argument
981 i9xx_compute_dpll(struct intel_crtc_state *crtc_state, const struct dpll *clock, const struct dpll *reduced_clock) argument
1060 i8xx_compute_dpll(struct intel_crtc_state *crtc_state, const struct dpll *clock, const struct dpll *reduced_clock) argument
1200 ilk_update_pll_dividers(struct intel_crtc_state *crtc_state, const struct dpll *clock, const struct dpll *reduced_clock) argument
1233 ilk_compute_dpll(struct intel_crtc_state *crtc_state, const struct dpll *clock, const struct dpll *reduced_clock) argument
[all...]
/linux-master/arch/powerpc/kernel/vdso/
H A Dvgettimeofday.c9 int __c_kernel_clock_gettime(clockid_t clock, struct __kernel_timespec *ts, argument
12 return __cvdso_clock_gettime_data(vd, clock, ts);
21 int __c_kernel_clock_gettime(clockid_t clock, struct old_timespec32 *ts, argument
24 return __cvdso_clock_gettime32_data(vd, clock, ts);
27 int __c_kernel_clock_gettime64(clockid_t clock, struct __kernel_timespec *ts, argument
30 return __cvdso_clock_gettime_data(vd, clock, ts);
/linux-master/kernel/sched/
H A Dclock.c18 * clock with bounded drift between CPUs. The value of cpu_clock(i)
41 * Otherwise it tries to create a semi stable clock from a mixture of other
44 * - GTOD (clock monotonic)
58 * Scheduler clock - returns current time in nanosec units.
91 u64 clock; member in struct:sched_clock_data
149 * The only way to fully avoid random clock jumps is to boot with:
161 scd->clock = scd->tick_gtod + __gtod_offset;
265 u64 now, clock, old_clock, min_clock, max_clock, gtod; local
274 old_clock = scd->clock;
277 * scd->clock
298 u64 clock; local
391 u64 clock; local
[all...]
/linux-master/drivers/gpu/drm/gma500/
H A Doaktrail_crtc.c113 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
114 static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock) argument
116 clock->dot = (refclk * clock->m) / (14 * clock->p1);
119 static void mrst_print_pll(struct gma_clock_t *clock) argument
122 clock->dot, clock->m, clock->m1, clock
130 struct gma_clock_t clock; local
188 struct gma_clock_t clock; local
371 struct gma_clock_t clock; local
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H A Dcdv_intel_display.c209 * DPLL reference clock is on in the DPLL control register, but before
214 struct gma_clock_t *clock, bool is_lvds, u32 ddi_select)
244 * refclka mean use clock from same PLL
246 * if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll
272 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT);
288 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT);
290 if (clock->vco < 2250000) {
293 } else if (clock->vco < 2750000) {
296 } else if (clock->vco < 3300000) {
312 p |= SET_FIELD(clock
213 cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc, struct gma_clock_t *clock, bool is_lvds, u32 ddi_select) argument
393 cdv_intel_clock(int refclk, struct gma_clock_t *clock) argument
407 struct gma_clock_t clock; local
583 struct gma_clock_t clock; local
826 i8xx_clock(int refclk, struct gma_clock_t *clock) argument
844 struct gma_clock_t clock; local
[all...]
H A Dpsb_intel_display.c68 static void psb_intel_clock(int refclk, struct gma_clock_t *clock) argument
70 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
71 clock->p = clock->p1 * clock->p2;
72 clock->vco = refclk * clock->m / (clock
106 struct gma_clock_t clock; local
312 struct gma_clock_t clock; local
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/linux-master/tools/perf/tests/shell/
H A Drecord_bpf_filter.sh31 if ! perf record -e task-clock --filter 'period > 1' \
43 if ! perf record -e task-clock -c 10000 --filter 'ip < 0xffffffff00000000' \
69 if ! perf record -e task-clock --filter 'cpu > 0' \
77 if ! perf record --sample-cpu -e task-clock --filter 'cpu > 0' \
91 if ! perf record -e task-clock --filter 'period > 1000 || ip > 0' \
99 if ! perf record -e task-clock --filter 'cpu > 0 || ip > 0' \
107 if ! perf record -e task-clock --filter 'period > 0 || code_pgsz > 4096' \
H A Dpipe_test.sh17 if ! perf record -e task-clock:u -o - ${prog} | perf report -i - --task | grep ${task}; then
22 if ! perf record -e task-clock:u -o - ${prog} | perf inject -b | perf report -i - | grep ${sym}; then
27 perf record -e task-clock:u -o - ${prog} | perf inject -b -o ${data}
33 perf record -e task-clock:u -o ${data} ${prog}
/linux-master/drivers/net/phy/
H A Ddp83640.c107 struct dp83640_clock *clock; member in struct:dp83640_private
133 /* we create one clock instance per MII bus */
147 /* reference to our PTP hardware clock */
174 "The address of the PHY to use for the ancillary clock features");
231 if (dp83640->clock->page != page) {
233 dp83640->clock->page = page;
246 if (dp83640->clock->page != page) {
248 dp83640->clock->page = page;
303 static int periodic_output(struct dp83640_clock *clock, argument
307 struct dp83640_private *dp83640 = clock
376 struct dp83640_clock *clock = local
409 struct dp83640_clock *clock = local
431 struct dp83640_clock *clock = local
456 struct dp83640_clock *clock = local
473 struct dp83640_clock *clock = local
533 struct dp83640_clock *clock = local
552 struct dp83640_clock *clock = dp83640->clock; local
629 recalibrate(struct dp83640_clock *clock) argument
968 struct dp83640_clock *clock; local
990 dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus) argument
1021 choose_this_phy(struct dp83640_clock *clock, struct phy_device *phydev) argument
1033 dp83640_clock_get(struct dp83640_clock *clock) argument
1046 struct dp83640_clock *clock = NULL, *tmp; local
1081 dp83640_clock_put(struct dp83640_clock *clock) argument
1106 struct dp83640_clock *clock = dp83640->clock; local
1423 struct dp83640_clock *clock; local
1484 struct dp83640_clock *clock; local
[all...]
/linux-master/sound/pci/echoaudio/
H A Dgina24_dsp.c33 static int set_input_clock(struct echoaudio *chip, u16 clock);
102 /* Map the DSP clock detect bits to the generic driver clock
154 48 kHz, internal clock, S/PDIF RCA mode */
166 u32 control_reg, clock; local
172 /* Only set the clock for internal mode. */
175 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
182 clock = 0;
189 clock = GML_96KHZ;
192 clock
236 set_input_clock(struct echoaudio *chip, u16 clock) argument
[all...]
H A Dlayla24_dsp.c32 static int set_input_clock(struct echoaudio *chip, u16 clock);
94 /* Map the DSP clock detect bits to the generic driver clock detect bits */
150 48 kHz, internal clock, S/PDIF RCA mode */
162 u32 control_reg, clock, base_rate; local
168 /* Only set the clock for internal mode. */
171 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
182 clock = 0;
186 clock = GML_96KHZ;
189 clock
252 set_input_clock(struct echoaudio *chip, u16 clock) argument
[all...]
/linux-master/include/soc/fsl/qe/
H A Ducc.h38 int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
40 int ucc_set_tdm_rxtx_clk(unsigned int tdm_num, enum qe_clock clock,
42 int ucc_set_tdm_rxtx_sync(unsigned int tdm_num, enum qe_clock clock,
47 /* QE MUX clock routing for UCC
/linux-master/drivers/net/ethernet/cavium/common/
H A Dcavium_ptp.h2 /* cavium_ptp.h - PTP 1588 clock on Cavium hardware
44 static inline int cavium_ptp_clock_index(struct cavium_ptp *clock) argument
46 return ptp_clock_index(clock->ptp_clock);
63 static inline int cavium_ptp_clock_index(struct cavium_ptp *clock) argument
/linux-master/sound/firewire/fireworks/
H A Dfireworks_command.c27 /* for clock source and sampling rate */
90 [EFR_STATUS_BAD_CLOCK] = "bad clock",
274 command_get_clock(struct snd_efw *efw, struct efc_clock *clock) argument
281 (__be32 *)clock, sizeof(struct efc_clock));
283 be32_to_cpus(&clock->source);
284 be32_to_cpus(&clock->sampling_rate);
285 be32_to_cpus(&clock->index);
296 struct efc_clock clock = {0}; local
306 err = command_get_clock(efw, &clock);
311 if ((clock
346 struct efc_clock clock = {0}; local
358 struct efc_clock clock = {0}; local
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/linux-master/tools/testing/selftests/vDSO/
H A Dvdso_test_correctness.c257 static void test_one_clock_gettime(int clock, const char *name) argument
262 printf("[RUN]\tTesting clock_gettime for clock %s (%d)...\n", name, clock);
264 if (sys_clock_gettime(clock, &start) < 0) {
266 vdso_ret = vdso_clock_gettime(clock, &vdso);
268 printf("[OK]\tNo such clock.\n");
270 printf("[FAIL]\tNo such clock, but __vdso_clock_gettime returned %d\n", vdso_ret);
274 printf("[WARN]\t clock_gettime(%d) syscall returned error %d\n", clock, errno);
279 vdso_ret = vdso_clock_gettime(clock, &vdso);
280 end_ret = sys_clock_gettime(clock,
319 test_one_clock_gettime64(int clock, const char *name) argument
[all...]
/linux-master/arch/powerpc/platforms/512x/
H A DMakefile5 obj-$(CONFIG_COMMON_CLK) += clock-commonclk.o
/linux-master/arch/mips/alchemy/common/
H A DMakefile9 obj-y += prom.o time.o clock.o platform.o power.o gpiolib.o \
/linux-master/drivers/clk/sunxi-ng/
H A Dccu-sun4i-a10.h11 #include <dt-bindings/clock/sun4i-a10-ccu.h>
12 #include <dt-bindings/clock/sun7i-a20-ccu.h>
23 /* The PLL_VIDEO0_2X clock is exported */
32 /* The PLL_VIDEO1_2X clock is exported */
35 /* The CPU clock is exported */
/linux-master/arch/loongarch/include/asm/
H A Dtime.h46 unsigned int clock)
48 clockevents_calc_mult_shift(cd, clock, 4);
45 clockevent_set_clock(struct clock_event_device *cd, unsigned int clock) argument
/linux-master/drivers/clk/hisilicon/
H A Dclk-hip04.c3 * Hisilicon HiP04 clock driver
16 #include <dt-bindings/clock/hip04-clock.h>
39 CLK_OF_DECLARE(hip04_clk, "hisilicon,hip04-clock", hip04_clk_init);
/linux-master/tools/testing/selftests/damon/
H A Daccess_memory.c35 start_clock = clock();
36 while ((clock() - start_clock) * 1000 / CLOCKS_PER_SEC <
/linux-master/arch/sh/kernel/cpu/sh2/
H A DMakefile8 obj-$(CONFIG_CPU_SUBTYPE_SH7619) += setup-sh7619.o clock-sh7619.o

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