i915/display/intel_dpll.c

195  * We calculate clock using (register_value + 2) for N/M1/M2, so here
268 	  * clock and actual rate limits are more relaxed, so checking
284 	 * clock and actual rate limits are more relaxed, so checking
308  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
309  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
310  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
311  * The helpers' return value is the rate of the clock that is fed to the
312  * display engine's pipe which can be the above fast dot clock rate or a
316 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
318 	clock->m = clock->m2 + 2;
319 	clock->p = clock->p1 * clock->p2;
321 	clock->vco = clock->n == 0 ? 0 :
322 		DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
323 	clock->dot = clock->p == 0 ? 0 :
324 		DIV_ROUND_CLOSEST(clock->vco, clock->p);
326 	return clock->dot;
334 int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
336 	clock->m = i9xx_dpll_compute_m(clock);
337 	clock->p = clock->p1 * clock->p2;
339 	clock->vco = clock->n + 2 == 0 ? 0 :
340 		DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
341 	clock->dot = clock->p == 0 ? 0 :
342 		DIV_ROUND_CLOSEST(clock->vco, clock->p);
344 	return clock->dot;
347 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
349 	clock->m = clock->m1 * clock->m2;
350 	clock->p = clock->p1 * clock->p2 * 5;
352 	clock->vco = clock->n == 0 ? 0 :
353 		DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
354 	clock->dot = clock->p == 0 ? 0 :
355 		DIV_ROUND_CLOSEST(clock->vco, clock->p);
357 	return clock->dot;
360 int chv_calc_dpll_params(int refclk, struct dpll *clock)
362 	clock->m = clock->m1 * clock->m2;
363 	clock->p = clock->p1 * clock->p2 * 5;
365 	clock->vco = clock->n == 0 ? 0 :
366 		DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22);
367 	clock->dot = clock->p == 0 ? 0 :
368 		DIV_ROUND_CLOSEST(clock->vco, clock->p);
370 	return clock->dot;
419 /* Returns the clock of the currently programmed mode of the given pipe. */
427 	struct dpll clock;
436 	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
438 		clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
439 		clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
441 		clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
442 		clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
447 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
450 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
455 			clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
459 			clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
470 			port_clock = pnv_calc_dpll_params(refclk, &clock);
472 			port_clock = i9xx_calc_dpll_params(refclk, &clock);
481 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
485 				clock.p2 = 7;
487 				clock.p2 = 14;
490 				clock.p1 = 2;
492 				clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
496 				clock.p2 = 4;
498 				clock.p2 = 2;
501 		port_clock = i9xx_calc_dpll_params(refclk, &clock);
520 	struct dpll clock;
531 	clock.m1 = REG_FIELD_GET(DPIO_M1_DIV_MASK, tmp);
532 	clock.m2 = REG_FIELD_GET(DPIO_M2_DIV_MASK, tmp);
533 	clock.n = REG_FIELD_GET(DPIO_N_DIV_MASK, tmp);
534 	clock.p1 = REG_FIELD_GET(DPIO_P1_DIV_MASK, tmp);
535 	clock.p2 = REG_FIELD_GET(DPIO_P2_DIV_MASK, tmp);
537 	crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock);
547 	struct dpll clock;
563 	clock.m1 = REG_FIELD_GET(DPIO_CHV_M1_DIV_MASK, pll_dw1) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
564 	clock.m2 = REG_FIELD_GET(DPIO_CHV_M2_DIV_MASK, pll_dw0) << 22;
566 		clock.m2 |= REG_FIELD_GET(DPIO_CHV_M2_FRAC_DIV_MASK, pll_dw2);
567 	clock.n = REG_FIELD_GET(DPIO_CHV_N_DIV_MASK, pll_dw1);
568 	clock.p1 = REG_FIELD_GET(DPIO_CHV_P1_DIV_MASK, cmn_dw13);
569 	clock.p2 = REG_FIELD_GET(DPIO_CHV_P2_DIV_MASK, cmn_dw13);
571 	crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock);
580 			       const struct dpll *clock)
582 	if (clock->n < limit->n.min || limit->n.max < clock->n)
584 	if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
586 	if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
588 	if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
592 		if (clock->m1 <= clock->m2)
596 		if (clock->p < limit->p.min || limit->p.max < clock->p)
598 		if (clock->m < limit->m.min || limit->m.max < clock->m)
602 	if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
604 	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
607 	if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
639  * Returns a set of divisors for the desired target clock with the given
655 	struct dpll clock;
660 	clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
662 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
663 	     clock.m1++) {
664 		for (clock.m2 = limit->m2.min;
665 		     clock.m2 <= limit->m2.max; clock.m2++) {
666 			if (clock.m2 >= clock.m1)
668 			for (clock.n = limit->n.min;
669 			     clock.n <= limit->n.max; clock.n++) {
670 				for (clock.p1 = limit->p1.min;
671 					clock.p1 <= limit->p1.max; clock.p1++) {
674 					i9xx_calc_dpll_params(refclk, &clock);
677 								&clock))
680 					    clock.p != match_clock->p)
683 					this_err = abs(clock.dot - target);
685 						*best_clock = clock;
697  * Returns a set of divisors for the desired target clock with the given
713 	struct dpll clock;
718 	clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
720 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
721 	     clock.m1++) {
722 		for (clock.m2 = limit->m2.min;
723 		     clock.m2 <= limit->m2.max; clock.m2++) {
724 			for (clock.n = limit->n.min;
725 			     clock.n <= limit->n.max; clock.n++) {
726 				for (clock.p1 = limit->p1.min;
727 					clock.p1 <= limit->p1.max; clock.p1++) {
730 					pnv_calc_dpll_params(refclk, &clock);
733 								&clock))
736 					    clock.p != match_clock->p)
739 					this_err = abs(clock.dot - target);
741 						*best_clock = clock;
753  * Returns a set of divisors for the desired target clock with the given
769 	struct dpll clock;
777 	clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
781 	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
783 		for (clock.m1 = limit->m1.max;
784 		     clock.m1 >= limit->m1.min; clock.m1--) {
785 			for (clock.m2 = limit->m2.max;
786 			     clock.m2 >= limit->m2.min; clock.m2--) {
787 				for (clock.p1 = limit->p1.max;
788 				     clock.p1 >= limit->p1.min; clock.p1--) {
791 					i9xx_calc_dpll_params(refclk, &clock);
794 								&clock))
797 					this_err = abs(clock.dot - target);
799 						*best_clock = clock;
801 						max_n = clock.n;
852  * Returns a set of divisors for the desired target clock with the given
864 	struct dpll clock;
873 	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
874 		for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
875 			for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
876 			     clock.p2 -= clock.p2 > 10 ? 2 : 1) {
877 				clock.p = clock.p1 * clock.p2 * 5;
879 				for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
882 					clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
883 								     refclk * clock.m1);
885 					vlv_calc_dpll_params(refclk, &clock);
889 								&clock))
893 								&clock,
898 					*best_clock = clock;
910  * Returns a set of divisors for the desired target clock with the given
923 	struct dpll clock;
935 	clock.n = 1;
936 	clock.m1 = 2;
938 	for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
939 		for (clock.p2 = limit->p2.p2_fast;
940 				clock.p2 >= limit->p2.p2_slow;
941 				clock.p2 -= clock.p2 > 10 ? 2 : 1) {
944 			clock.p = clock.p1 * clock.p2 * 5;
946 			m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
947 						   refclk * clock.m1);
949 			if (m2 > INT_MAX/clock.m1)
952 			clock.m2 = m2;
954 			chv_calc_dpll_params(refclk, &clock);
956 			if (!intel_pll_is_valid(to_i915(dev), limit, &clock))
959 			if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
963 			*best_clock = clock;
999 		     const struct dpll *clock,
1028 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1031 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
1032 		WARN_ON(reduced_clock->p1 != clock->p1);
1034 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1035 		WARN_ON(reduced_clock->p1 != clock->p1);
1038 	switch (clock->p2) {
1052 	WARN_ON(reduced_clock->p2 != clock->p2);
1069 			      const struct dpll *clock,
1077 		hw_state->fp0 = pnv_dpll_compute_fp(clock);
1080 		hw_state->fp0 = i9xx_dpll_compute_fp(clock);
1084 	hw_state->dpll = i9xx_dpll(crtc_state, clock, reduced_clock);
1091 		     const struct dpll *clock,
1101 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1103 		if (clock->p1 == 2)
1106 			dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1107 		if (clock->p2 == 4)
1110 	WARN_ON(reduced_clock->p1 != clock->p1);
1111 	WARN_ON(reduced_clock->p2 != clock->p2);
1122 	 * both DPLLS. The spec says we should disable the DVO 2X clock
1139 			      const struct dpll *clock,
1144 	hw_state->fp0 = i9xx_dpll_compute_fp(clock);
1147 	hw_state->dpll = i8xx_dpll(crtc_state, clock, reduced_clock);
1255 static u32 ilk_dpll_compute_fp(const struct dpll *clock, int factor)
1259 	fp = i9xx_dpll_compute_fp(clock);
1260 	if (ilk_needs_fb_cb_tune(clock, factor))
1267 		    const struct dpll *clock,
1292 	 * The high speed IO clock is only really required for
1295 	 * the clock needlessly does no real harm, except use up a
1310 	dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1314 	switch (clock->p2) {
1328 	WARN_ON(reduced_clock->p2 != clock->p2);
1340 			     const struct dpll *clock,
1346 	hw_state->fp0 = ilk_dpll_compute_fp(clock, factor);
1349 	hw_state->dpll = ilk_dpll(crtc_state, clock, reduced_clock);
1369 				    "using SSC reference clock of %d kHz\n",
1541 				    "using SSC reference clock of %d kHz\n",
1590 				    "using SSC reference clock of %d kHz\n",
1628 				    "using SSC reference clock of %d kHz\n",
1668 				    "using SSC reference clock of %d kHz\n",
1904 	const struct dpll *clock = &crtc_state->dpll;
1930 	tmp = DPIO_M1_DIV(clock->m1) |
1931 		DPIO_M2_DIV(clock->m2) |
1932 		DPIO_P1_DIV(clock->p1) |
1933 		DPIO_P2_DIV(clock->p2) |
1934 		DPIO_N_DIV(clock->n) |
1938 	 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
2031 	const struct dpll *clock = &crtc_state->dpll;
2037 	m2_frac = clock->m2 & 0x3fffff;
2044 		       DPIO_CHV_P1_DIV(clock->p1) |
2045 		       DPIO_CHV_P2_DIV(clock->p2) |
2050 		       DPIO_CHV_M2_DIV(clock->m2 >> 22));
2079 	if (clock->vco == 5400000) {
2084 	} else if (clock->vco <= 6200000) {
2089 	} else if (clock->vco <= 6480000) {
2128 	/* Enable back the 10bit clock to display controller */
2136 	 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
2267 	/* Disable 10bit clock to display controller */