Lines Matching refs:clock
32 static int set_input_clock(struct echoaudio *chip, u16 clock);
94 /* Map the DSP clock detect bits to the generic driver clock detect bits */
150 48 kHz, internal clock, S/PDIF RCA mode */
162 u32 control_reg, clock, base_rate;
168 /* Only set the clock for internal mode. */
171 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
182 clock = 0;
186 clock = GML_96KHZ;
189 clock = GML_88KHZ;
192 clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1;
195 clock = GML_44KHZ;
198 clock |= GML_SPDIF_SAMPLE_RATE0;
201 clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 |
205 clock = GML_22KHZ;
208 clock = GML_16KHZ;
211 clock = GML_11KHZ;
214 clock = GML_8KHZ;
219 clock = LAYLA24_CONTINUOUS_CLOCK;
240 control_reg |= clock;
245 "set_sample_rate: %d clock %d\n", rate, control_reg);
252 static int set_input_clock(struct echoaudio *chip, u16 clock)
256 /* Mask off the clock select bits */
261 /* Pick the new clock */
262 switch (clock) {
288 "Input clock 0x%x not supported for Layla24\n", clock);
292 chip->input_clock = clock;
339 /* Set clock to "internal" if it's not compatible with the new mode */