Searched refs:for_each_set_bit (Results 51 - 75 of 706) sorted by last modified time

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/linux-master/drivers/gpu/drm/xe/
H A Dxe_irq.c304 for_each_set_bit(bit, intr_dw + bank, 32)
308 for_each_set_bit(bit, intr_dw + bank, 32) {
H A Dxe_gt_topology.c112 for_each_set_bit(bit, &mask, 32) {
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dr535.c1394 for_each_set_bit(head, &mask, 8)
1599 for_each_set_bit(i, &disp->head.mask, disp->head.nr) {
1608 for_each_set_bit(i, &disp->sor.mask, disp->sor.nr) {
1628 for_each_set_bit(i, &mask, 32) {
/linux-master/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_smp.c225 for_each_set_bit(blk, *assigned, cnt) {
292 for_each_set_bit(pipe, &state->assigned, sizeof(state->assigned) * 8) {
318 for_each_set_bit(pipe, &state->released, sizeof(state->released) * 8) {
/linux-master/drivers/gpu/drm/i915/selftests/
H A Dintel_uncore.c313 for_each_set_bit(offset, valid, FW_RANGE) { function
/linux-master/drivers/gpu/drm/i915/gvt/
H A Ddisplay.c638 for_each_set_bit(event, irq->flip_done_event[pipe],
/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_workarounds.c1329 for_each_set_bit(i, &gt->info.mslice_mask, GEN12_MAX_MSLICES)
H A Dintel_gt_mcr.c149 for_each_set_bit(i, &fuse, 3)
H A Dintel_gt_irq.c159 for_each_set_bit(bit, &intr_dw, 32) {
/linux-master/drivers/gpu/drm/i915/gem/selftests/
H A Dhuge_pages.c515 for_each_set_bit(bit, &supported, ilog2(I915_GTT_MAX_PAGE_SIZE) + 1) {
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.c370 for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
H A Dintel_display_power.c1165 for_each_set_bit(i, &abox_regs, sizeof(abox_regs))
1618 for_each_set_bit(i, &abox_mask, sizeof(abox_mask))
1622 for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) {
/linux-master/drivers/gpu/drm/
H A Ddrm_print.c268 for_each_set_bit(i, &value, nbits) {
/linux-master/drivers/gpu/drm/display/
H A Ddrm_dp_tunnel.c1650 for_each_set_bit(id, &move_mask, BITS_PER_TYPE(move_mask))
/linux-master/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_pipeline.c54 for_each_set_bit(i, &avail_comps, 32) {
266 for_each_set_bit(id, &avail_comps, 32) {
280 for_each_set_bit(id, &supported_inputs, 32) {
313 for_each_set_bit(id, &avail_comps, 32) {
373 for_each_set_bit(id, &avail_comps, 32) {
/linux-master/drivers/gpu/drm/amd/pm/swsmu/
H A Dsmu_cmn.c698 for_each_set_bit(dep_bit, &dep_status, 32)
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dgmc_v9_0.c483 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
511 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
960 for_each_set_bit(i, adev->vmhubs_mask,
2334 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
H A Damdgpu_umc.h50 for_each_set_bit((node_inst), &(adev->umc.active_mask), adev->umc.node_inst_num)
/linux-master/drivers/acpi/
H A Dplatform_profile.c41 for_each_set_bit(i, cur_profile->choices, PLATFORM_PROFILE_LAST) {
/linux-master/arch/x86/kvm/mmu/
H A Dmmu.c1793 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
/linux-master/arch/riscv/kvm/
H A Dvcpu_sbi.c221 for_each_set_bit(i, &reg_val, BITS_PER_LONG) {
H A Dvcpu_onereg.c654 for_each_set_bit(i, &reg_val, BITS_PER_LONG) {
H A Dvcpu_pmu.c175 for_each_set_bit(i, &cmask, BITS_PER_LONG) {
518 for_each_set_bit(i, &ctr_mask, RISCV_MAX_COUNTERS) {
589 for_each_set_bit(i, &ctr_mask, RISCV_MAX_COUNTERS) {
844 for_each_set_bit(i, kvpmu->pmc_in_use, RISCV_KVM_MAX_COUNTERS) {
H A Daia.c468 for_each_set_bit(i, &hgei_mask, BITS_PER_LONG) {
/linux-master/arch/powerpc/platforms/powernv/
H A Dpci-sriov.c293 for_each_set_bit(window_id, iov->used_m64_bar_mask, MAX_M64_BARS) {

Completed in 426 milliseconds

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